1.04 GBd low EMI digital video interface system using small swing serial link technique

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998

1.04 GBd Low EMI Digital Video Interface System Using Small Swing Serial Link Technique Kyeongho Lee, Student Member, IEEE, Yeshik Shin, Student Member, IEEE, Sungjoon Kim, Student Member, IEEE, Deog-Kyoon Jeong, Member, IEEE, Gyudong Kim, Bruce Kim, and Victor Da Costa

Abstract—In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electro magnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal–oxide–semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640 2 480 pixels) up to XGA (1024 2 768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd. Index Terms—Digital video interface, electromagnetic interference, flat panel system, low-voltage swing serial interface.

I. INTRODUCTION

T

ODAY the resolution of flat panel displays is increasing rapidly. Beyond the SVGA (800 600), which requires 768), which requires a total of 120 MB/s, XGA (1024 a total of 195 MB/s, is ready for production by many flat panel manufacturers. The biggest bottleneck for designing a high-resolution flat panel display interface is the unavoidable increase of electro magnetic interference (EMI) during digital video signal transmission. As shown in Fig. 1, a conventional interface, which directly connects the host LCD controller to a flat panel display, requires numerous parallel lines and transmits a full-swing signal on each line. As the resolution of flat panel display increases, the required video data transmission rate is increased as well. However, the huge number of parallel signal lines and the full-swing signal drastically increases the EMI effects as the video signal transmission rate increases. Consequently, a new video signal interface for high-resolution flat panel systems that can overcome EMI problems is needed. In this paper, we propose a new high-speed, low-voltage swing video signal interface that can overcome such EMI problems. The proposed system uses only four cable pairs—three for redgreen-blue (RGB) data channels and one for the clock channel. Each data channel transmits data using low-voltage swing Manuscript received August 13, 1997; revised October 16, 1997. K. Lee, Y. Shin, S. Kim, and D.-K. Jeong are with the Department of Electronics Engineering and the Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea. G. Kim, B. Kim, and V. Da Costa are with Silicon Image, Inc., Cupertino, CA 95014 USA. Publisher Item Identifier S 0018-9200(98)02242-2.

serial data signaling. The maximum data rate per channel is 1.04 GBd, enabling XGA resolution with just three RGB data channels. Small swing serial data transmission and decreased line count to four pairs can reduce EMI during high-rate data transmission. To support high data rates of up to 1.04 GBd and to overcome channel-to-channel skew problems caused by cable length mismatches, a high-speed skew-insensitive data recovery system is required. This paper includes a digital phase-locked loop (PLL) that enables robust skew-insensitive data recovery of up to 1.04 GBd. II. SYSTEM ARCHITECTURE As shown in Fig. 2, the transmitter is composed of three video data channels, a common PLL, and a swing control circuit. Each channel of the transmitter is composed of a data capture logic, a transition-minimized dc-balancing 8B/10B coder [1], and a serializer. As shown in Fig. 3, the receiver is composed of three channels, a common PLL, an impedancematching circuit, and an output interface logic. Each channel of the receiver is composed of a three-times data oversampler, a digital PLL, a byte-alignment logic, an interchannel synchronization logic, and a decoder. Each channel of the transmitter receives 8-b video data, 2-b control signals, and an DE (data enable signal) from the LCD controller. When the DE is high, 8-b video data is coded into 10-b transition-minimized dcbalanced data by the 8B/10B coder [1]. The 8B/10B coder not only minimizes the number of transitions, but also balances the dc value of the 10-b coded data which enables long length cable transmission (via transformer coupling) and optical transmission. When the DE is low, the 2-b control signal is coded into one of four 10-b special character sets. A serializer receives 10-b coded data from the 8B/10B coder and converts the 10-b coded data, which is synchronized to a 100 MHz system clock to a 1 GBd serial data stream, and transmits the serial data stream onto the cable. The swing control circuit allows adjustment of the voltage swing of the serial data stream depending on the distance and the noise. Voltage swing can be set to the minimum level allowed for a given noise level to minimize the EMI. Fig. 4 shows the timing diagram of serial data transmission. During the active data period (when the DE is high), transition-minimized dc-balanced video data is serialized and transmitted. During the blank period (when the DE is low), control signals, which are coded into 10-b special characters, are serialized and transmitted. The 10-b special characters are used for clock recovery and byte alignment and decoded to the original control signals in the receiver. The three-times data oversampler of the receiver accepts the

0018–9200/98$10.00  1998 IEEE

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998

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Fig. 1. Structure of conventional flat panel display system.

Fig. 2. Block diagram of transmitter.

serial data stream from the cable and samples one serial bit three times. The digital PLL continuously keeps track of the center of each serial bit, which results in skew-insensitive data recovery. A byte-alignment logic finds the start position of a 10-b frame from the recovered data. By using a 10-b special character set that has a controlled number of transitions for data recovery and byte-alignment information, the phase tracking and the byte alignment are accomplished during the blank period (when the DE is low). A decoder block decodes the 10-b coded data to generate 8-b original video data during the data-active period, and decodes 10-b special characters to generate 2-b control signals during the blank period. III. TRANSITION-MINIMIZING DC-BALANCING CODER As shown in Fig. 4, for embedding control signals into the data line, a transition-minimizing dc-balancing 8B/10B coding

scheme [1] is used. Each encoder of transmitter encodes 8-b graphic data, DE, and 2 b of control signals. Three functionally identical encoders are used to transmit 24-b graphic data, 6-b control signals, and a DE signal. Control signals are assumed to change only during the blank period (when the DE is low), therefore the level of the control signals are assumed to be constant during the active data period (when the DE is high). In the active data period, each encoder converts 8-b graphics data into the transition-minimized dc-balanced 10-b 256 data codes [1] which can support low-power operation and guarantees the dc balancing for long cable length transmission. In the blank period, four kinds of special characters are used for the level encoding of the 2-b control signal. These special characters are characterized by the sufficient number of transitions for the phase synchronization of digital PLL in the receiver part. All special characters also have the information of the start

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Fig. 3. Block diagram of receiver.

Fig. 4. Timing diagram of video data and control signal transmission.

bit location for byte alignment. Table I shows the four kinds of special character sets. The decoder can separate the special character sets from the 256 data codes because the number of transitions of each special character is larger than that of the 256 data codes [1].

TABLE I SPECIAL CHARACTER SETS

IV. CIRCUIT DESCRIPTION A. Swing Control Circuit and Small Swing Data Driver Fig. 5 shows the detailed circuit diagram of a swing control circuit and a small swing data driver. The feedback loop in and the a swing control circuit continuously equalizes internal reference voltage , which is fixed at V, by adjusting the current level of external resistor. The current

control signal is converted into a swing control signal which controls the current source in the small swing data driver. With the scaled sizing shown in Fig. 5, the output current level of the data driver is ten times that of an external resistor. As the value of external resistor decreases, the current level needed to equalize and increases, which in turn increases the voltage swing of the small swing signal. The formula to

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Fig. 5. Circuit diagram of swing control circuit and small swing data driver.

determine voltage swing is shown in Fig. 5. To obtain a 400mV voltage swing, for example, a 625 external resistor is needed if the characteristic impedance of the cable is 50 . The data driver sends one serial bit at the every rising edge of ECK [0 : 3]. The four-phase clocking reduces the complexity of clock distribution and the amount of output loading compared with previous ten-phase clocking schemes [2], [3]. B. Data Recovery Operation of Digital PLL Digital PLL’s using data oversampling techniques were previously developed in [2], [4], and [5] with 40-, 30-, and 32-phase PLL clocks, respectively. References [2], [4], and [5] require huge computing hardware for phase detection because they need more than 30-phase clock distribution and they calculate the transition numbers of all phases to find the correct phase. In contrast, the proposed digital PLL uses only 12phase PLL clocks, which reduces the complexity of clock distribution and reduces the size of phase-detection hardware using fine feedback structure with a proposed phase-detecting cell and phase-aligning window. Fig. 6 shows the detailed block diagram of the digital PLL, a common charge pump PLL, and a data oversampler. A digital PLL is composed of a phase-aligning window, a phase-detection logic, a digital loop filter, and a phase-adjusting FSM (finite state machine). The proposed data recovery system receives the MHz reference clock and 10 Mbd serial data from the transmitter part. MHz, The common charge pump PLL generates the 2.5 12-phase clocks (CK[0 : 11]). The data oversampler samples

Fig. 6. Detailed block diagram of the digital PLL, a common charge pump PLL, and a data oversampler.

one serial bit by three times with the rising edges of the 12-phase clock CK[0 : 11]. The 4-b received serial data are converted into the 12-b oversampled data S[0 : 11] by the data oversampler. Only four bits sampled at the center position of an one bit duration are continuously selected as recovered 4-b data by the digital PLL. 1) Phase-Aligning Window: Fig. 7 shows the operation of the phase-aligning window. The phase-aligning window receives 12-b oversampled data (S[0 : 11]) and two extra oversampled data (SP[11] and SN[0]) from the data oversampler. S[0 : 11] is the 12-b oversampled data of the current cycle,

When PHASE[0:2] = 100 (Phase0) When PHASE[0:2] = 010 (Phase1) When PHASE[0:2] = 001 (Phase2) A[N] = S[N+1] N = A[0] = SP[11] A[N] = S[N] N= A[N] = S[N-1] N= A[11] = SN[0]

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Fig. 7. Operation of a phase-aligning window.

Fig. 8. Block diagram of a phase-detection block.

SP[11] is the last oversampled bit (S[11]) of the previous cycle, and SN[0] is the first oversampled bit (S[0]) of the next cycle. The phase-aligning window is controlled by the PHASE[0 : 2] signal generated by the phase-adjusting FSM and generates 12b phase-aligned data A[0 : 11]. A[0 : 11] which are determined as shown at the bottom of the previous page. The overall mechanism of the digital PLL continuously keeps track of the A[0 : 11] and makes A[0 : 11] become exactly phase aligned. ], and The exact phase alignment means that A[ ], A[ ], where is 0, 1, 2, 3, become 3-b oversampled A[ data, which comes from one serial bit, which also means that ] that is, A[1], A[4], A[7], and A[10], can be selected A[

as the 4-b recovered data which are sampled at the exact center position of the one bit duration. 2) Phase-Detection Block: Fig. 8 shows the block diagram of the phase-detection block. As shown in Fig. 8, the phasedetecting block is composed of four phase-detecting cells and an up–down decision logic. The phase-detecting cell , where is 0, 1, 2, 3, receives 3-b phase-aligned data, which are ], and A[ ], and decides whether A[ ], A[ the phase is exactly aligned or not. When a phase is found to be exactly aligned, both UP[ ] and DOWN[ ], which are outputs of the phase-detecting cell , are set to “0.” When a phase is found to be misaligned, and moving to a

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N

Fig. 9. Phase-detecting operation (a) detailed circuit of the phase-detecting cell , (b) phase is exactly aligned, (c) phase is misaligned and moving to lower phase is necessary, and (d) phase is misaligned and moving to higher phase is necessary.

higher (lower) phase is required, UP[ ] is set to “1”(“0”) and DOWN[ ] is set to “0”(“1”). Fig. 9 shows the detailed description of the phase-detecting operation. Fig. 9(a) shows the detailed circuit of the phase-detecting cell . Fig. 9(b) shows the case when a phase is exactly aligned. In this case, A[ ], A[ ], A[ ] are “000” or “111” and a change of phase is not needed, which results in setting both UP[ ] and DOWN[ ] to “0.” Fig. 9(c) shows the case when a phase is misaligned and moving to a lower phase, such as phase2 phase1, phase1 phase0, phase0 phase2, is necessary. This case occurs when A[ ], A[ ], A[ ] are “001” or “110,” which results in setting UP[ ] to “0” and DOWN[ ] to “1.” Fig. 9(d) shows the case when a phase is misaligned and moving to a higher phase, such as phase0 phase1, phase1 phase2, phase2 phase0, is necessary. This case occurs when A[ ], A[ ], A[ ] are “011” or “100,” which results in setting UP[N] to “1” and DOWN[ ] to “0.” The up–down decision logic shown in Fig. 8 receives four UP signals (UP[0 : 3]) and four DOWN signals (DOWN[0 : 3]) from the four phase-detecting cells. Only when the number of 1’s in the four UP (DOWN) signals is larger than or equal to two is the UPF (DOWNF) signal set to “1.” By using the proposed phase-detecting scheme, calculating the transition numbers of all phases [2], [4], [5] to find the correct phase is not necessary. This can drastically reduce the amount of computing hardware needed for finding the correct phase in the oversampling data recovery system. V. EXPERIMENTAL RESULTS 3) Phase Adjustment: The digital loop filter receives UPF and DOWNF signals from the phase-detection block. Only when consecutive four UPF (DOWNF) signals are detected is UPT(DOWNT), which is one of the output signals of digital loop filter, set to “1.” In other cases, both UPT and DOWNT

are set to “0” and the HOLD signal, which is also one of the output signals of digital loop filter, is set to “1.” The purpose of the digital loop filter is to smooth the phase change of DPLL and to obtain the stable condition of the negative feedback loop. Three low-voltage swing data links can support 312 MB/s GBd ) which can sufficiently support up to ( 768) resolution at 60 Hz refresh rate, which XGA (1024 requires at least 195 MB/s. Fig. 10(a) shows the 1.042 GBd eye diagram. The eye diagram is measured on the following conditions. The transmitter is integrated on the graphics controller board. The transmitter receives 24-b graphic data which are synchronized to a 104 MHz system clock from twisted-pair cable is used. the graphics controller. A 100 The voltage swing is set to 400 mV. The 1.042 GBd eye diagram is measured at the end of a 2 m cable. Fig. 10(b) shows the PLL jitter histogram. A graphic board system that includes a transmitter and a XGA panel system that includes a receiver are used for PLL jitter measurement. The system clock received from the graphics controller is set to 65 MHz (XGA mode frequency). The measured input clock jitter is peak-to-peak 1.5 ns. The measured rms value of receiver PLL jitter is 11.94 ps at the XGA mode frequency (65 MHz 2.5). Fig. 11 shows the EMI measurement result. A notebook system including a proposed transmitter and receiver is used for EMI measurements. The amount of EMI emerging from the proposed video interface is measured at the distance of 2 m. Voltage swing is set to 350 mV by setting the external resistor to 714 . Fig. 11 shows the current European EMI compliance limit (CISPR 22B) and FCC Part 15 limit. Fig. 11 shows that the proposed interface included in the notebook system passes both limits on the condition that the voltage swing is set to 350 mV, the data rate is 650 Mb/s, and a 100 shielded twistedpair cable is used. Table II shows the chip characteristics. The

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(a) Fig. 10.

(b)

(a) 1.042 GBd eye diagram measured at the end of 2 m cable and (b) PLL jitter histogram.

TABLE II CHIP CHARACTERISTICS

Fig. 11.

The EMI compliance with European (CISPR 22B) and FCC limit.

worst case power consumption of the transmitter and receiver is less than 500 mW, which is much smaller than comparable speed interface systems [2], [4], [6]. The block size occupied by a digital PLL is 490 m 460 m. The BER (bit error rate) is measured by sending a pseudorandom bit sequence , and comparing it with (PRBS), the period of which is the received sequence. A 2 m, 100 twisted-pair is used for

BER measurements. The measured BER is less than 10 on the condition that the data rate is 1.042 GBd and the voltage swing is 400 mV. VI. CONCLUSIONS Only four cable pairs are needed to support up to XGA GBd resolution. High bandwidth up to 1.04 GBd ( MB/s) and control signal embedding schemes drastically reduce the number of signal lines. Low-voltage

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differential swing data transmissions and the reduced number of signal lines allow the reduction of the EMI level compared with conventional parallel wires. Skew insensitivity is realized in the 1 GBd link by recovering data through the proposed data recovery scheme. Standard CMOS (complimentary metaloxide-semiconductor) technology and low cable cost enable the low-cost implementation of high-resolution flat panel display systems. REFERENCES [1] Y. Shin K. Lee, D.-K. Jeong, and D. D. Lee, “Transition-controlled digital encoding and signal transmission system,” U.S. patent pending.

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[2] K. Lee, S. Kim, G. Ahn, and D.-K. Jeong, “CMOS serial link for fully duplexed data communication,” IEEE J. Solid-State Circuits, vol. 30, pp. 353–363, Apr. 1995. [3] A. Fiedler, R. Mactaggart, J. Welch, and S. Krishnan, “A 1.0625 Gbps transceiver with 2X-oversampling and transmit signal pre-emphasis,” in ISSCC 1997 Digest Tech. Papers, Feb., pp. 238–239. [4] S. Kim, K. Lee, D.-K. Jeong, D. D. Lee, and A. Nowatzyk, “An 800 Mbps multi-channel CMOS serial link with 3 X oversampling,” in Proc. IEEE Custom Integrated Circuit Conf., 1995, pp. 451–454. [5] M. Bazes and R. Ashuri, “A novel CMOS digital clock and data decoder,” IEEE J. Solid-State Circuits, vol. 27, pp. 1934–1940, Dec. 1992. [6] T. H. Hu and P. R. Gray, “A monolithic 480 M parallel AGC/decision/clock-recovery circuit in 1.2-m CMOS,” IEEE J. Solid-State Circuits, vol. 28, pp. 1314–1320, Dec. 1993.