A 1W Class-D Audio Power Amplifier in a 0.35μm CMOS Process

A 1W Class-D Audio Power Amplifier in a 0.35m CMOS Process Kin-Keung Lee, Yelin Wang, Qingyuan Zhang and Henrik Sjöland Department of Electrical and Information Technology, Lund University, Box 118, 221 00 Lund, Sweden

Abstract — A fully integrated class-D audio power amplifier for mobile applications is presented. The amplifier is realized in a 0.35μm CMOS process featuring 3.3V and 5V transistors. To reduce the outof-band noise generation, possibly eliminating the need of an output filter, the Double Sided Natural Sampling (DSNS) pulse width modulation (PWM) scheme is used at a designed carrier frequency of 384kHz. By using a 5V full bridge, a maximum output power of 1W (rms) was measured in a 7.5 load at 1% THD+N and an efficiency of 80%. The THD+N was 0.24% at 500mW output, and 0.15% in minimum. The total chip area is 2.55mm2 including pads. This chip was designed and simulated with Cadence IC design tools as a student project in the course IC Project and Verification at Lund University.

I. INTRODUCTION In mobile phones, long time between battery re-charges is one of the key factors to achieve user satisfaction. At the same time, there is a trend towards higher audio output power. It is therefore important to use an audio power amplifier with highest efficiency possible. Due to the low efficiency, especially at low output power levels, conventional class-AB audio power amplifiers are therefore not attractive. High efficiency is also important since it reduces the heat that is produced by the chip. This simplifies chip packaging and allows more freedom in the design of the phone enclosure. While having a high efficiency and being able to produce high output power, the amplifier must of course also provide good sound quality, that is the level of noise and distortion should be as low as possible. In addition, the amplifier must have a small physical size and a low production cost.

To address these requirements, a class-D audio power amplifier was realized in a 0.35μm CMOS process. The process featured both 3.3V and 5V transistors, where the 5V devices were used in the output stage to achieve high power. This enabled an output power of 1W (rms) in 7.5 at 1% total harmonic distortion plus noise (THD+N). The efficiency was 80% at 1W, but more importantly, it was also high at reduced output power, with 65% at 100mW, corresponding to 10dB back-off. This is the major advantage of class-D, since the efficiency of a class-B amplifier is proportional to the output amplitude, and at 10dB back-off its theoretical maximum is therefore below 25%. The THD+N was 0.24% at 500mW. The drawback of class-D amplifiers is the generation of out-of-band noise, requiring an output filter which cannot be integrated on chip. The DSNS scheme is therefore adopted to produce the PWM signal. Its three level output reduces the out-of-band noise compared to a single-sided counterpart [1]. The lower noise level relaxes the filtering requirements and makes it possible to use the speaker as the only filtering element [2]. The solution then also satisfies the requirement of small physical size, being a fully integrated amplifier with a chip area of just 2.55mm2.

II. CIRCUIT DESIGN A fully-differential structure is necessary to implement the DSNS scheme. It provides the benefits of better rejection of disturbances, cancellation of even-order distortions, and doubled voltage signal swing. The architecture of the class-D amplifier is shown in Fig. 1. A feedback loop is used to suppress power supply noise and distortion. A loop with a single dominant pole realized by an integrator is used because of its inherent stability.

Fig. 1 Architecture of the class-D amplifier

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Fig. 2. Schematic of fully differential 2-stage folded-cascode amplifier The schematic of the fully differential operational amplifier used in the input stage and in the integrator is depicted in Fig. 2. A 2-stage folded-cascode topology is employed to provide high DC gain and output swing. In the first stage, the supply voltage is 5V to maximize the input swing and thick gate transistors are utilized to prevent gate oxide breakdown. The comparator is shown in Fig. 3. The required operating frequency is just a few MHz, which enables the usage of an OTA to make a high precision comparator. The input common-mode voltage range must be rail-to-rail. This is achieved by using an nMOS and a pMOS differential input pair in parallel [3]. The triangular wave generator (oscillator) is one of the most critical building blocks, since its linearity directly affects the linearity of the complete amplifier. Fig. 4 shows the schematic of the triangular wave generator [4]. The comparators and the latches can be considered as a high performance Schmitt Trigger, which controls the charge pump to charge and discharge the capacitor. The result is a relaxation oscillator with high linearity. To further increase the linearity, switches SW1 and SW2 are added to make sure that the current sources never turn off [5]. The charge pump is also connected to the 5V supply to provide better headroom. The efficiency of class-D amplifiers can be severely reduced by current shoot-through of the power bridge.

Dead-time generators are inserted to eliminate this harmful current. They generate a delay to ensure that the nMOS and pMOS in the same side of the bridge are never on simultaneously. The result is that a dead-time is introduced, during which both transistors are off. This dead-time must be sufficiently long to ensure that no shoot-through occurs in any process corner. At the same time, it must not be any longer, as it affects the THD performance of the amplifier [6]. The schematic of the delay circuit is shown in Fig. 5. This structure was adopted because of its simplicity, more advanced structures can be found in e.g. [7, 8]. The theoretical maximum efficiency, accounting only for ohmic losses in the output bridge, is given by:

=

R LOAD R LOAD + R ON -pMOS + R ON -nMOS

(1)

To achieve a high efficiency with a low load resistance, the nMOS and pMOS in the output bridge must thus be very large to minimize their on-resistance. However, this increases the size of the chip and thereby the fabrication cost. Moreover, the parasitic capacitances and thereby the

Fig. 4. Schematic of triangular wave generator

Fig. 3. Schematic of comparator with rail-to-rail input range

Fig. 5. Schematic of dead-time generator

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Fig. 6. THD+N versus output power at 1kHz Fig. 8. 8192 point FFT at 1kHz 500mW output

lower output power. At 100mW the efficiency is 65%. Fig. 8 shows the frequency spectrum when the output power is 500mW at 1kHz. A die microphotograph of the class-D amplifier is shown in Fig. 9. The chip area, including pads, is 2.55mm2 and the output bridges occupy about 22% of the total chip area.

IV. CONCLUSION

Fig. 7. Efficiency versus output power

switch losses increase. As a compromise the RON-pMOS and the RON-nMOS are set to 0.4 each, resulting in a maximum efficiency of 90% according to eq. (1). As the total efficiency was 80%, this indicates a good balance between ohmic losses and switch losses, each reduces the efficiency by 10%. To make use of the properties of the fully differential architecture, a common-centroid layout technique was used to achieve good matching between critical elements. To prevent coupling, important signal wires were also shielded and the supplies of sensitive analog circuits were separated from the supply of the digital circuits and the output stages. To reduce substrate noise, the output bridge was separated by a guard ring connected to a dedicated ground pad.

A fully integrated class-D audio power amplifier targeting mobile applications has been realized in a 0.35m CMOS process. It can deliver 1W (rms) into a 7.5 load with a maximum efficiency of 80% and a THD+N of 1%. The THD+N is 0.24% at 500mW output and 0.15% in minimum. The chip was designed as a student project by the first three authors under supervision of the fourth author, in the course IC-project and verification at Lund University.

III. EXPERIMENTAL RESULTS An Audio Precision System Two audio analyzer was used to measure the THD+N and efficiency. For measurement purposes, a second order LC lowpass filter with a cutoff frequency of 27kHz was used before the load. Fig. 6 shows the THD+N versus output power. As can be seen, the amplifier can deliver 1W (rms) into a 7.5 load with 1% THD+N. The THD+N is 0.24% at 500mW output and 0.15% in minimum. Fig. 7 shows the efficiency versus output power. The maximum efficiency is 80%, at an output power of 1W. The efficiency remains high also at

Fig. 9. Die photograph

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ACKNOWLEDGEMENT

[4]

H. P. Forghani-Zadeh and G. A. Rincón-Mora, “Low-Power CMOS Ramp Generator Circuit for DC-DC Converters,” J. Low Power Electronics, vol. 2, no. 3, pp. 437-441, Dec. 2006.

[5]

A. C. Y. Lin, D. K. Su, R. K. Hester, and B. A. Wooley, “A CMOS oversampled DAC with multibit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems,” IEEE J. SolidState Circuits, vol. 41, pp. 868-875, Apr. 2006.

[6]

P. M. I. D. Mosely and C. Bingham, “Effect of dead time on harmonic distortion in class-D audio power amplifiers,” Electronic Letters, vol. 35, no. 12, pp. 950–952, 1999.

[7]

A. Axholt, F. Oredsson, T. Petersson, J. Wernehag, and H. Sjöland, "A 0.25W fully integrated class-D audio power amplifier in 0.35m CMOS," in Proc. Norchip 2007, pp. 1-4.

[8]

M. Berkhout, “An integrated 200-W class-D audio amplifier,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1198–1206, Jul. 2003.

The authors would like to express their gratitude to Ericsson Mobile Platforms in Lund, Sweden, for financial support enabling fabrication of the chip.

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