Int. J. Electron. Commun. (AEÜ) 64 (2010) 813 – 818 www.elsevier.de/aeue
A 2.4-GHz 0.18-m CMOS Class E single-ended switching power amplifier with a self-biased cascode Sohiful Anuar Zainol Murad∗ , Ramesh K. Pokharel, Haruichi Kanaya, Keiji Yoshida, Oleg Nizhnik Graduate School of Information Sciences and Electrical Engineering, Kyushu University, Motooka 744, Nishi-ku, Fukuoka 819-0395, Japan Received 29 January 2009; accepted 12 June 2009
Abstract This paper describes the design of a 2.4-GHz CMOS Class E single-ended power amplifier (PA) for WLAN applications in TSMC 0.18-m CMOS technology. The Class E PA proposed in this paper employs cascode topology with a self-biasing technique to prevent device stress and to decrease the requirement for additional bond pads. Further, all inductors are realized by bondwires for high PA performance. The post-layout simulation results indicate that the PA delivers 23 dBm output power and 44.5% power added efficiency with 3.3 V power supply into a 50 load. 䉷 2009 Elsevier GmbH. All rights reserved. Keywords: CMOS; Class E power amplifier; Cascode; Self-biasing; Output power
1. Introduction Recently, wireless devices are becoming more and more popular in many applications and the need to build compact, low cost and low power blocks arises. In addition, more and more signal processing is done in CMOS. Therefore, a single chip transceiver demands an integrated CMOS power amplifier (PA). However, as the down-scaling of MOS devices continues, the CMOS PA is not the optimum technology of choice due to the problem such as low oxide breakdown voltage, low current drive capability, substrate coupling and low quality and high tolerances of on chip passives [1,2]. This makes CMOS PA design and implementation a major challenge particularly when designing in GHz frequencies range. Most CMOS PAs that are published choose differential topology to obtain high linearity watt range [3]. Since the ∗ Corresponding author. Tel./fax: +81 92 802 3720.
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components driven by the PA and the antenna input are still single-ended, such topology still requires a balun or transformer to be integrated in differential topology [3–5]. Therefore, the design become complicated and occupies large size on chip. In CMOS, Class E PA is the most favored candidates among all classes of switching mode power amplifiers (Classes D and F) due to their circuit simplicity and excellent power added efficiency (PAE). High PAE are important because PAs typically dominate the power consumption in a wireless transceiver system. However, the linearity is very poor due to the switching nature. Therefore, the systems with constant envelope modulation scheme such as FSK (or FM) are most suitable for switched-mode amplifiers. Furthermore, signal swing in a Class E PA can be two or three times the supply voltage that seriously stresses MOS devices. Safe device operating conditions can be guarantee by decreasing supply voltage is usually less than the maximum available, at the price of efficiency degradation [1,6,7]. Cascode configuration have been used to overcome device stress problem in MOS devices [1,8]. However, a
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Vdd
Ldc
Vin
Cs
M1
Ls
Cshunt
Lx
Ropt
Matching Vout Network 50Ω
Fig. 1. Basic Class E PA.
conventional cascode amplifier, the gate of common gate (CG) transistor is directly connected to the supply voltage by means extra bond pad is required [1]. In this paper, Class E single-ended switching PA is designed at 2.4-GHz using TSMC 0.18-m CMOS process. The propose design implemented cascode topology with self-biasing technique to overcome the device stress and to decrease the additional bond pads requirement. All inductors are realized by bonding wires for high quality factor (Q) inductors and for reducing the chip size. The driver stage is biased in Class A and the effects of bonding wires are also taken into account in the simulation. The outline of this paper is as follows. In Section 2, the basic operation of a Class E PA is briefly discussed. Section 3 presents the realization of bonding wire inductors with simulation results. The proposed design of Class E singleended PA with self-biased cascode is presented in Section 4. Section 5 presents the simulation results of proposed Class E PA and final conclusions are given in Section 6.
2. Class E power amplifier The first Class E PA in a high efficiency was introduced by Sokal in 1975 [9]. Fig. 1 shows the basic Class E PA [10]. The Class E PA consists of an active device M1, a shunt capacitance Cshunt, a series resonance circuit Cs–Ls, and an excess inductance Lx. Both Cshunt and Lx, together with Ldc, shape the current and voltage waveforms across the switch as shown in Fig. 2. The Class E PAs achieved significantly higher efficiency as high as 100% in the ideal case [2]. The component values can be calculated using the equations in [1,9]. The choice of Class E PA depends on several advantages. First, switching mode PAs such as Class E have generally higher efficiency due to the strong switching operations and zero voltage switching (ZVS) conditions, which permits to reduce capacitance discharge losses. Second, as the supply voltage decrease, also decrease the value of the optimum load required to achieve a specific value for output power. Therefore, the matching network transformation ratio from 50 will increase, causing more losses in the matching network. This effect is less pronounced in Class E PA making
Fig. 2. Ideal drain voltage and drain current waveform of Class E PA. R1
R2 R3
CHIP
L1
L3
PCB
L2
Fig. 3. Lumped-element model of a bondwire inductor.
it more suitable for low voltage operation. Third, the circuit topology incorporating the transistor output capacitance is very simple and easy to implement. However, Class-E PAs feature high peak voltage and rms current waveforms, which constitute a serious stress for the devices. For this reason, the supply voltage is usually lowered compared to its maximum to assure safe operating conditions, thus degrading the overall efficiency because a lower load resistance should be matched for the same output power. Therefore, this paper implemented Class E PA based on the cascode topology to allow a higher supply voltage without enhancing the device stress.
3. Inductor realization CMOS on-chip spiral inductors are well known for their low Q owing to high substrate loss and high parasitics [11]. Furthermore, spiral inductors occupy a large space on-chip and also encounter self-resonance in microwave frequency band, which permits their use beyond that frequency. Therefore, bondwire inductors are used in this design to implement high Q inductors to obtain a higher PAE. Although bondwire inductors provide a high Q, predetermination of bondwire inductance is difficult. Since the inductance is sensitive to bonding geometry, the bondwires need to be modeled accurately before they can be used as inductors in a power amplifier. To obtain an accurate model, all the elements used in the inductor model need to be well defined, and modeled according to the electromagnetic theory and their physical structure. Fig. 3 shows a lumpedelement model for a bondwire inductor. The model consists
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140
100 Im (2 mm) Im (5 mm) Re (2 mm) Re (5 mm)
100
Ld
80
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70 60
80
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60
Real Part
Imaginary Part
120
R3 M3
RF_IN L1
C2
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Co
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10 1.0
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Bond Ldc wire Ls+Lo Lext Cs RF_OUT
C3
30
40
Vdd
Vdd
Bond wire
90
815
0 5.0
Vbias1
Lsd
Vbias2 Lgnd Bond wires
Fig. 4. Z-parameter for bonding wire inductor model.
Fig. 6. Complete schematic of the proposed Class E single-ended PA.
85 Q of 5mm bondwire Q of 2mm bondwire
Quality Factor
75 65 55 45 35 25 1.0
1.5
2.0
2.5 3.0 3.5 Frequency (GHz)
4.0
4.5
5.0
Fig. 5. Q of a bondwire inductor simulated using Cadence SpectreRF.
of the inductances and resistances of a bondwire caused by skin effects. In this proposed design, two types of bonding wires with a length of 2 and 5 mm are used. These bondwire inductors were first simulated using Cadence SpectreRF. The Zparameter simulation result for both bondwires is shown in Fig. 4. The real parts for both bondwires are zero, while the imaginary parts are 30 and 62 for 2 and 5-mm bondwire, respectively, at 2.4 GHz. The values are equivalent to 2.0 nH for the 2-mm bondwire and 4.1 nH for the 5-mm bondwire. The simulation model of a bondwire inductor gained high Q, as shown in Fig. 5. This high Q resulted in the high performance of the proposed Class E PA. The Q for the 2 and 5-mm bondwires were found to be approximately 62 and 35, respectively, at the 2.4-GHz operation frequency.
4. Design and implementation The proposed Class E single-ended PA cascode topology with self-biasing is shown in Fig. 6. The designed
Fig. 7. Transient response for drain current and drain voltage of M3.
PA can be divided into two stages, driver stage and power stage. The transistor of the driving stage M1 is biased in Class A with a size of 512 m/0.35 m. The supply voltage is set to 3.3 V. DC block capacitor C1 and bondwire L1 are part of input matching. The bondwire Ld is connected to the supply voltage (Vdd) for M1 with a length of 5 mm. The interstage matching network consists of the integrated series capacitor C2 set to 6 pF after fine-tuning to provide high gain to the power stage. The power stage is implemented by cascode topology with self-bias. In the conventional Class E cascode topology, common source (CS) gate is connected to Vdd [1,12]. However, in this proposed design, the bias for CS gate is provided by R3 and C3, for which no extra bond pad is required. The dc voltage applied to the CS gate is the same as that applied to CS drain. The values of R3 and C3 can be chosen for optimal performance. To minimize the switch on-resistance, a maximum-size switch transistor is preferred. Thus, to optimize the performance of the power stage altogether, three transistors in parallel for CS and four transistors in parallel for common gate with 64 fingers were selected. All devices have a maximum width of 8 m and minimum length of
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30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -20 -16
Pre-layout (Pout) Post-layout (Pout) Pre-layout (PAE) Post-layout (PAE)
by using 2-mm bondwire. Since it is more critical to have a low ground inductance at the power stage, nine bondwires (Lgnd) are used to ground the source of M2, which provided an inductance of about 0.22 nH for the same bondwire length. The grounds are separated to avoid feedback from the power stage to the drive stage.
5. Simulation results The circuit design of the Class E single-ended PA is simulated using Cadence SpectreRF simulator in TSMC 0.18-m CMOS process. Fig. 7 shows the simulated drain voltage and current waveform of the power stage. Class E operation wherein the voltage and current are not overlapping with each other can be observed. On the other hand, the voltage and current are not maximum level at the same time, that is, the power dissipation or the product of drain current and voltage are minimized. Therefore, high efficiency can be obtained. The minimum voltage is non-zero because of the transistor’s on-resistance. Fig. 8 shows the pre-layout simulation and post-layout simulation for the output power (Pout) and PAE vs. input power (Pin). The results for the post-layout simulation are degraded because of the parasitics effects. However, both simulation results match well at higher input power levels. The proposed Class E PA delivers the maximum output power of 23 dBm with 44.5% PAE for an input power of 16 dBm. Output power and PAE vs. supply voltage are shown in Fig. 9(a), the output power changes approximately proportional to Vdd2 , from 18.5 to 24.5 dBm when the supply voltage is swept from 2.0 to 3.6 V. It can be noted that the output power can be controlled through the supply voltage. Fig. 9(b) shows the output power and PAE of the PA as a function of frequency. The output power is kept at least 20 dBm over the frequency range of 2.0–2.6 GHz. However, more than 40%
50 45 40 35 30 25 20
PAE (%)
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Fig. 8. Output power and PAE vs. input power.
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Pout (dBm)
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0.35 m. The gate of M2 is biased at 0.75 mV and the Vdd for M3 is 3.3 V. Based on the selected Vdd, frequency, and the wanted output power, the values of Cshunt, Cs and Ls were calculated [13]. The finite DC inductance Ldc is realized by a 5-mm bondwire connecting the CS drain to the DC supply connection. The 50 output resistance is downconverted by means of the simple L–C matching circuit, Lo and Co. Lo is realized by 5-mm bondwire, Co being an off-chip capacitor with the value of 3.3 pF. Co is a high-frequency microchip capacitor, which has the contact on the surface side and the ground on the opposite side. Therefore, extra bondwire Lext is required to connect to the output for experimental purpose with the length of 2 mm. It should be finally noted that the effect of bondwires was taken into account during simulations (Lsd and Lgnd in Fig. 6). Three bondwires (Lsd) are used to ground the source of M1, which results in an inductance of about 0.67 nH
45 40
23 35 22 30 21
25
20 2.0
2.1
2.2
2.3
2.4
Frequency (GHz)
Fig. 9. Output power and PAE vs. (a) supply voltage and (b) frequency (post-layout).
2.5
20 2.6
PAE (%)
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compared with [13,14] by considering down-scaling technology; however, in [15], it gains high output power and high PAE, though the chips occupy a large space. The results from this proposed design also take into account the effect of bonding wires during simulation. The layout of the proposed Class E PA is presented in Fig. 11. The die area including the pads is 0.70 mm×0.53 mm; this layout is already taped out for fabrication.
2 -8
-4 0 4 Pin (dBm)
8
12
16
20
0
Fig. 10. Output power and power gain vs. input power (post-layout). Table 1. Performance summary of CMOS single-ended PAs. Reference
[13]
[14]
[15]
This work
Technology (m) Frequency (GHz) Vdd (V) Pout (dBm) PAE (%) Total chip size (mm2 )
0.35 2.4 2.5 20 59 1.00
0.18 2.4 3.3 21.3 40 0.43
0.25 2.4 3.3 24.1 50.6 1.01
0.18 2.4 3.3 23 45.5 0.37
6. Conclusion A self-biased cascode topology Class E single-ended PA for WLAN applications has been designed and simulated in the TSMC 0.18-m CMOS process by considering the effect of bonding wires. All circuit components, except the capacitor for output matching network, have been designed onchip and all inductances are realized using bonding wires. The post-layout simulation results show that the power amplifier can deliver an output power of 23 dBm with a PAE of 44.5% at 2.4 GHz.
Acknowledgments This work was partly supported by a grant of Knowledge Cluster Initiative implemented by Ministry of Education, Culture, Sports, Science and Technology (MEXT) and KAKENHI. This work was also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent Corporation.
References
Fig. 11. Layout of the proposed Class E single-ended PA on 0.18-m CMOS technology.
of high efficiency is kept only over the frequency range of 2.35–2.50 GHz. This PA can operate at the 2.35–2.50 GHz band with higher performance. Output power and power gain vs. input power is shown in Fig. 10. The maximum power gain of approximately 13 dB is obtained for an input power of 6 dBm. Table 1 presents the comparison of performances of the previously reported Class E single-ended PA and this work. The proposed design obtains better performance when
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[8] Mazzanti A, Larcher L, Brama R, Svelto F. A 1.4–2 GHz wideband CMOS Class-E power amplifier delivering 23 dBm peak with 67% PAE. In: IEEE digest of papers, radio frequency integrated circuits (RFIC) symposium 2005. p. 425–8. [9] Grebennikov A, Sokal NO. Switchmode RF power amplifiers. Elsevier; 2007. [10] Tawfik S, Tong T, Nielsen TS, Larsen T. A 1.9 GHz CMOS Class E power amplifier with +29 dBm output power and 58% PAE. In: Proceedings of IEEE European conference on circuit theory and design, 2005. p. I/87–90. [11] Ho KW, Luong HC. A 1-V CMOS power amplifier for bluetooth application. IEEE Transactions on Circuits and Systems-II, Analog and Digital Signal Processing 2003;50:445–9. [12] Grebennikov A. RF and microwave power amplifier design. McGraw-Hill; 2005. [13] Leungvongsakorn P, Thanachayanont A. A 0.1-W CMOS Class-E power amplifier for bluetooth applications. In: TENCON IEEE conference on convergent technology for Asia-Pacific region, 2003. p. 1348–51. [14] Saari V, Juurakko P, Ryynanen J, Halonen K. Integrated 2.4 GHz Class-E power amplifier. In: IEEE digest of paper, radio frequency integrated circuits (RFIC) symposium, 2005. p. 645–8. [15] Huang J-F, Liu RY, Hong P-S. An ISM band CMOS power amplifier design for WLAN. AEU – International Journal of Electronics and Communications 2006;60:533–8. Sohiful Anuar Zainol Murad was born in Kedah, Malaysia in 1975. He received the B.Eng. degree in Electronic Engineering from Saga University, Japan, in 2000 and the Master of Science in Electronic Systems Design Engineering from the Malaysia Science University, Malaysia in 2004. In 2000, he joined SGTi Globetronic Technology (M) Sdn. Bhd., Malaysia as QA engineer. After 3 months, he quit and joined Sharp-Roxy Corporation (M) Sdn. Bhd., Malaysia as R&D engineer for almost 3 years. In 2003, he moved to Malaysia Perlis University, Malaysia as a lecturer in the School of Microelectronic Engineering. He is currently pursuing the Ph.D. degree working on CMOS power amplifiers and RF designs at the Graduate School of Information Science and Electrical Engineering, Kyushu University, Japan since 2008. Ramesh K. Pokharel received the M.E. and Doctorate degrees from the University of Tokyo, Japan in 2000 and 2003, respectively, all in Electrical Engineering. He had short academic and industrial experiences in Nepal before he joined the University of Tokyo in 1997 as a research student. He had been a post-doctoral research fellow with the Department of Electrical Engineering and Electronics, Aoyama Gakuin University, Japan from April 2003 to March 2005.
In April 2005, he joined the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University where he is currently an assistant professor. His current research interests include the employment of passive components such as CPW in RF CMOS system LSI, EMC and signal integrity issues of LSI, and low-noise and high linear RF frontend architectures. He is a member of the IEEE. Dr. Pokharel was a recipient of the Monbu-Kagakusho Scholarship of the Japanese Government (1997–2003) and an excellent COE research presentation award from the University of Tokyo in 2003. Haruichi Kanaya was born in Yamaguchi, Japan, in 1967. He received the B.S. (Physics) degree from Yamaguchi University in 1990 and the M.E. (Applied Physics) and D.E. degrees from Kyushu University in 1992 and 1994, respectively. In 1994, he became a Research Fellow (PD) of the Japan Society for the Promotion of Science. In 1998, he was a visiting scholar at the Massachusetts Institute of Technology (MIT), USA. He is currently engaged in the study and design of RF CMOS System LSI and superconducting microwave devices, as an Associate Professor in the Department of Electronics, Graduate School of Information Science and Electrical Engineering, and also System LSI Research Center, Kyushu University. Dr. Kanaya is a member of the Institute of Electrical and Electronics Engineers (IEEE). Keiji Yoshida was born in Fukuoka, Japan, in 1948. He received the B.E., M.E. and Dr. Eng. degrees from Kyushu University in 1971, 1973 and 1978, respectively. He is currently engaged in the study of applications of superconducting thin films to microwave and optical devices and design of RF-LSI chips for SoC, as a Professor in the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University. Dr. Yoshida is a member of the Institute of Electrical and Electronics Engineers (IEEE) and the Japan Society of Applied Physics. Oleg Nizhnik received the B.E. and M.E. in Industrial Electronics from Moscow Power Engineering University in 2004 and 2006, respectively. He was awarded excellent research presentation awards from Moscow Power Engineering University in 2003 and 2004. In 2005, he joined Lianozovo Design Bureau, where he designed radar electronic components. In 2007, he entered doctoral courses of Kyushu University. His current research interests include the design of RF front-end subcircuits.
