A 3-V 0.5-μm CMOS A/D audio processor for a microphone array

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Brief Papers A 3-V 0.5- m CMOS A/D Audio Processor for a Microphone Array F. Balestro, V. Fraisse, G. Martel, D. Morche, P. Senn, G. Le Tourneur, and Y. Mahieux Abstract—A 0.5-m 3-V CMOS mixed-mode audio processor is presented. It is mainly composed of 11 low-noise input channels and a dedicated digital audio processor. Analog input signals are provided through an 11-microphone array. The chip size is about 50 mm2 , and the power dissipation is less than 100 mW. This circuit is dedicated to multimedia applications. Index Terms— Acoustic arrays, CMOS analog integrated circuits, digital signal processors, sigma-delta modulation.

I. SYSTEM ENVIRONMENT

I

N teleconference systems and hands-free telephone sets as well as in multimedia workstations with audio interfaces, picked up speech signals are disturbed by the acoustic environment (room effect and ambient noise). The microphone array has been demonstrated as an efficient technique to improve the speech quality in various applications [1]. In a microphone array, the signals picked up by the several sensors are combined such that the useful signals are coherently summed and therefore enhanced with respect to the disturbing signals (see Fig. 1). If we assume: —a linear array made of omnidirectional microphones; —a plane wave system (the source is supposed to be relatively far from the array as compared with , the microphone pitch). Then the path-difference between two adjacent microphones and the source is

(a)

(b)

Fig. 1. (a) Microphone array principle and (b) diagram directivity.

Fig. 2. Optimal directivity pattern (without spatial aliasing).

and the global transfer function from the source to the microphone array can be approximated by

with

the wave-length of the audio signal.

Previous studies [2] have shown the improvement in the speech quality obtained from a specific array composed of 11 low-cost unidirectional microphones compared to a single microphone. The directivity patterns of the array are shown on Fig. 1(b).

Fig. 3. Practical realization of the microphone array.

The maximum of the function Manuscript received November 20, 1996; revised February 13, 1997. F. Balestro, V. Fraisse, G. Martel, D. Morche, and P. Senn are with France Telecom, CNET Grenoble, 38243 Meylan Cedex, France. G. Le Tourneur and Y. Mahieux are with France Telecom, CNET Lannion, 22301 Lannion Cedex, France. Publisher Item Identifier S 0018-9200(97)04367-9. 0018–9200/97$10.00  1997 IEEE

are given by

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Fig. 4. Chip architecture.

Fig. 5. FIR transfer functions (two sets of coefficient).

This formula shows that the whole system may present some spatial aliasing. The directivity of the antenna is given by the 3-dB width of the main lobe

In order to avoid any secondary lobes, we have to verify the following condition (see Fig. 2): which is equivalent to: It is therefore necessary to find a compromise with (number of microphones) and (distance between two successive microphones).

Fig. 3 presents the basic scheme of the array. In order to achieve a control of the directivity pattern over the frequency range [100 Hz, 7 kHz], the sensors are grouped into four subarrays. Each subarray is characterized by a specific intersensor spacing and is dedicated to a part of the frequency range by means of a band of filters. The characteristics of the subarrays are the following: cm, • 1-low frequencies (100 Hz–1 kHz), spacing: two microphones plus two “side” microphone; • 2-medium frequencies 1 (1 kHz–2 kHz), spacing: cm, five microphones; • 3-medium frequencies 2 (2 kHz–4 kHz), spacing: cm, five microphones; cm, • 4-high frequencies (4 kHz–7 kHz), spacing: five microphones.

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Fig. 6. Third-order (2 + 1) delta-sigma converter (MASH architecture).

In order to reduce the cost of the whole system, as well as the volume of the equipment, a dedicated chip has been designed. A 0.5- m CMOS process, including high quality (double poly) capacitors has been used and specific layout rules applied in order to maintain a high S/N ratio, in spite of the 3-V power supply and the 7-kHz bandwidth signal.

II. CIRCUIT DESCRIPTION Fig. 4 presents the architecture of the circuit. The 11 microphone preamplifiers (see Fig. 3) have not yet been implemented within the chip for noise considerations. After this external 40 dB gain, the 11 analog full differential input signals are again amplified within the chip, through low-noise variable-gain amplifiers. These amplifiers [3] allow the global and individual gain of each channel to be adjusted if necessary from 20 dB to 20 dB, with a 0.5 dB step. The 11 signals are then mixed in order to obtain the four (low, medium 1, medium 2, and high frequency) signals. These four signals are then digitalized thanks to four third-order 2-MHz delta-sigma converters. The four 2-MHz digital signals are downsampled to 64 kHz after blocks. After this first down sampling, the spectrum of these four signals is limited to 7 kHz with four identical ninth-order infinite impulse response (IIR) filters, implemented with a bit-serial architecture. The four signals are then directly downsampled to 16 kHz and sent to four different finite impulse response (FIR) filters in order to retain the desired part of the input signal spectrum coming from each subarray and to eliminate the other unwanted components. The four transfer functions of the FIR are presented in Fig. 5 and they are made of sixty-first-order symmetrical filters. The four signals are then directly recombined (adder) and a last IIR high-pass (cutoff frequency of 125 Hz) filter eliminates all the undesirable dc and low frequency parts of the signal. A simple

Fig. 7. Measured directivity patterns of the array (5 dB between two circles) for the octave bands centered around 500 Hz (—), 1 kHz (- -), 2 kHz (::::), and 4 kHz (-.-.-).

dual-single D/A channel has also been implemented in order to provide a local analog control signal. III. CIRCUIT OPTIMIZATION All the digital parts have been implemented by using a topdown synthesis approach. The digital optimization has been made at the architectural level by using specific bit-serial generators for the four low-pass and the high-pass IIR filters [4] and a generator of filter banks for the FIR part. Two sets

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of coefficients have been implemented for the FIR filters, and the complexity of the digital part is about 250 K transistors. Specific care has been taken with the layout of the analog part. The main constraints arise from the 3 V power supply and the bandwidth of the signal (7 kHz). The input variable gain amplifiers can adjust the level of each channel, in a range from 20 dB to 20 dB (for a global gain adaptation and for specific microphone corrections, if necessary). The amplifier has been optimized for high linearity [100 dB total harmonic distortion (THD)], low noise (1.1 V in a 7-kHz bandwidth), and low power (less than 4 mW/Aop with 3 V power supply). The gain adjustment of the 11 input amplifiers is made through the variations of 11 independent differential resistor ladders. In order to maintain a high SNR, about 120 dB in a 7 kHz bandwidth, large input stage transistors have been used for these amplifiers (e.g., 250 m/100 m for the NMOS load), making each of them as space consuming as 10 k digital transistors. This is certainly an economic limitation for further low-noise mixed-mode development with lower supply voltage and high quality analog processing. The main characteristics of the 11 on-chip amplifiers are the following: • Voltage gain: 20 dB to 20 dB with 0.5 dB steps; • Input noise: 1.1 V 100 Hz–7 kHz (with 20 dB gain); • THD: better than 80 dB (20 kHz band); • Output load: A/D converter input capacitor load (10 pf); • Power consumption: 1.4 mA–3 V; • Total area: 0.44 mm . The four A/D converters are built around a classical third order MASH structure (see Fig. 6) [5]. The analog coefficients have been optimized in order to reduce the dynamic range at the integrator outputs, and the SNR, measured on stand-alone converters, using the same architecture and the same process, is better than 98 dB in a 7 kHz bandwidth. Due to the existence of the five input analog (capacitor) adders in front of each Delta-Sigma converter, the input thermal noise is added and so the input dynamic range is reduced. One solution is to increase the input capacitance, with the constraint of a large first amplifier capacitive load. An optimization has been made in order to guarantee an SNR better than 80 dB in the 7 kHz bandwidth, in spite of all the couplings between the digital and analog parts. The layout of the delta-sigma converters has been obtained automatically, taking into account analog routing constraints [6]. IV. MEASUREMENTS

AND

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TABLE I

Fig. 8. Global transfer function (from the central microphone to the D/A output).

CONCLUSION

Measurements have shown a very good agreement with the simulations. The digital part is fully functional and the analog measurements have shown very low degradation due to digital crosstalks. Fig. 7 shows the measured directivity patterns of the array for the octave bands centered around: 500 Hz, 1 kHz, 2 kHz, and 4 kHz, and Fig. 8 presents the global transfer function of the chain, including the A/D part (from the central microphone) and the D/A part. Table I summarizes the main electrical features of the chip and Fig. 9 shows the microphotograph of the whole chip. An acoustic antenna made of a microphone array and a specific audio processor has been presented. This approach

Fig. 9. Microphotograph of the chip.

leads to a low-cost solution for a high-quality hands-free communication. By introducing variable digital delays, it will be possible to dynamically adapt the direction of the main lobe and therefore improve multispeaker conference sound quality, for example. Finally, 0.5- m double-poly, triple-metal CMOS process has demonstrated its capability to implement highperformance 3 V mixed-mode signal processing functions.

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ACKNOWLEDGMENT The authors would like to thank B. Lucas and L. Sponga for the layout and J.-P. Laval for the measurements. REFERENCES [1] J. L. Flanagan, D. A. Berkley, G. W. Elko, J. E. West, and M. M. Sondhi, “Autodirective microphone systems,” Acustica, vol. 73, pp. 58–71, 1991. [2] Y. Mahieux, G. Le Tourneur, A. Gilloire, A. Saliou, and J. P. Jullien, “A microphone array for multimedia workstations,” presented at Third Int. Workshop on Acoustic Echo Control, Plestin les Gr`eves, France, Sept. 1993.

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[3] E. Compagne, G. Martel, and P. Senn, “A 100 dB THD, 120 dB SNR programmable gain amplifier in a 3.3 V 0.5 m CMOS process,” presented at ESSCIRC’95, Lille, France, Sept. 1995. [4] F. Balestro et al., “Design of digital filters for advanced telecommunications ASIC’s using a special-purpose silicon compiler,” IEEE J. Solid-State Circuits, vol. 26, pp. 1047–1055, July 1991. [5] Y. Matsuya et al., “A 16 bit oversampling A to D conversion technology using triple integration noise shaping,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, Dec. 1987. [6] L.-O. Donzelle, P. F. Dubois, B. Hennion, and P. Senn, “A constraint based approach to automatic design of analog cell,” in Proc. 28th DAC, San Francisco, June 1991, pp. 506–509.