A low power ECG signal processor for ambulatory arrhythmia monitoring system

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A low Power ECG Signal Processor for Ambulatory Arrhythmia Monitoring System Hyejung Kim1, Refet Firat Yazicioglu1, Tom Torfs1, Patrick Merken1, Hoi-Jun Yoo2, and Chris Van Hoof1 1

IMEC, B-3001 Leuven, Belgium, 2Department of Electrical Engineering, KAIST, Daejeon, Korea E-mail: [email protected]

Abstract An ECG signal processor (ESP) is proposed for ambulatory arrhythmia monitoring systems. The ESP consists of three heterogeneous processors and performs filtering, data compression, ECG classification, and encryption. A data reduction scheme, consisting of skeleton and Huffman coding, are employed to reduce the on-chip memory capacity and memory access power. Clock gating and voltage scaling are also applied to reduce the power consumption. The ESP consumes 1.26-µW at 0.7V, while providing real time signal processing. Keywords: biomedical signal processing, ECG, processor Introduction The most important requirements of ambulatory arrhythmia monitoring system are real time significant computational capability, large storage capability, programmability for the variability of users and application requirements, and very low power consumption. However, the general purpose processors still serve limited functionality [1] or cannot achieve very low power consumption due to their limited computing power [2]. In this paper, an application-specific ECG signal processor is designed to perform the required signal processing for ambulatory arrhythmia monitoring system under very low power budget. ECG Signal Processor The proposed ECG signal processor (ESP) mainly executes four functions: filtering, data compression, ECG classification and encryption [3, 4]. Those functions are divided into three stages of pre-processing, classification, and post-processing by their computational characteristic. The three function-specific heterogeneous processors are proposed for each stage as shown in Fig.1, and they are pipelined in the heartbeat segmentation level to improve the parallelism and hardware utilization. Thanks to the parallel processing architecture, the operating clock frequency can be reduced down to the sampling frequency. The processors share the data via the segmentation memory bank, so the shared memory architecture with the priority scheduling technique is designed to protect congestions. The pre-processing stage extracts the feature vector from the ECG raw data for classification stage. The processing with raw data, such as filtering and feature extraction requires the most computational power. The dedicated hardware with full pipeline is implemented to accelerate the complex functions, and 1-cycle/sample throughput is achieved. In addition, the quad-level vector (QLV), which indicates the ECG waveform delineation and its information level, is generated. Based on this QLV, the further processing can focus on only the interested regions, like QRS complex, to reduce the workload and computational complexity. The classification stage analyzes whether the current heartbeat has the abnormality. The RISC architecture is adapted to enhance programmability for the various classification algorithms and to overcome the variability of users. The RISC is designed in event-driven 3-stage pipelined architecture. The compact 16-bit Instruction Set Architecture (ISA) and the special datapath are designed to reduce the operating cycle and the code size. After all the arranged program codes are processed, the RISC goes to sleep mode by clock gating until an event occurs. In this work, the classification algorithm with numerical conditions [4] is performed, and the RISC runs about 250-cycle for each heartbeat analysis. In the post-processing stage, the data format is converted to the 16-bit-wise word format for the efficient memory access, and the

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AES-128 encryption algorithm is performed to protect the privacy of the medical information before wireless transmission. Since AES requires complex calculations with large number of iterations, this stage should focus on single round latency reduction. The overall latency of post-processing is achieved as 6.56 cycle/sample, which is higher than the previous stages. However, since the processing bandwidth is already reduced by a factor of eight through the skeleton encoding which will be described in next section, it is enough to meet the target performance. On-chip Memory Reduction Scheme Since integrated SRAM consumes the largest factor of the total power consumption due to the memory access and leakage power consumption, an efficient memory architecture is required. In this work, the on-chip data memory consists of segmentation memory bank and main memory (MM) as shown in Fig.2(a). In general, the previous 8 heartbeats are necessary to decide the arrhythmia [5]. The segmentation memory bank, which consists of the QLV array, 0.5kB temporary memory (TM), and the segmentation feature register files (FTR), is implemented to keep about 10 seconds of data during the signal processing. The skeleton and Huffman coding are applied to reduce the memory capacity and the number of memory access. The main idea of the skeleton is that the sampling rate is varied according to the information level of the signal (Fig.3(a)). More samples are assigned to the highest level like QRS complex, and fewer samples are assigned to the lower level like TP segment based on the QLV value (Fig.3(c)). Still, the skeleton is the lossy-compression algorithm, therefore, there should be a tradeoff between the compression ratio (CR) and the error rate (PRD). According to the error graph (Fig.3(b)), the range of 7-10 is satisfied with both of CR and the target error range of PRD < 1%. The Huffman coding is performed before the results are stored in the main memory. The overall data is reduced by 94% through the proposed data reduction schemes while maintaining the crucial information (Fig.2(b)). Power Management In order to reduce the wireless transmission power consumption, the system transmits only the sections that are physiologically important instead of continuously transmitting the total range of ECG signal [3]. Based on this transmission mode, post processing stage needs to run only, when the event occurs like abnormal heartbeat detection. The RISC also goes active mode only when the new segmentation is incoming. Each processing unit can be individually enabled or disabled by the clock gating method according to the necessity as shown in Fig.4. The clock controller enables the clock signals (CLK_CL, CLK_PST) with the wakeup signal (CL_Wakeup, PST_Wakeup), when the processors are necessary to operate. Fig.4(b) shows the timing diagram of the proposed partial activation. Since the RISC and the post-processor occupy 12% and 37% of the total power, respectively, a power reduction up to maximum 49% and average 28% can be achieved. For further power reduction, the supply voltage is reduced up to 0.7V, while the functionality is guaranteed. Implementation Results The ESP is fabricated in 1-poly 6-metal 0.18µm CMOS technology. The core size is 2.25-mm2 with the 10.5kB SRAM, and the operating frequency is same as the sampling rate between 250 and 1k sample/sec. Fig.5 shows the chip photograph and the performance summary. Fig.6 shows the measured waveform of the alert detection mode. The R peaks and the abnormal heartbeat are successfully detected after the pre-processing and classification, respectively. Only

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Segmentation Memory Bank

the skeleton data for the abnormal region with ±2 seconds range are transmitted to the receiver, then they are reconstructed. Fig.8 shows active power consumption measurement result and frequency characteristic across the supply voltage (Vdd). The ESP consumes 6-µW (16.7nJ/sample) and 1.26-µW (3.5nJ/sample) at Vdd=1.8V and Vdd=0.7V, respectively.

References [1] S.C.Jocke, et al., “A 2.6 µW Sub-threshold Mixed-signal ECG SoC,” IEEE Proc. of VLSI Symp., Jun. 2009 [2] R.F.Yazicioglu, “Ultra-low-power Wearable Biopotential Sensor Nodes,” IEEE Proc. of EMBC, Sep. 2009 [3] H.Kim, et al., “An Integrated Circuit for Wireless Ambulatory Arrhythmia Monitoring Systems,” IEEE Proc. of EMBC, Sep. 2009 [4] H.Kim, et al., “ECG Signal Compression and Classification Algorithm With Quad Level Vector for ECG Holter System,” IEEE Trans. on ITB, vol.14, no.1, pp.93-100, Jan.2010 [5] D.C.Reddy, “Biomedical Signal Processing – Principles and Techniques,” Mc.Graw Hill, 2005

Power Consump.(uW)

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Figure 1. Top Block Diagram of ECG Signal Processor (i)

Segmentation Memory Bank

ECG Data Stream Skeleton CR = 8.4:1

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Figure 4. Power Management with Clock Gating Scheme

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Figure 5. Chip Photograph of ESP and Performance Summary

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Figure 6. Measured waveform with Abnormal Heartbeat

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Figure 3. Skeleton Encoding

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Figure 7. Active Power Consumption as Function of Supply Voltage

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