A sampleddata CMOS analog adaptive filter
Descrição do Produto
A SampledData CMOS Analog Adaptive Filter Gabriel Gomez and Raymond Siferd Wright State University

A b s h c t A fully ansampleddata CMOS AdapUve Fliter realizing the LMS adaptation on a Fourtap FIR filter has been fabricated. The system uses clocked CMOS sampleddata storage, fourquadrant CMOS Anaiog Multipliers and CMOS opampbased Arithmetic M d ules. For achieving higher output sampling rates, and for allowing modularity, a parallel architecture has been used, implementing each filter tap separately, instead of using a single tlmemultiplexedprocessing unit. The prototype chip was fabricated using doublemetal doublepoly 2micron CMOS pwei~techn, oeeupying an area ot 4 . 0 ” ~ and using +5Vpower supplies.
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1. INTRODUCTION An adaptive System is one whose structure is adjustable in such a way that its performance improves through contact with the environment, according to some desired criterion. Adaptive filters are widely applied in such fields as Communications, Radar, Seismology,Mechanical Design, Automatic Controls, Biomedical electronics, and so on.
In many cases the input signals to an Adaptive System are Analog in nature, and so are the desired outputs. For this reason, a fully analog adaptive system may be desirable in some applications, if its convergence is ensured in spite of the low accuracy attainable with Analog Signal Processing Arithmetic. The advantages of such systems are the direct Analog signal processing with no requirements for A D or D/A conversion, the reduced size of some of the main building blocks (like the multipliers), and the relatively fast convergence.
FIG.l Adaptive Filter
In this paper, the weights are adapted according to the LMS algorithm [l]: w{k+I) = w{k)
+ Zp.e(k).x(ki), i=O,I,..LI
(2),
where x(k) is the filter input, y(k) the filter output, d(k) the desired signal, e(k) the error output, L the filter order, and p is the algorithm’sconvergence factor. The LMS algorithm can be implemented as a correlator; for the system used in this paper, a simple scheme using a delay line has been used, as shown in Fig.2. zu
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The operation of this Filter is based on a basic Finite Impulse Response (FIR) Filter, which output y(k) is compared with a ’desired’ signal d(k) ,to obtain an ’error’ output e(k):
If in (1) the weights wi(k) are changed dynamically (adapted) according to a given Adaptive Algorithm, the general form of an Adaptive Filter, shown in Fig.1 is obtained.
CH30072/91/00000106 $1 .OO 1991 IEEE
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FIG.2 LMS Algorithm
As inferred from Fig.1 and Fig.2, only four building blocks are needed for the implementation of this system. Those blocks are: Sample and Hold, Delay, Multiplier and Adder blocks. The design of these blocks will be discussed in the next section. The design implemented here mes to keep the timing as simple as possible, uses a nonmultiplexed approach (unlike the multiplexed design of Fichtel et al. [2]) to allow modularity, and utilizes amplitude scaling (by means of opampbased modules) to keep the signal inside the allowed range.
 PenaFino1 and Connely [5] Multiplier: This multiplier, based on the Quartersquarealgebraic identity:
v* = [ (V1+V2? (V1V2?1.114 = VI.V2
(3).
showed also good linearity for a limited range, without the problem of the level shift. Its main problem is that it needs too many transistors, when compared to the other designs; besides, the original design had to be modified to allow using singleendedinputs.
2. BUILDING BLOCK MODULES
The module designs are discussed below: A. Opamp Module
A simple twostage operational Amplifier with Millercompensated poles and Resistorcompensated zero, proved to be good enough for this application. The schematic of this circuit, designed by Jundi [3], is shown in Fig.3. In this design, both the size of Cc and the value of Rz depend on the output capacitance. During the Filter's design, small variations on the value of Cc have been used for differen t applications. 50
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Bult and Wallinga [4] Multiplier: This multiplier, based on a basic VI converter. proved to have good linearity in all four quadrants for a limited range. Its biggest problem is the level shift needed at both inputs to ensure saturation of all transistors; additional circuitry is required to solve that problem.
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 Song and Kim 161 Multiplier: This circuit is also based on the Quartersquare identity, but it uses much simpler circuitry. Simple fourtransistor circuits are used to perform the sumsquaring and differencesquaring operations on two differential inputs. The original Song and Kim design had to be modified to allow singleended inputs and a singleended output; the modified design is shown in Fig.5. Due to its intrinsic simplicity, this circuit occupies a very reduced chip area. making it the best choice for the present application. Its main disadvantage is its limited output range, but, nevertheless, it was chosen for the final Filter design, The results of an SPICE simulation of this circuit are shown in Fig.4 @C Transfer characteristic), and can be compared against the results measured from a fabricated chip, shown in Fig.6.
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FIG.3. Opamp Module
All the adders and scalers needed in the filter use this @amp module in simple Resistive feedback configurations. B. Multiplier Module
Three different CMOS Analog Multipliers were considered for the design. AU three were simulated, physically implemented, and tested, the circuit best suited for this application was chosen after some modifications. FIG.4 SPICE simulation of the Multiplier
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FIG. 5 Modified Song and Kim Multiplier
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C, was chosen to be 1pF and fabricated using doublepoly to achieve small Droop and fast convergence.
Measured Results
It can be seen from Fig.6 that the measured output range is smaller than the simulated one, and, as expected, the offset is bigger. The theoretical Bandwidth with a load of 1.5pF is about 8MHz, but the measured one is just about 2MHz.
The results of a SPICE simulation for this module, in the range of interest, are shown in Fig.8. As can be seen, fast convergence and small droop have been achieved.
C . Sample and Hold and Delay Line Modules
The delay line was implemented using a simple twoopamp Sample and Hold configuration with Clear (Fig.7), synchronized by a twophase nonoverlapping clock. The control Signals A and B are derived from the Clocks
as shown, and are included to allow Clearing the Cell.
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3. SYSTEM DESIGN To build the Adaptive Filter, the modules described in part 2 have to be combined as shown in Fig.1 and Fig.2. For obtaining a versatile design, and for simplifying the testing, some features had to be taken into account:
* Several extemal Resistors allow adjusting the output ranges of some modules, allow also amplitude scaling and provide means for avoiding overflow.
* An internal clock generator provides all necessary timing signals from a single clock input and an asynchronous Clear input. * An extemal control signal (CFIR)allows switching between a simple fourstage FIR filter and the Adaptive Filter. U
* The "desired input signal has to be sampled and Held to obtain d(k).
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FIG. 8 Sample and Hold Simulation
* The convergence factor p has to be small enough to allow convergence, and big enough for fast convergence. The value of p is set by varying the gain of an adderamplifierby changing the value of an extemal Resistor.
* All the outputs are buffered so the external capacitance d m not affect the internal functioning.
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FIG. 9 Filter Block Diagram
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* External biasing is provided for the multipliers and the sample and Hold circuits, to correct for variations in circuit parameters associated with the particular fabrication run. The block diagram of the designed system is shown in Fig.9, and the layout in Fig.10.
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4. TESTING
A fist functional test was made by Computer simulation. A FORTRAN program was written to simulate the circuit's behavior and several signals were used to test the results. A simulation operating the filter as an adaptive noisecanceller was run; this application was chosen because it can be easily implemented to test the actual chip and compare the results to the simulation. In this application, the signal ~ ( t ) , corrupted by an interference n(t) is applied to the desired input &(). The noise signal n(t) is also applied directly to the filter input x(t) (reference input).
It has been shown [l] that if s(t) and n(t) are uncorrelated, then e(k) will converge to the best fit (in the leastsquares sense) to the signal s(t), and y ( t ) will similarly converge to
n(0. To run the simulation, very simple input signals were cho
sen: s(t), a 2KHz unitamplitude sine wave and n(t), a 4.8KHz unitamplitude sine wave. The input signals and the simulation results are shown in Fig.11; for this simulation the convergence factor p, is 0.008 and the initial weight values are all set to zero. For this value of p, the convergence is relatively fast: y(k)
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FIG.11 Filter Testing: Simulation
converges to x(k) in about 100 iterations, and e(k) converges to s(k) in about 300 iterations; the filter weights converge to +0.05 of their final value in about 350 iterations. The range of values of p for which the filter converges was found to be 0.002
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