Architectural System Design of Six Channels Compact Fuzzy Logic Controller for Arm Robot Joints Using FPGA Technology

Applied Mechanics and Materials Vols. 541-542 (2014) pp 1127-1131 Online available since 2014/Mar/12 at www.scientific.net © (2014) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/AMM.541-542.1127

Architectural System Design of Six Channels Compact Fuzzy Logic Controller for Arm Robot Joints Using FPGA Technology Bambang Siswoyo1, a, Moch. Agus Choiron2, b, I. N.G. Wardana2, c and Yudy Surya Irawan2, d 1

PhD Student of Mechanical Engineering, University of Brawijaya 2

Mechanical Engineering Department, University of Brawijaya JL. MT. Haryono 167, Malang, East Java, Indonesia

a

[email protected], [email protected], [email protected], [email protected]

Keywords: Robotic, Arm Robotic, FPGA, Fuzzy Logic Controller, FLC, Embedding, Digital Control

Abstract. The purpose of this study is to develop the architectural system design of the Six Channels Compact Fuzzy Logic Controller (SCC-FLC) ready to be embedded into the FPGA (Field Programmable Gate Array) for joints of arm robot's manipulator. The FPGA based system design of this study could controlled independently six servo of arm robot manipulators to reduce workload of computer system. The method of this study divided into four steps. The first step, the FLC-P (Fuzzy Logic Controller Processor) block module of single channel C-FLC (Compact Fuzzy Logic Controller) on the previous study is redesigned in architectural system design by adding lots of block modules using multiplexing method. The second step, the module interconnections of system architecture are designed by defining some of inputs and output ports. The third step, the specific function of block modules about working processes is determined based on the definition of input and output ports. The fourth step, sequences of multiplexing processes are determined based on the algorithm of FLC, thus the total processing time of SCC-FLC could be estimated from architectural system design. Architectural system design of SCC-FLC requires external chips are 12bit ADC MAX-186 chip and 12bit DAC MAX-3203 of six chips. The block modules of SCC-FLC are FLC-P, LUT-MBFs (Look Up Table of Membership Function), ADC-I (Analog to Digital Converter Interface), DAC-I (Digital Analog Converter Interface), ECEG (Error and Change Error Generators), SPL (Set Point Latchs) and TAC (Time And Control). The total processing time of SCC-FLC by estimation is 256.2 µS or sampling frequency of 3.907KHz using clock frequency of 100MHz. Introduction Arm Robot for manufacture automation applications generally has six DOF (Degree Of Freedom) manipulators. In application, the six joints of arm robot manipulators must be regulated independently by servo controllers based on digital or analog system in order to make angles of joints steady on desired set-point. The controller used of this study is FLC algorithm for six joints of arm robot manipulator. Scope of this study is focused on the architectural system design of SCCFLC ready to be written into HDL (Hardware Description Language) like VHDL (Very High Speed Description Language). FLC-P is block module part of the C-FLC have been done in the previous studies as shown in Figure 1a [1]. FLC-P has 3 input ports and 1 output port to support as processor of FLC Algorithm. Two input ports are E (Error) and CE (Change Error) as input crisps to be processed by FLC-P, both has 12bits. CLK (clock) as 1 bit input port provide signal to start the processing of FLC-P. Another port is an output port of 12 bits width provide the processing result by FLC-P algorithm, thus ready to be sent to the input port of DAC chip. The FLC-P internally has two LUT-MBFs of E and CE. Each LUT-MBF provides 16 tables of tri-angle function variations by arrays of VHDL source code writing. FLC-P is developed in order to extend the number of channel became six channels by only one FLC-P block module used. In the previous study, processing time All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP, www.ttp.net. (ID: 180.253.64.197-23/04/14,02:41:01)

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of C-FLC is about 65.4uS using clock frequency of 50MHz on Spartan 3 XC3S1000 chip [1]. Regarding study of the Design and Implementation of a Fast Digital Fuzzy Logic Controller Using FPGA Technology [3], speed of processing time of 65nS is too fast to be applied into servo control for joints of arm robot manipulators. In order to process the six channels, FLC-P is implemented to process one channel at a time, or it called multiplexing method. Fast Fuzzy Logic Controller using concurrent method will need very huge of FPGA resources to control about six joints of arm robot manipulators [3,4,5,6,7,8]. This study focused on FPGA-based of SCC-FLC which need minimal resources, however, the processing time needed is enough to serve six joints of manipulators. In terms of minimizing the use of FPGA resources, architecture of system design used RTL (Register Transfer Level) [10]. Generally in industrial application, the movement speed of arm robot used a low speed of straight line movement on the end-effector about 0.5 m/s, which is based on Unimate PUMA-500's Robot [2]. The whole implementation of arm robot application on industry will need digital processor for processing of indirect kinematic algorithm, processing of servo control algorithm for joints stability, processing of movement language such as VAL II for PUMA robot etc. On the PC (Personal Computer) based controller of arm robot manipulators, whole processing will be done by all resources of computer [9]. The uniqueness of this study are compact design of six channels FLC with minimal FPGA resources needed; can reduce the workload of the PC as a whole of digital processing in the robot system, because not necessary to control the joints of arm robot manipulators. Method The method of this study was divided into four steps. The first step, FLC processor on Figure 1a on previous study has been modified in order to pull out the internal LUT-MBFs as externally six block modules as shown in Figure 1b. In order to interconnect between FLC-P and LUT-MBFs modules, 12bits of input ports namely X1, X2, X3, U1, U2, U3 are added into FLC-P module for incoming data ports of MBF tables from LUT-MBFs to FLC-P.

(a) (b) Fig. 1 (a) FLC processor part of Compact-FLC on previous study (b) FLC-P on this study The additional input ports namely A[0..2] are added to select the current channel for data transfer processing of MBF-LUTs. CLK and RST signal are 1 bit signal for modul interconnects to synchronize data transfer of E/CE membership functions between LUT-MBFs and FLC-P. CLK is needed as timing signal of data transfer process. RST signal must be asserted before data transfer process is begun. The architectural design of SCC-FLC is designed by adding six modules could process the FLC algorithm using multiplexing method. The six modules are MBFs (Memberhip Function), ADC-I (Analog to Digital Converter Interface), DAC-I (Digital Analog Converter Interface), ECEG (Error and Change Error Generators), SPL (Set Point Latchs) and TAC (Time And Control). The second step, based on architectural design, on each block module is determined the number of input/output ports needed including type, direction and number of bit. The function operation of each module will be determined by this step in order interconnection between block modules. The third step, functional operation of each module is determined corresponding with the algorithm of six channels compact-FLC. The fourth step, sequences process for each channel are

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determined when the previous channel have done processed. Finally, the total processing time of six channels could be estimated based on time processing of C-FLC on previous study. Result The system architecture design of SCC-FLC shown in Figure 3 consists seven block modules with shortened names are TAC, SPL, MBF, ECEG, FLC-P, DAC-I and ADC-I. Every block module have specific function provides some input and output ports. Each block module is doing the process by triggering signal from another block module for the whole system synchronization. The block modules descriptions about specific functions, shorten name, module name and specific function are explained in Table 1. Architectural system design of the Compact-FLC consisting of 7 block modules are MBFs (Memberhip Function) of six modules, ADC-I (Analog to Digital Converter Interface) of one module, DAC-I (Digital Analog Converter Interface) of one module, ECEG (Error and Change Error Generators) of six modules, SPL (Set Point Latchs) of six modules and TAC (Time And Control) of one module.

Fig. 3 The System Architecture Design of Six Channels Compact Fuzzy Logic Controller Table 1. Specific function of Block Modules descriptions No. 1. 2.

Shortten Name TAC SPL

3.

LUT-MBF

4.

ECEG

5.

FLC-P

6.

DAC-I

7.

ADC-I

Module Name

Specific Function

Timing And Control SetPoint Latch Look Up Table of Membership Function Error and Change Error Generator Fuzzy Logic Controller Processor Digital to Analog Converter Interface Analog to Digital Converter Interface

Generate Timing and Control for system Hold current channel of SetPoint for desired position Hold the datas of six channel Membership Functions for Error and Change Error Calculate and Change Error based on SetPoint and datas of ADC MAX-186 chip Process the Fuzzy Logic Algorithm by datas of Error and Change Error Send datas to every chip of DAC MAX-3203 chips Starting ADC MAX-186 chip to read each channel of the feedback and send to ECEG

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Table 2. Function of input and output ports No

1

Shortten Name

TAC

2

SPL

3

LUT-MBF

4

ECEG

5

FLC-P

6

DAC-I

7

ADC-I

Input/Ouput Port

Port Direction

Spesific Function

START

Input

Control to start the process of SCC-FLC

WAIT

Input

Wait for ADC-I when ready

RST

Output

System reset for DAC-I and ADC-I

A[0..2]

Output

Select channel will be processed

CLK

Output

Control to start ADC converstion and SPL module

NEXT

Input

Wait for DAC-I ready

FUZ1..FUZ6

Output

Control to start FLC-P

CLK A[0..2] SP[0..11] DO[0..11] A[0..2] X1..X3, U1..U3 RST CLK A[0..2] FB[0..11] WR SP[0..11] FUZ1..6 E[0..11] CE[0..11] RDY E[0..11] CE[0..11] CLK X1..X3, U1..U3 DO[0..11] RST CLK RDY CS, SCLK, DO CS[0..2] RST CLK DI[0..11] CS, SCLK, DI SSTRB, DOUT WR DO[0..11] RST CLK RDY A[0..2]

Input Input Input Output Input Output Input Input Input Input Input Input Input Output Output Output Input Input Input Input Output Output Output Output Output Input Input Input Input Output Input Output Output Input Input Output Input

Control to latch a channel of SetPoint Select channel of Setpoint 12bits input datas of six channel Setpoints 12bits output datas of six channel Setpoints Select channel of MBF 12bits output datas of six channels MBFs Reset Signal to send datas of LUT-MBFs Clock for synchronizing datas tranfer Select channel of ECEG 12bits datas of feedback from ADC-I Control to write 12bits datas from ADC-I Six channel of 12bits datas from SetPoints Wait to start FLC-P 12bits datas of error calculating to FLC-P 12bits datas of change error result Status when processing is ready 12bits datas of error to be processed 12bits datas of change error to be processed Wait to start processing of FLC-P 12bits datas from current LUT-MBFs 12bits datas of output result Reset Signal to start LUT-MBFs Clock for synchronizing datas tranfer Status of FLC-P when have done Interconnecting signal of DAC chip Select channel of DAC chip Wait reset from TAC Wait to start for writing datas to DAC chip 12bits datas to be sent to DAC chip Interconnecting signal of ADC chip Control to write datas of ADC to ECEG 12bits datas from ADC chip Wait reset from TAC Wait to start of ADC processing . Status of ADC-I when ready Selech channel of DAC chip

The function of input and output ports in each block module is explained in Table 2. The frequency of 100MHz will be applied to the SCC-FLC. Based on previous study, using frequency of 50MHz, single channel of C-FLC have processing time of 65.4uS. Now, the processing speed

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will increase twice of 32.7uS with frequency of 100MHz. ADC conversion time is 10µS for each channel. Finally, processing time of each channel Compact-FLC will be 10µS+32.7µS = 42.7µS. Thus, the maximum processing time on six channel C-FLC could be estimated based on architectural system design about 6x42.7µS=256.2µS, or 3.907KHz of sampling frequency. Conclusions Architectural design of the Six Channels Compact-FLC would be useful for servo control in the field of robot system. This six channels Compact-FLC could control joints independently thus reduce the workload of computer system in realtime processing of 256.2µS or sampling frequency of 3.907KHz, because the realtime servo control worked independently; thus all types of computer system could be used for movement algorithm processing such as inverse kinematic algorithm and others processing needed by robotic system. In the future study, it can be developed: Computer system interfacing with six channels Compact-FLC. This interface makes it easier to send a series of set points requested by the PC so that all types of PCs can be connected to the SCC-FLC using standard peripheral, i.e. serial USB. Algorithms of point to point movement could be embedded into FPGA. Thus, the trajectory movement of arm robot end-effector can be constructed by sending some series of coordinate data by regular PC. LUT-MBFs data can be saved on external memory such as EEPROM for online updating without recompiling and re-embedding of VHDL sources program. This can be done by developing further modules of LUT-MBFs. The indirect kinematic algorithm processing could be embedded into the FPGA to build the standalone controller of the whole robotic system. References [1] Bambang Siswoyo, Moch. Agus Choiron, I.N.G. Wardhana, Yudi Surya Irawan, in: System Architecture and FPGA Embedding of Compact Fuzzy Logic Controller for Arm Robot Joints, Journal of Applied Mechanics and Materials, Vol. 493, page 480-485, 2014. [2] Unimation: Unimate PUMA series 500 Industrial Robot, Descriptive Bulletin 22-523, 1984. [3] K. M. Deliparaschos, F. I. Nenedakis and S. G. Tzafestas: Design and Implementation of a Fast Digital Fuzzy Logic Controller Using FPGA Technology, Journal of Intelligent and Robotic Systems, Springer, 2006. [4] S. S_anchez-Solano, A. J. Cabrera, I. Baturone, F. J. Moreno-Velo and M. Brox: FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications, IEEE Transactions on Industrial Electronics, 2007. [5] Jose Edinson Aedo Cobo and Wilhelmus A.M. Van Noije: VHDL models for high level synthesis of fuzzy logic controllers, Article. [6] Nasri Sulaiman, Zeyad Assi Obaid, M.H. Marhaban and M.N. Hamidon: FPGA-Based Fuzzy Logic: Design and Applications a Review, IACSIT International Journal of Engineering and Technology, 2009. [7] Zeyad Assi Obaid, Nasri Sulaiman and M.N. Hamidon: Developed Method of FPGA-based Fuzzy Logic Controller Design with the Aid of Conventional PID Algorithm, Australian Journal of Basic and Applied Sciences, 2009. [8] Balwinder Singh, Rajneesh Goyal, Rakesh Kumar and R.P.P Singh: Design and VLSI implementation of Fuzzy Logic Controller, International Journal of Computer and Network Security, 2009. [9] M. Farooq M, Dao Bo Wang: Implementation of a New PC based Controller for a PUMA Robot based on COEM, IAENG International Journal of Computer Science, 2008. [10] Phong P. Chu: RTL Hardware Design Using VHDL, John Wiley & Sons, Inc, 2006.

Engineering and Manufacturing Technologies 10.4028/www.scientific.net/AMM.541-542

Architectural System Design of Six Channels Compact Fuzzy Logic Controller for Arm Robot Joints Using FPGA Technology 10.4028/www.scientific.net/AMM.541-542.1127