Cintia: a neuro-fuzzy real-time controller for low-power embedded systems

CINTIA:



A Neuro-Fuzzy Real Time Controller for Low Power Embedded Systems

L.M. Reyneri, M. Chiaberge, L. Zocca  Dip. di Elettronica - L.I.M. Dip. di Ingegneria dell'Informazione Universita di Pisa Politecnico di Torino Via Diotisalvi, 2 - 56126 PISA (I) C.so Duca Abruzzi, 24 - 10129 TORINO - (I) e.mail: [email protected] e.mail: [email protected]

Abstract

1 This paper describes CINTIA, a Neuro-Fuzzy real-time controller based on Pulse Stream computation techniques and designed for applications in low power embedded systems. The proposed system mixes two dierent approaches, namely Neuro-Fuzzy Controllers and Finite State Automata. The former are implemented by means of a custom neural chip (manufactured by ES2), while the latter are implemented as sequential code on a traditional microcontroller. The proposed system is used to demonstrate the advantages of mixing the two approaches and the feasibility of embedded Neuro-Fuzzy control systems. A low power, single chip version is also under design.

1 Introduction Real time control of non-linear systems is often a quite complex and computationally intensive task. It is for this reason that Neural Networks (NN) and Fuzzy Systems (FS) are gaining widespread acceptance in the eld of learning and intelligent control [11]. This is due mainly to their intrinsic parallelism, their learning and adaptation capabilities and, to some extent, also to their increased fault tolerance. Although NN and FS provide interesting performance for non-linear controllers, they alone 1 The work has been supported partially by the Italian National Project, CNR 93.05234.ST74, Sistemi Elettronici Avanzati - Reti Neurali and the InterUniversity Cooperation \Integrated Neural System for Robotic Applications" between Italy and Spain.

cannot satisfy all the requirements of a real plant. In fact there are several cases where an analog controller alone is not sucient as, for instance, when the plant has also ON/OFF input/outputs, or when the plant has a number of well de ned discrete states (which cannot be easily handled by NNs and FSs) and plant characteristics dier largely from state to state, etc. As examples, we can mention the forward and backward steps of autonomous walking machines, the control of electric engines running at dierent speeds in dierent phases of an industrial process, the optimal trajectory control of a manipulator with two largely different load conditions, and many others. In all these cases a more comprehensive approach is required, where Finite State Automata (FSA) and Intelligent Controllers (IC) must coexist and they must be tightly integrated with each other. In such a hybrid approach, the FSA keeps track of the discrete states of the plant and varies the controller parameters accordingly, while the internal continuous states of the plant may also act to switch the FSA from one state to another. This paper describes CINTIA, a hybrid Neuro-Fuzzy system devoted to the real-time learning control of non-linear plants. Thanks to the neural circuits used, CINTIA is particularly suited to low-power embedded applications where a small size, associated to a reduced power consumption and a high reliability, are often a must. The paper gives an overview of the overall project. Section 2 describes the hybrid intelligent control methods, while section 3 describes some approaches to intelligent control. Sec-

Figure 1: Block diagram of CINTIA's approach to IC. tion 4 describes the neural chip which is the core of CINTIA, while section 5 describes how to interface I/O sensors and eectors to the neural chip. Section 6 describes the rst prototype of CINTIA. At the end, sections 7 and 8 present, respectively, some application of this system and its theoretical and measured performance.

2 Hybrid Intelligent Control is a real-time controller which integrates FSA and IC methods into a common environment. Fig. 1 shows how a FSA checks a number of binary inputs from the plant and tracks the plant's discrete states. As a consequence, it supplies to the NN one out of a prede ned set of weight matrices W k (virtually one per each state). The NN measures the plant state variables y and drives the plant control variables u accordingly. The FSA switches from state to state according both to its binary inputs and to some thresholded control variables (i.e. ui > i , with i a programmable threshold). It is worth noting that network topology, including number of layers, can be modi ed by changing weight matrices. It is therefore possible to have dierent network topologies and sizes in the dierent plant states. The rationale of mixing these two approaches is that all the analog computations can be implemented more eciently by means of a NN engine, while FSA can be handled much more eciently by a digital programmable microCINTIA

controller. Due to the very small rate of discrete state changes typical of most plants, the controller will have a very low clock frequency (typically lower than 1kHz), which leads to a very low power dissipation and also to very low electromagnetic interferences. On the other hand, all analog computations can be handled by a Pulse Stream [1, 2, 3, 5] (PS) neural chip, which is also very energy-ecient. If the same dynamic performance had to be achieved by a single digital signal processor, a very high clock frequency would be required (in order to cope with the real-time requirements of the analog part of the controller) and this could be obtained at the cost of a much higher power dissipation (about three to six decades higher, as shown in table 2) and stronger electromagnetic interferences. A prototype board (see sect. 6) hosts one custom neural chip and a commercial microcontroller plus some glue logic which provides a tight interface between the Neuro-Fuzzy PS network and the microcontroller-based FSA. The board also hosts some signal conditioning circuit for direct interface with sensors and effectors. Another chip is being developed, containing all the elements which are currently placed on the prototype board, including self-learning. This chip will provide intelligent control capabilities with a very low power consumption and with all the advantages of Neuro-Fuzzy systems. Although CINTIA handles dierent NeuroFuzzy design strategies, in practice the system is centered around a NN computing kernel, since NNs can be implemented more eciently using PS techniques, although they can oer the same input/output characteristic of FSs. A useful design strategy consists in designing the controller using a fuzzy language and then training the NN to emulate it, as shown in g. 1 and described in sect. 3. This training can be done automatically by the programming environment described in sect. 6.3. The proposed system is centered around a full custom CMOS neural ASIC designed using Coherent Pulse Width Modulation (CPWM), a PS technique which shows very good performance [2]. Applying CPWM to Neuro-Fuzzy

by the fuzzy set theory paradigms. Although FS dier from NN, their inputoutput characteristic u = f (yd ) (usually memoryless) can be mapped on a NN directly. Once a fuzzy controller has been de ned, tested (and tuned), a NN can be trained thereafter, until the desired accuracy has been reached. Training of the NN can be done automatically by CINTIA's programming environment (see sect. 6.3).

 Neural Controllers with o-line training ( g. 2.b), which are trained \by

Figure 2: Examples of dierent control strategies: a) Fuzzy; b) o-line neural; c) on-line neural; d) inverse control. systems simpli es the design of synapses and neurons and provides evident advantages with respect to either fully analog or fully digital implementations, such as [4, 5, 10]: high noise immunity, ease of multiplexing, low energy requirements, straightforward interfaces with analog environments, higher accuracy, easier recon gurability.

3 Approaches to Neuro-Fuzzy Control has been designed with the requirements of intelligent control [11] in mind. It can accommodate several strategies for the development of the desired control system. The most interesting ones are shown in g. 2 and shortly described below: CINTIA

 Fuzzy Controllers ( g. 2.a), which

are described using a human-like language [11], where the uncertainties intrinsic in most plant models are handled

examples", by copying from a reference controller (may also be an existing one), which is used to generate an appropriate training set. The NN can be trained with a given accuracy but obviously the resulting controller cannot perform better than the reference. In this case the NN usually has state feedbacks. The network is trained by the programming environment, either o-line or on-line (i.e. with the neural chip inserted in the control loop).

 Passive Learning Neural Controllers

( g. 2.c), which learn directly from the plant, by on-line minimization of an appropriate cost function (often the square sum of errors). This methodology does not require a reference controller and can therefore provide better performance. The main drawback is that it behaves more as an adaptive than as a learning controller, since it may suer from over tting around the actual trajectories in the state space [11]. Learning can either be done o-line (i.e. by the programming environment) or on-line (i.e. using the learning capabilities of CINTIA's hardware). Also in this case learning can either be done oline or on-line (see above).

 Active Learning Neural Controllers,

which learn directly from the plant, as for passive learning controllers. The dierence is that the system tries to learn also from untrained regions in the state space, improving the overall performance also for rapidly varying plant conditions or for unforeseen input conditions [11].

 Inverse Controllers ( g. 2.d) which

learn from the plant both the direct (N1) and the inverse (N2) plant characteristics. The multiplexing features of CINTIA are well suited to inverse controllers, which usually require two (or pairs of) networks, one being the identical copy of the other. This can be accomplished by multiplexing on the same network the two dierent sets of input and output signals (e.g. yd , u, u , on N2 and its copy). Also in this case learning can either be done o-line or online (see above). Due to the many control strategies considered, it was felt that the exible programming environment described in sect. 6.3 was needed to exploit all the bene ts of the proposed approach, where the same control problem can be faced from dierent points of view. Several applications have been considered so far, some examples of which are described in sect. 7.

3.1 Controller optimization

In many cases, certain types of controllers (e.g. fuzzy or neural with o-line training, etc.) need to be optimized to provide performance comparable to others (e.g. Passive and Active learning controllers). This paragraph gives a brief overview of some optimization methods which have been used in CINTIA. For further details see [8, 12].  Genetic Algorithms (GA), which are powerful optimization methods [12] which can be used in conjunction with other techniques (e.g. PID, NN, etc.), to nd either the best controller parameters or the best network topology. They are substantially \trial and error" methods based on the way biological evolution works. A drawback is that this algorithm wastes a lot of memory since, for each \generation", a population of dierent solutions need to be stored and veri ed through a tness function but just one will be the nal one.  Simulated Annealing (SA), in which the solutions are evaluated by a tness

function and chosen randomly with a probability which is function of both the tness variations and a global parameter called temperature. This approach may be slower than GA but this algorithm does not require a large population of solutions and this is an advantage for hardware implementations (see table 1).  Hybrid Approach (GA+SA), which is the combination of GA and SA. This keeps the advantages of both methods, namely: lower memory requirements of SA and better performance of GA. The use of the GA+SA algorithm combines the main properties of standard GA operators (ecient sampling of the solution space, stochastic hill-climbing, memory of the latest stages of search) with those of SA (small population, ecient use of memory, easy hardware implementation). Table 1 compares the dierent methods for one of the applications described in sect. 7 and in [8].

4 CPWM Neural System This section describes a neural chip set based on CPWM techniques which has been designed, manufactured using ES2's 1:5m CMOS double-metal, single-poly technology, and it has been successfully tested [2]. The description is intentionally short, since most components of this chip set have already been reported in [2]. The following description has been inserted only for completeness. The CPWM neural chip set has been used in CINTIA as the analog computing kernel for Neuro-Fuzzy control. It is worth noting that, as mentioned before, such a system can also implement Fuzzy rules, as these can be automatically converted to neural weight matrices (transparently from the user). The neural chips are then tightly interfaced to the microcontroller via an external digital weight memory. Several independent weight matrices can be stored and selected at run time according to the state of the FSA. In the future all the components of CINTIA will be included in a single chip (currently un-

and M , convert the dierential voltage into a
(I , I , ): dierential current IS = M M +

IS = f (
V )  KW wij ;

Figure 3: Timing diagrams of CPWM modulations: a) plain, b) multiplexed. der design), which will exploit all the advantages of the proposed methods, together with an increased reliability and a much lower power dissipation (see sect. 8).

(2)

where KW is a proportionality factor. In the prototype chip, KW  2A and wij = 1
:5VV 2 [,1 : : : + 1]. The buer B pulses the current IS for a period Ti proportional to the input activation ii . Therefore the dierential charge injected into the summing nodes S + and S , is given by (from (1) and 2):

Qji = KW Tmax (wij ii );

(3)

4.1 Coherent Pulse Width Modula- which is the desired synaptic multiplicative tion function.

As shown in g. 3.a, CPWM activation pulses A neuron (not shown) sums up the charge (X1 : : : XN ) have constant frequency fo = T1O , contributions from all the synapses, applies a while their width is proportional to the activa- non-linear squashing function (usually a sigmoid, although it can be varied) and converts tion value [5]: back to a CPWM output. currents, the voltage on caTi = Tmax i; (1) Due to leakage pacitors C + and C , must be periodically rewhere i 2 [0 : : : 1] and Tmax < TO . A refer- freshed, via input port AIN and control signals ence clock (CCK) de nes two phases: CPWM REN and CEN, from an external digital memsignals are allowed to be \1" only during the ory through a D/A converter (see sect. 4.5). active phase (Ti  Tmax ) but they must always In the prototype, capacitor voltages VC and be \0" during the idle phase. The rst proto- VC , can be updated in less than 100ns with an types of CINTIA use a clock period TO = 7:2s accuracy better than 1%. Worst case refresh period is about 10s. (fo  139kHz) and Tmax = 6:3s. It is worth noting that, in spite of what is Further details on this circuit, on the neuron commonly believed [3], the phase relationship functions and on other CPWM functions can of CPWM streams does not imply synchronism be found in [2], although few minor improveamong leading and trailing edges, which would ments have been done to the last prototype otherwise cause high current spikes on power to improve its performance. In particular, the non-linear squashing function has been implesupply. mented as a waveform-driven non-linearity [5], on the A/PS conversion techniques de4.2 Working principle of CPWM based scribed in sect. 5.1. synapses and neurons So far the chip set is composed of the following components: The working principle of a CPWM synapse is based on the main property of Pulse Streams [1, 1. A recon gurable synaptic array chip (see 2]: the energy of a train of pulses is the product g. 5), with 33  32 synapses and 32 neuof their amplitude times their width. rons. Size is 7:200m2 per synapse, plus The simple synaptic circuit shown in g. 4 is 20:000m2 per neuron. The chip has a reused to multiply input activation ii by synaptic sponse time of 7:2s, equivalent to a comweight wij . The weight is stored as a dierential puting power of about 140 MCPS. In
(V , V , ) on the pair of capractice, according to the results presented voltage
V = C C pacitors C + and C , . The two transistors M + in [10], that chip could run up to fo = +

+

Figure 4: Schematic diagram of a CPWM synapse.

2.

3. 4. 5. 6.

4.3

Figure 5: Microphotograph of the 33  32 synaptic array chip (total size is 6:1  4:1 mm2 ).

recon gurable MLP/RBF cell. All these im2MHz, providing about ten folds increase provements will be included into the future single chip version of CINTIA, although they are in total computing power. not reported here in more details, due to space Several I/O pads with dierent Analog limitations. to/from PS conversion capabilities (see sect. 5 and g. 6). Sizes are about 200  400m2 , with power dissipations in the 4.4 Multiplexing and recon guration range 20 to 100W, with a sampling rate of 140kHz. An interesting advantage of CPWM signals is A pair of digital to/from PS converters. that they can be multiplexed more easily than analog ones, thanks to their digital nature and An array of 32 low-power, 8-bit, 100ns, coherence. A simple MR to 1 digital multiD/A converters with internal memory for plexer can be used to sequentially select up to weight refresh (see sects. 4.4 and 4.5). MR signal sources, with the timing shown in g. 3.b, signal MX . The signal MSYN synA 32  32 pixels CPWM imaging sensor chronizes transmitters and receivers together. (currently under analysis). Multiplexing may have several advantages and applications, especially in the eld of real Other mathematical functions such as: Manhattan distance, winner-take-all, time control. The most interesting ones are: etc. [5].  to reduce pin count. This has several bene ts for very low cost embedded systems, where ASIC neural chips are often pinImprovements to CPWM limited. synapse

The synaptic circuit shown in g. 4 is currently being improved. The analog memory cell which, at present, is a dierential voltagestorage cell, is being modi ed into a currentstorage cell, using a circuit similar to that proposed by [9]. A discrete self-refreshing analog storage cell is also being added (using four additional transistors). Furthermore, by adding another two transistors, the proposed MLP synaptic cell of g. 4 will be converted into a

 to implement virtual copies of a single NN,

which is useful in many inverse control applications [11] (see sect. 3 and g. 2.d.)

 to recon gure dynamically the size and ar-

chitecture of a Neuro-Fuzzy system [2, 8]. The same array can be recon gured as fewer neurons with more synapses, or vice versa, provided that the total synapse count remains unchanged. In these cases,

input and output CPWM streams shall be multiplexed accordingly.  to modify network topology, including number of layers [8].  to implement populations of NNs, as required by genetic algorithms and simulated annealing [8] (see also sect. 4.5).

4.5 Virtual networks

The CPWM neural network of CINTIA can easily implement large populations of networks, as required by genetic algorithms and simulated annealing (see sect. 3.1), at a cost of some more external memory. The solution consists in \virtualizing" on the same synaptic array the dierent members of the population. The weights of each member shall be stored in a dierent area of the external memory and from there moved in blocks into the synaptic array. This solution is well suited to CPWM, thanks to its coherent nature. Provided that capacitor refresh can be made suciently fast, weight matrices can be changed at every CPWM clock cycle (or at every n-th cycle), during the idle phase. A prototype of an array of low power D/A converters has been designed (size is 350  250m2 ). A conversion time of 100ns with about 11mW power dissipation per converter are feasible. For an array of 32 converters, these gures correspond to an update rate of about 108 weights/s, with a total power dissipation of about 350mW (at highest refresh speed). As shown in g. 1, virtual networks are also used in CINTIA to interface the NN to the FSA. The latter selects what block of the external digital weight memory shall be used to refresh the neural weight matrix, therefore selecting the desired Neuro-Fuzzy characteristic.

4.6 On-chip learning

At present the CPWM chip has no on-chip learning capability, therefore learning of the NN is done by the associated microcontroller (see sect. 6.1), which modi es the neural weights stored in the digital weight memory

Figure 6: Microphotograph of an Analog to CPWM converter (size is about 370200 m2 ). (see g. 1). A new single-chip version of the CINTIA system, which is currently under design, will also feature direct on-chip learning (see sect. 4.3).

5 Analog to/from CPWM Conversion Within real-time controllers, the Neuro-Fuzzy network must interact with an external world which is intrinsically analog, while CPWM systems internally operate with pulses of xed amplitude and variable width. It is therefore necessary to perform a conversion from analog inputs to CPWM signals (A/PS) and from these back to analog outputs (PS/A). This section describes several analog to/from CPWM converters. As shown in g. 6, most of these circuits have been worked out as I/O pads, manufactured and tested, with the purpose of building a library of \Standard-Cells" for Neuro-Fuzzy ICs. These pads are used as the analog I/O interface in the chip shown in g. 5.

5.1 Analog to CPWM conversion

Two dierent methods for A/PS conversion have been considered: waveform-driven and capacitor-discharge. In both cases input voltage ranges of about 100mV to 4V can be obtained (with single 5V supply).

Waveform-driven converters (see g. 7)

are based on the binary comparison between the analog input signal Vi and an externallygenerated triangular wave Vr synchronous with

Capacitor-charging conversion is based

Figure 7: Schematic diagram of a waveformdriven A/PS converter.

on charging a capacitor CT with a constant current IZ for all the duration of the input pulse. At the end of the active phase, capacitor voltage is sampled and transferred to the output. The transfer function of the converter is:

Vo = Vmin + CIZ Ti : T

(6)

Further details, together with other PS/A the master clock CCK. Output pulse width is converters (e.g. waveform-driven) and perproportional to input amplitude: formance measurements on prototypes can be found in [2]. V , V i min TXO = Tmax V , V ; (4) max

min

where Vmin and Vmax are the lowest and highest values of Vr , within the duration of the active phase. Input dynamic range is easily adapted to the requirements by tuning the amplitude of the triangular wave. Further details, together with other A/PS converters (e.g. capacitor-discharge) and performance measurements on prototypes can be found in [2].

Non-linear conversion Another advantage

of this type of A/PS conversion is the possibility of a non-linear conversion, using nontriangular waveforms Vr0 = f (t). The resulting transfer function depends on the \inverse" of the waveforms used:

TXO = f ,1 (Vi )

(5)

Non-linear conversion can be used both to compensate non-linear sensors and to improve the performance when controlling strongly nonlinear systems. This method is also used in CINTIA to compute the sigmoidal squashing function within the neuron body, by using the inverse of a sigmoid for Vr0 (t).

5.2 CPWM to analog conversion PS/A conversion can be of two types: waveform-driven and capacitor-charging. In both cases output voltage ranges of about 100mV to 4V can be obtained (with single 5V supply).

5.3 Interfacing eectors

Most voltage-controlled eectors (e.g. DC motors, lamps, LED, heaters, analog and digital voltmeters) can be driven directly using CPWM signals through simple ON/OFF buers. This solution relies on the fact that the average value of a CPWM waveform is proportional to TTOi = TTmax O i . Direct driving presents relevant advantages for four main reasons: there is no need for PS/A conversion, with an increase in accuracy; ON/OFF power buers are much simpler than analog ones (a HEXFET is often sucient); it adapts to virtually any voltage range; galvanic isolation is simpli ed (e.g. an optocoupler). In some cases, when the eector has a fast response and cannot average the energy of PS (e.g. piezoelectric, oscilloscopes), a PS/A converter is required [2].

6 Hardware Implementation The main goal of CINTIA is to study the feasibility of a single-chip Hybrid Intelligent Controller. Since the proposed system is still at the prototyping stage, it has been made of discrete components mounted on a single PCB, as shown in g. 8.

6.1 The prototype board

The system is currently based on a commerc programmable microcontroller, cial 68HC11 which emulates the FSA part of CINTIA and handles communications with the programming environment (via a RS232 interface). The

6.3 Programming environment

Figure 8: The prototype board of CINTIA. microcontroller is tightly interfaced to the 33  32 synapse CPWM chip described in sect. 4, via a digital weight memory (for weight refresh) and some glue logic. The chip uses as analog I/O pads the A/PS and PS/A conversion pads described in sect. 5. As said before, at present NN learning is also done o-chip by the microcontroller. c is an advanced 8The Motorola 68HC11 bit microcontroller with sophisticated on-chip peripheral capabilities and on-chip memory (8 KB of ROM, 512 bytes of E2 PROM and 256 bytes of static RAM). The prototype board, developed in house, has dierent external interfaces, such as: RS232 direct PC interface, external D/A converters, external program memory and external board expansions with Xilinx FPGA. That particular microcontroller has been chosen because of its in-house availability and not because of its many capabilities. In practice only those capabilities have been used which will be included in the foreseen single chip version of CINTIA.

6.2 Analog to digital interface

c has its own A/D conAlthough the 68HC11 verters, all analog signals are processed directly by the neural chip, which implements the analog neural controller. The microcontroller is con ned to handle all binary signals (including thresholded input/output values) and, in this prototype, also NN training. Up to sixteen input signal conditioning circuits and few output power drivers can be mounted directly on the prototype board, for direct interface with the plant.

A exible programming environment is currently under development, which can exploit all the capabilities of CINTIA. As described in sect. 3, CINTIA can deal with a number of different control strategies and the programming environment must face all those alternatives. It will therefore be possible to develop a controller using a combination of dierent methodologies. Some of the possibilities which have proven to be more useful are:

 To design, simulate and tune a Fuzzy controller and then automatically train the NN engine of CINTIA using Backpropagation (Neuro-Fuzzy approach).

 To design a Fuzzy controllers, which can

be optimized using GA+SA algorithms. Then train the NN engine as described above.

 To design a Neuro controller (either

trained from a Fuzzy one, or from a HW reference) and then optimize its performance using GA+SA (or Backpropagation, whenever possible). This is an example of Neural controllers with o-line training. In this case the correspondence to the Fuzzy description may be lost.  To design a Neuro controller and then tune it using inverse control strategies. In this case the NN engine of CINTIA will receive multiplexed inputs relative to both the plant emulator and its copy (see g. 2).  To design several controllers, one per each of the plant's dierent discrete states and then to combine them either using the FSA approach (this may cause abrupt changes in the controller characteristic), or using Fuzzy methods (this gives smoother characteristics at a cost of worse overall performance). It is worth noting that the programming environment can optimize controller performance both o-line (i.e. using a simulator of the plant) or on-line, i.e. with CINTIA directly inserted in the control loop. Apart from dynamic performance (i.e. speed, response and settling

times, etc.), the programming environment can also optimize additional plant properties, such as power consumption, trajectory smoothness, etc. At present only the most useful routines have been developed although these have not yet been integrated into a common framework. So far all the routines have been written primarc language and some ily using the MATLAB of its toolboxes.

7 Applications of CINTIA The CINTIA system described in the previous sections is currently being used in several control and robotic applications. Some of them which have been considered so far are: magnetic bearings, autonomous vehicles (i.e. a \hexapod-like" walking system), a 2-D cart- Figure 9: A magnetic ball bearing system conpole balancer system in polar coordinates, and trolled by CINTIA. several others. Follows a short description of the most interesting ones: ferent genomes before the controller reaches M  1:5e1 ). Further details are found in [8].

7.1 Magnetic bearing

We have considered for this demonstrator a one-axis magnetic bearing [8], which is a rather simple problem, yet non linear and intrinsically unstable. As shown in g. 9, a metallic sphere is lifted by means of an electromagnet. The magnetic force FE shall balance the force of gravity mg and the inertia mx: The electromagnet-sphere system is controlled as part of a closed loop, where a PID is often used as the controller. The PID performs properly only in the linear zone around the target position x  0. As an example, this system has been controlled using various combinations of PID, Neuro-Fuzzy and genetic algorithms [8]. Table 1 compares the dierent control strategies in terms of the asymptotic RMS error e1 (in mm), the number TC of learning iterations needed to reach an error M  1:5
e1 , the size of the learning population (i.e. number of weight sets needed), the size of memory required (i.e. number of weights or PID coef cients times the size of the population) and the number of \trials" (i.e. number of times the controlled system is stimulated with dif-

7.2 Walking hexapod An autonomous walking machine is under development, which has a structure similar to that of a hexapod. Six identical legs (see g. 10) are controlled using CINTIA. Each leg has two completely dierent states, for the forward and the backward steps, respectively. The FSA tracks the leg's state and modi es the NN weight matrices accordingly, while the states of the six legs are coordinated by the FSA. The outputs from the NN control the driving current of the motor (i.e. corresponding to the control of the leg's pressure on the ground). This approach has provided better performance than controlling the motor supply voltage.

7.3 2-D pole-cart balancer The traditional 1-D pole-cart (broom) balancer has been converted to a more complex 2-D balancer working in polar coordinates (that is, the cart can either go back and forth or turn left or right, but it cannot move aside). The only possibility to balance the pole falling aside is therefore to turn (either left or right) and then

Method

PID NN GA SA GA+SA

1 TC Size of Memory size Number of Training (iterat.) (mm) population (bytes) trials 0.75 0.69 0.23 0.68 0.30

12 8 10 17

1 1 50 4 4

4 38 200 16 16

12 400 80 136

on HW SW on HW on HW on HW

Table 1: Performance comparison of dierent cognitive methods. 8 theta force

theta (degrees), force (N)

6

4

2

0

-2

-4

-6 0

2

4

6

8

10 time (s)

12

14

16

18

20

Figure 11: Plot of pole's angle from the vertical  and force F applied to the cart wheels, versus Figure 10: A hexapod leg controlled by CINTIA. time.

8 System Performance to move into the new direction. This problem is much more challenging than the 1-D or the 2-D with x-y motion capabilities, due to some idiosyncrasies which may arise controlling in polar coordinates (e.g. several controllers generate an equilibrium trajectory which is a growing spiral). Using the NeuroFuzzy approach described in sect. 3, it has been possible to make the system behave properly. Fig. 11 shows a plot of the pole's angle from the vertical  and the force F applied to the cart wheels, as a function of time. As can be seen, the cart can balance to pole to within  3 degrees from the vertical. This value cannot be reduced since it is due to the time the cart takes to turn by about 90 degrees when the pole falls aside. The plot is the result of a detailed simulation, since the hardware is still under manufacturing.

This section presents a theoretical analysis of the performance of the proposed CPWM Neuro-Fuzzy system. Power dissipation, response time, computation energy and the speed vs. accuracy tradeo have been considered and they are shortly described below. Data presented here are valid for fo = 139kHz. Other data are available in [2, 5, 10].

8.1 Power dissipation Dynamic Power Dissipation in the Digi-

tal Part of the NN is mainly caused by charging and discharging the parasitic capacitances. The average power dissipated by each synapse is function of CPWM frequency [2]. Postlayout simulations gave an average power dissipation of about PD  530nW per synapse. Active Power Dissipation in the Analog Part of the NN is due to the supply current drawn by transistors M + , M , , only when in-

coming pulse is at \1":

PA = Vdd Ion (7) where Ion = (IM + IM , ) is the supply current +

in the ON state. In the proposed CPWM system, Ion  2A and PA  10W. No power is dissipated when input pulses are at \0".

transition from one state to another. The actual value depends on the nal controller architecture that will be chosen for the nal singlechip version and it is still a matter of study, yet a very rough estimate can be given of about 1 , 10nJ per state transition.

Supply Power of A/PS and PS/A con- 8.3 Speed vs. accuracy tradeo verters can be made very small, for most types The accuracy of CPWM multipliers and conof converters. A power consumption lower than 50W per converter has been measured from several prototypes, which corresponds to a conversion energy below 300pJ. Supply Power of the FSA controller can be kept quite small, since it will be running at a very low clock frequency. An average frequency of 100,1000Hz is certainly high enough for several applications. At such low frequency, an average power dissipation of less than 1 to 100W can be achieved.

8.2 Response time

Neural response time TS is the time re-

quired to accurately compute a whole matrixvector multiplication. Since CINTIA operates synchronously with the CCK clock, TS = TO = 7:2s. Computation Energy EC (expressed in J per connection) is the product of response time TS by the average power dissipation of each individual synapse:

EC = TS (PD + PAi )

(8)

The theoretical worst-case computation energy of the proposed CPWM system is about 60 pJ per connection, which is so far the smallest gure among all existing implementations (see tab. 2). A slightly larger gure of 75pJ has been measured from prototypes, since it also includes power dissipation of neurons. This corresponds to less than 10mW power dissipation for 140MCPS (i.e. 1024 synapses at fo  139kHz) or, for instance, 0:75W for 10KCPS. For the FSA controller, it is more dicult to de ne some equivalent of the computation energy, since its functions are less well de ned. Yet, a State Transition Energy ES can be de ned as the average energy required to make a

verters is function of the overall \time accuracy"
T achievable from threshold comparators, switches, sample-and-hold circuits, signal skews, rising and falling times of digital signals, etc. A rough estimate of the relative error i is: i = 
max (9)  
T 
T : i

Tmax TO For a given value of
T , the error can be reduced only by increasing TO . Since TO is in-

versely proportional to the per-synapse processing speed SC = T1S , the following constraint must be satis ed:  
TSC (10) A reasonable compromise has been found by choosing Tmax = 6:3s and TO = 7:2s, which gives about 1:5% error for
T = 100ns, at a speed of 139KCPS per synapse. A more detailed analysis can be found in [10].

8.4 Comparison with other techniques

Table 2 compares the performance of the CPWM Neuro-Fuzzy system with several other ANS hardware implementations ( [1, 4, 3, 5], et al.). Data for analog and digital devices have been extracted from [4], although gures (both size, speed and power) have been \scaled" (either up or down) to a generic 1:5m CMOS technology according to well established scaling rules, to allow for a fair comparison. Furthermore all values have been \normalized" to approximately the same error   1:5% (an equivalent of 6 signi cant bits). The table shows that CPWM has the lowest power dissipation and computation energy gures, while synaptic size and response time are

SYSTEM

SYNAPSE CONNECTIONS COMPUT. RESPONSE POWER SIZE PER SECOND ENERGY TIME DISSIPATION (1:5m CMOS) (per chip, 50mm2) (per synapse) (103 m2 ) (106 =s) EC (pJ) TS (s) (W ) CPWM 5 - 20 100 - 500 60 - 600 5 - 10 10 - 100 CPWM(y) 20 - 100 10 - 100 600 - 6.000  10 50 - 500 ANALOG 10 - 50 20 - 500 500 - 15K 2 - 50 75 - 1.000 DIGITAL 500 - 5.000 10 - 500 10K - 1M -

Table 2: Performance comparison among dierent silicon implementations of ANS, for   1:5%, using a typical 1:5m CMOS technology. (y for virtual networks, including external memory and D/A converters). comparable with analog. The main advantages of CPWM neural systems with respect to analog circuits of comparable accuracy are, among others [10]:

 PS multiplication is intrinsically linear,

since it operates in the time domain and it is based on integration, which is a linear operator.  Current generators are always used in either of two operating points (ON/OFF), therefore they need not be so linear as in analog multipliers.  The dynamic range of PS multipliers is higher than that of analog ones (in excess of 3 decades).  Waveform-driven non-linearities may operate with less supply power than analog ones. The FSA controller is not yet included in this comparison, since it is not yet implemented as an ASIC and performance data are not yet available. Data obtained by the prototype board would be irrelevant, since these are relative to a commercial microcontroller which is far from being optimized for the proposed approaches. Yet, from preliminary analyses, it can be estimated that power dissipation of the FSA controller can be a fraction of the overall power dissipated by CINTIA.

9 Conclusion The paper has presented CINTIA, a real-time Neuro-Fuzzy controller based on a pulse stream neural chip. The system mixes analog neural

controllers together with nite state automata and supports a variety of dierent intelligent control strategies. A prototype of the system has been manufactured and it has been used to control dierent mechanical systems. A programming environment makes the use of the system and controller design a simple and straightforward task. The neural chip is based on pulse stream computation and it has mixed analog/digital synapses with analog dierential weight storage, while the nite state automata are currently implemented on a commercial microcontroller. Recon guration and multiplexing allows exible network topologies and a number of control strategies suited to intelligent control. A single chip version of the system, incorporating all the elements of the prototype is currently under design.

Acknowledgments The authors wish to thank Drs. Eduardo Miranda and Luca Sensi for their helpful contributions in simulating parts of the system.

References

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