Design of a 2 GHz GaAs HBT-based Class-E power amplifier Dusan Milosevic, Johan van der Tang and Arthur van Roermund Eindhoven University of Technology (TU/e) Department of Electrical Engineering, Mixed-signal Microelectronics (MsM) Group, EH 5.28 P.O. Box 513, 5600 MB Eindhoven, The Netherlands phone: +31 40 247 3393, fax: +31 40 245 5674 email:
[email protected] Abstract— This paper presents a design procedure for the GaAs HBT-based Class-E power amplifier for 2 GHz. An empirical approach, based on load-pull and source-pull simulations has been used to find an optimal impedance point for high efficiency operation. The simulation results show that a single-stage single-ended Class-E PA can achieve PAE higher than 70 %, output power of 24 dBm and transducer power gain of 15 dB when driven from a standard 50 Ohm signal generator. Three different solutions for the implementation of the load network are discussed, including both lumped and distributed components. Keywords— Power amplifier, Class-E operation, HBT
I. I NTRODUCTION High-efficiency power amplifiers are required for many RF and microwave applications. In a transceiver, the power amplifier (PA) is typically the most power-hungry block and to a large extent determines the overall power consumption of the system. Particularly the rapid development of mobile communication systems has put efficiency of PAs in focus. Mobile terminals are battery operated devices and the talktime of a handset will strongly depend on efficiency of the power amplifier in it. More efficient PAs will enable a smaller and lighter battery and/or a longer talktime, and consequently will make the final product more attractive in the market. Therefore, there is a strong interest to pursue development of PAs with a high efficiency of power amplification. Power amplifiers are traditionally categorized into the classes of operation, based on the quiescent operating point and the way in which the transistor is operated. In this paper we focus on the design of a Class-E power amplifier for operation at 2 GHz. The Class-E PA was introduced by the two Sokals in 1975 [1] and belongs to the family of switching type power amplifiers. Over the years, a lot of research on this intriguing type of circuit has been done and published and some of the classic papers include [2] - [5]. Class-E circuits have been successfully
designed and implemented in various technologies and in different frequency bands. In many papers it is shown how the circuit deviates from its nominal operation when different kinds of non-ideal effects are taken into account. These effects include finite-inductance DC-feeding coil, finite Q-factor of the load network, non-zero fall time of the collector/drain current, variations in duty cycle, nonlinear capacitances of the device etc. Most of the time a single effect and its impact on the circuit operation are investigated. However, when all of these effects are simultaneously combined, the Class-E operation becomes enormously complex and analytically intractable problem. Therefore, a more practical procedure in the circuit design may be needed. In this paper, we present an experimental approach based on load-pull and source-pull simulation techniques. The main goal is to optimize operation of the circuit for high power added efficiency (PAE) and desired output power, while staying within the boundaries of the Class-E operation. The circuit is based on the realistic model of a GaAs HBT device and takes into account parasitic elements that would inevitably occur in the practical implementation of the PA. The paper also investigates three different implementations of the load network, which result in a relatively similar performance. The structure of the paper is as follows. In section 2, the basic principle of operation of the Class-E PA is briefly reviewed. Section 3 explains the design procedure and considers possible implementations of the load network. The simulation results are discussed in section 4, followed by the conclusion in section 5. II. T HE C LASS -E
PRINCIPLE OF OPERATION
In this section the principle of operation of Class-E PAs will be revisited, together with the original design equations for its circuit elements. The equivalent circuit diagram of the basic Class-E PA is shown in figure 1. The circuit consists of an active device (which is shown as a
switch), shunted by a capacitor C p , an RF choke (RFC), a series LC resonator Ls Cs , an additional reactance X and a load resistance R. For the purpose of analysis, it is necessary to take the following assumptions: 1. Transistor is modeled as an ideal switch, i.e. short circuit in the ON state and open circuit in the OFF state, with instant switching action. 2. The switch is operated with the 50 % duty-cycle, at the carrier frequency ωc . 3. The switch can sustain the current running through it in the ON state and also must be able to stand the non-zero voltage that appears during the OFF state. 4. The RF choke (DC-feeder) has a very large inductance and accordingly allows only DC current to flow through it. 5. The Q-factor of the of the series resonator Ls Cs is high enough, so it can be considered that a purely sinusoidal current is running through the load R.
of circuit elements:
ZL jωc ZL jnωc
I dc isw(t)
23
(1) (2) (3)
where ωc is the angular frequency of operation and R is the load resistance (see fig. 1). The load resistance is essentially determined by the required output power and supply voltage as V2 (4) R 0 577 dc Pout
The characteristic Class-E waveforms corresponding to this ideal case are given in figure 2.
isw(θ) Ipk Idc
tuned @ ωc
Ls
Cs
v x jX
θ
ic(θ)
ic(t) iR(t) v c(t)
j1 152
∞ n 0 1836 ωc RL
Cp
V dc
RFC
R1
R
Cp Z L(jω)
Fig. 1. Equivalent Class-E circuit
A unique property of the Class-E operation which distinguishes it from other types of switching-mode PAs is the so-called ”soft switching”. It means that the circuit operation is arranged in such a manner that the shunt capacitor is never discharged through the switch. In other words, the switch closes precisely at the instant where the shunt capacitor is completely discharged. In addition to that, the slope of the capacitor voltage vc t at the instant of turn-on is also set to zero. The carefully arranged transient response of the load network in conjunction with the switching operation guarantees that there is no overlap of the simultaneously non-zero values of the device current and voltage. This type of operation results in high efficiency of power amplification, theoretically 100% if the passive components in the circuit are lossless. The Class-E analysis has been performed many times in the literature [2] - [6], and only the final design equations for circuit elements will be given here. Under the previously stated conditions and adopted assumptions, an optimal Class-E operation results for the following values
θ
v c(θ) Vpk
π
0 ON
2π
θ
OFF
Fig. 2. The characteristic Class-E waveforms
III. D ESIGN
PROCEDURE
Having reviewed the principle of operation of the ClassE power amplifier, in this section we will present a design procedure for the circuit based on a GaAs Heterojunction Bipolar Transistor (HBT). Our goal is to design a circuit for operation at fc 1 95 GHz and with output power of Pout 250 mW. A modified Gummel-Poon model is used for simulations. The first step in the design procedure is to analyze the DC I-V curves of the appropriately sized HBT device. In the Class-E operation, the peak collector/drain current can reach the value I pk 2 86Idc and the transistor
needs to be sized in accordance with this criterion. For the given supply voltage and desired output power, and knowing that the ”knee” voltage of the device and other losses will decrease the efficiency, we have estimated the peak collector current to be approximately 300 mA. The HBT process that we consider allows the maximum collector current density of JCmax 0 2 ma µ m2 . Therefore, assuming the maximum collector current of approximately 320 mA, we have chosen the emitter area of AE 1600 µ m2 . The transistor output characteristics (Ic vs. VCE ) and the Class-E load-line are given in figure 3. In the ”ON” state,
Fig. 3. The DC I-V characteristics of the HBT and the Class-E loadline
the transistor is in saturation, and the voltage drop across its terminals is VCEsat . Therefore, the ”effective” supply voltage becomes Ve f f
VCC
VCEsat
(5)
and this value should be used for calculation of the output power in eq. 4. Thus, by taking Ve f f 2 7V and equations 4 and 3, we obtain the load resistance R 16 8 Ω and the shunt capacitance C p 0 89 pF. A schematic of the Class-E circuit with conceptual matching networks is shown in fig. 4. IMN and OMN represent the input and output matching network, respectively. Inductors Lc and Le are the estimated parasitic inductances of the bondwires and emitter (backside) vias. For accurate simulations, it is necessary to take these parasitic effects into account, although their values, at first glance, may seem to be negligible. The base biasing is set by VBB and Rb to keep the device slightly in conduction in the absence of RF drive signal. Cb is a DC blocking capacitor and Lb is the parasitic inductance of bondwires on the input side of the die. The DC-feeding RF choke from fig. 1 is replaced by a more practical finite inductance L1 . Such an inductor has a lower DC resistance than a high-inductance coil and
consequently introduces lower losses. In addition to that, a lower inductance enables an easier realization of the Envelope Elimination and Restoration technique, which can be used for implementation of high-efficiency linear transmitter [6], [7]. The design problem is now reduced to finding suitable impedances ZL and ZS to be presented to the transistor. First we will focus on impedance of the load network (LN), ZL jω . Equations 1 and 2 clearly define conditions that the Class-E load network should satisfy. However, these equations hold for an unrealistic, highly idealized case of the Class-E operation. A practical circuit will exhibit a number of deviations from the idealized Class-E operation, such as non-ideal switching, presence of some harmonic currents in the load network, variable current through the DC-feeding inductor etc. Therefore, it is necessary to find impedance conditions that will provide an optimum performance from the efficiency point of view. However, when many non-ideal effects are simultaneously combined, the circuit operation becomes analytically intractable problem. In this work, we have adopted an empirical approach in search for the optimum load network impedance. First, the available source power Pavs is initially set at a sufficiently high level to provide a good switching operation of the transistor, regardless of the mismatch conditions at the input. Then, we have swept the value of ZL jωc across the range of impedances in the Smith chart, performing an exhaustive search for the optimum impedance point. During this procedure, the output power, DC-to-RF efficiency (η ) and the circuit waveforms have been monitored. While sweeping ZL jωc , harmonic impedances ZL jnωc have been kept at very high (reactive) values. The circuit operation has been simulated using harmonic balance analysis. When a well defined impedance point ZL jωc Zopt for high efficiency operation has been established, a load network depicted in fig. 5 has been designed to transform a standard 50 Ω termination to the desired impedance point Zopt at the fundamental frequency ωc . The frequency response of the network has then been simulated at harmonic frequencies, and the corresponding values have been substituted in the load-pull setup for resimulation of the circuit. Thus, the search for the optimal impedance has been repeated and necessary adjustments have been made to the final value of Zopt . During this iterative load-pull procedure, the collector voltage and current waveforms have been closely monitored, to make sure that the circuit operation stays in the Class-E mode. Now that the load network configuration has been fixed, a similar procedure is performed for the input port, i.e. an exhaustive search for the source impedance ZS jωc that will provide a good match and consequently a good
L BB
V CC
V BB Rb Lb
Lc
L1 OMN
Cb
IMN
HBT
50 Ω
50 Ω
Cp
Le
Pavs
ZS
ZL
Fig. 4. Class-E PA circuit with conceptual input and output matching networks L2
of the Class-E operation [2]. We have focused our design on obtaining high PAE for the target output power of 24 dBm. Thus, the impedance point corresponding to marker m3 in fig. 7 represents a good overall compromise, with Pout =24 dBm, PAE=70.1 % and transducer power gain of 15 dB. These results include estimated losses in typical SMD components that can be used for practical implementation. In figure 8, the simulated waveforms of the collector voltage and current are given and they show that the circuit is operating in the Class-E mode.
C2
50 Ω
C3 Z L (jω)
Fig. 5. Load network LN1
power gain and power added efficiency (PAE). During the variation of ZS jωc , the available source power Pavs has also been changed, i.e. gradually decreased from the initially preset value, which was high because of mismatch conditions. Again, the key parameters (output power, efficiency, gain and waveforms) are observed during the tuning procedure, in order to find an acceptable value of ZSopt . A simple matching circuit shown in fig. ZS jωc 6 is then designed, to transform the generator impedance of 50Ω to ZSopt .
Fig. 7. Load-pull simulation of the Class-E PA
LIN 50 Ω CIN Pavs
Z S (jω)
Fig. 6. Input matching network
IV. S IMULATION
RESULTS
The design procedure described in the previous section produces a set of constant output power and constant PAE contours in the impedance Smith chart. In fig. 7, these contours together with the optima for maximum PAE and maximum Pout are displayed in the 50 Ohm impedance chart. The simulated peak PAE is 72 %, and the constant PAE contours are given with the step of 5 %. The maximum output power is 26 dBm, and the constant Pout contours are given with the step of 0.5 dB. The two optimum points do not coincide and this is a normal behavior
Fig. 8. Simulated collector waveforms
The Class-E principle of operation requires certain impedance values to be presented to the transistor at the fundamental frequency and at the harmonics, but does not imply a structure of the load network. In figures 9 and 10, another two possible solutions for the load network are shown, but based on distributed elements (transmission lines) instead of lumped ones. The solution shown in fig. 9 (LN2) is based on the concept similar to that described in [8], while as the network in fig. 10 (LN3) offers
a relatively similar performance with a smaller and simpler structure. The simulated impedance responses of all three load networks (LN1-LN3) are displayed in fig. 11 in the 50 Ohm impedance Smith chart, from the fundamental frequency to the 5th harmonic. The main loss in the circuit is due to non-ideal switching operation of the transistor. During a part of the RF cycle, there is overlap of considerable collector current and voltage values. Also, in the ON state, the saturation voltage of the transistor VCEsat imposes a theoretical limitation to the DC-to-RF efficency of η 1 VCEsat VCC . A careful design of the specific driver stage could potentially improve the efficiency performance of the circuit. A part of the drop in the efficiency is caused by losses in passive components, and simulation shows that this loss is around 5 % of PAE for practical 0201 SMD components.
TL2 TL1
TL4 TL6
TL 3
TL5
50 Ω
Fig. 11. The impedance responses of the load networks LN1, LN2 and LN3
tions for the switching-type operation, a relatively high efficiency and satisfactory performance have been achieved. Three different solutions for the implementation of the load network are shown. ACKNOWLEDGMENTS
Z L (jω)
Fig. 9. Load network LN2 with distributed elements TL1
The work presented in this paper is funded by the Dutch technology foundation STW. The authors would like to thank STW for their financial support. R EFERENCES
TL 2
50 Ω
Z L (jω)
Fig. 10. Load network LN3
V. C ONCLUSION A design of the Class-E PA is not a trivial task at RF frequencies. A number of non-ideal effects is present and the nominal Class-E design equations do not provide conditions for an optimum performance. In this paper, we have presented a design procedure based on load-pull and source-pull simulations. A certain part of the impedance space has been exhaustively searched for the load and source impedances that would provide a high efficiency of power amplification while achieving desired output power. The simulation results show that the Class-E circuit, based on a GaAs HBT device, achieves PAE higher than 70 % with Pout =24 dBm and 15 dB transducer power gain. Although a sine wave drive does not provide optimal condi-
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