Electrical memory features of ferromagnetic CoFeAlSi nano-particles embedded in metal-oxide-semiconductor matrix

Thin Solid Films 519 (2011) 6160–6163

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Thin Solid Films j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / t s f

Electrical memory features of ferromagnetic CoFeAlSi nano-particles embedded in metal-oxide-semiconductor matrix JaBin Lee a, KiWoong Kim b, JunSeok Lee a, GwangGuk An a, JinPyo Hong a,⁎ a b

Novel Functional Materials and Devices Laboratory, Department of Physics, Hanyang University, Seoul 133-791, Republic of Korea Semiconductor R&D Center, Samsung Electronics Co. Ltd, Gyeonggi-Do 445-701, Republic of Korea

a r t i c l e

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Article history: Received 14 September 2010 Received in revised form 5 April 2011 Accepted 6 April 2011 Available online 13 April 2011 Keywords: Sputtering Heusler material Co2FeAl0.5Si0.5 Nanoparticles Metal-oxide-semiconductor Capacitance–voltage

a b s t r a c t Half-metallic Heusler material Co2FeAl0.5Si0.5 (CFAS) nano-particles (NPs) embedded in metal-oxidesemiconductor (MOS) structures with thin HfO2 tunneling and MgO control oxides were investigated. The CFAS NPs were prepared by rapid thermal annealing. The formation of well-controlled CFAS NPs on thin HfO2 tunneling oxide was confirmed by atomic force microscopy (AFM). Memory characteristics of CFAS NPs in MOS devices exhibited a large memory window of 4.65 V, as well as good retention and endurance times of 105 cycles and 109 s, respectively, demonstrating the potential of CFAS NPs as promising candidates for use in charge storage. © 2011 Elsevier B.V. All rights reserved.

1. Introduction Nonvolatile memory devices, particularly current floating gate devices, are approaching their fundamental limits and face reliability issues, such as tunneling-oxide scaling, short charge retention, and limited cycling endurance. Therefore, next-generation devices like nano-particle (NP) memories are proposed to improve their immunity to tunnel oxide defects and reduce capacitive coupling effects [1,2]. To avoid charge loss, NP memory device stores charges in mutually isolated crystalline NPs, instead of in continuous poly-silicon (Si) layers as in conventionally stacked gate memory. The NP system also offers several attractive characteristics, such as thin tunneling oxides, without sacrificing non-volatility, small operating voltages, fast write/erase speeds, and long endurance. The first NP nonvolatile memory devices were demonstrated by Tiwari et al. using Si NPs embedded in SiO2 [2]. Since then, numerous efforts to improve retention and reliability have been made to develop nonvolatile memory devices through various NPs [3–5]. The NP system can be scaled down and maintain good retention characteristics with thin tunneling oxide and low voltage operation. Among NP materials, metal NPs have several advantages, including higher density of state around Fermi level, a wide range of available work functions, and smaller energy perturbations compared to their semiconductor counterparts [6]. However, NPs with metallic and magnetic charac-

⁎ Corresponding author. Tel.: + 82 2 2220 0911; fax: + 82 2 2296 3738. E-mail address: [email protected] (J. Hong). 0040-6090/$ – see front matter © 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2011.04.024

teristics that may function as discrete charge traps have not been studied extensively up to now [7]. In this paper we present the charge storage performance of Cobased full-Heusler alloy Co2FeAl0.5Si0.5 (CFAS) NPs embedded in thin HfO2 tunneling and MgO control oxide layers as discrete charge traps. CFAS NPs were fabricated from a half-metallic ferromagnet material at room temperature (RT) by the rapid thermal annealing (RTA) process [8]. Structural and electrical properties of CFAS NPs embedded in metal-oxide-semiconductor (MOS) structures are discussed. 2. Experimental details An ultrathin HfO2 tunnel oxide was grown on (100) oriented p-type silicon wafers using an atomic layer deposition (ALD) method followed by the deposition of a thin CFAS layer with thickness of approximately 1 nm on the HfO2 tunnel oxide layer by using a rf sputtering system. For 1 nm film growth, the growth rate of CFAS thin film of about 50 nm thickness was calculated by AFM and SEM (scanning electron microscopy) measurements. From obtained growth rate, the sputtering time for CFAS thin film of 1 nm thickness was calculated. The annealing process was performed on the CFAS thin film with a RTA system at 700 °C for 30 s. According to several reported works [9–11], it is well-known that the minimum ordering temperature of CFAS film is about 400 °C. Therefore, we have determined the annealing temperature of about 700 °C after scanning various annealing range because we needed both the ordered crystalline structure and aggregation properties of CFAS film after RTA annealing process. The RTA process used in this experiment was wellcontrolled so that it did not affect the structural properties of the ALD-

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Fig. 1. (a) Schematic illustration of CFAS NPs embedded in MOS structure. (b) Typical M–H curve of CFAS thin film measured by the VSM system. (c) AFM image of CFAS NPs on the HfO2 tunnel oxide layer formed by the RTA process. (d) AFM image of as-grown CFAS film fabricated without the RTA process.

HfO2 tunneling oxide [12]. After the growth of the MgO (thickness 2 nm) control oxide layer by the rf sputtering system on this stack, the CFAS film gate electrode (circular with 200 μm diameter) and Ta capping layer were deposited by dc sputtering using metal mask. All deposition processes were carried out in 400 mPa. In this experiment, HfO2 tunneling oxide was prepared so that it would have attributes that allow reliable operation, such as low leakage current, since HfO2 exhibits good thermal stability with a Gibbs free energy of about −1.09× 103 kJ/mol [13]. The resultant CFAS NPs were analyzed with atomic force microscopy (AFM) in contact mode using a PSI XE-100, to obtain surface morphology. Magnetic properties were carried out by utilizing vibrating sample magnetometer (VSM) in external magnetic field range of −3.0 ×10−2 T to 3.0× 10−2 T. Memory characteristic measurements, such as capacitance–voltage (C–V) at 1 MHz in constant voltage mode and capacitance versus time (C–t) were performed with a Hewlett-Packard 4294A parameter analyzer and Keithly 4200 semiconductor system at RT to study the charge storage and retention effects of electron/hole traps in NPs.

Fig. 1(c) presents typical AFM images of the CFAS NPs that were formed on the HfO2 tunneling oxide layer before the deposition of the top MgO control oxide layer. As shown in Fig. 1(c), the average

3. Results and discussion Fig. 1(a) shows a schematic illustration of CFAS NPs embedded in the MOS structure. The MOS device had a stacking structure of Si/HfO2 (10)/CFAS NPs (1)/MgO (2)/CFAS (5)/Ta (10), with the numbers in parentheses representing the thicknesses in nanometers. Fig. 1(b) presents typical M–H hysteresis curves of as-grown 5 nm thick CFAS thin film that was investigated using a VSM. The coercivity of the CFAS thin film was about 1.5 × 10− 3 T. This paper does not focus on the magnetic effects of CFAS NPs on charge trapping characteristics. However, the magnetic properties of CFAS materials in MOS devices will potentially assist the realization of next-generation nonvolatile memory devices. Therefore, more detailed studies of the unique magnetic responses of CFAS NPs embedded in MOS structures are currently being conducted in order to enable an external degree of freedom in nonvolatile memory device work.

Fig. 2. Typical capacitance–voltage curves of MOS structure (a) with CFAS NPs, and (b) without CFAS NPs.

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diameter and center-to-center distance of neighboring NPs are observed to be about 50–70 nm and 50–80 nm, respectively. The average density was determined to be about 2.90 × 1010 /cm2. The mechanism of formation of the CFAS NPs is the thermal melting effect on CFAS thin film by the RTA process, which lasts only for a short time, after which the melted film joins together to form NPs due to the strain effect. As expected, aggregation effect from thermal energy results in about 1 nm thickness CFAS NPs which have half-spherical shape. Fig. 1(d) is an AFM image of the as-grown CFAS thin film grown without the RTA process, demonstrating a smooth surface over the whole area, as expected. Fig. 2(a) shows high-frequency (1 MHz) C–V loops of MOS devices containing CFAS NPs. As shown in this figure, a large hysteresis loop in the C–V loop over the 8 to −8 V voltage sweep originates due to the existence of three-dimensionally confined CFAS NPs. Because ΔVFB (flat-band voltage) increases up to 4.65 V with increasing applied sweep voltage, these charging behaviors suggest the existence of trap sites in the gate oxide layer caused by the CFAS NPs. The electrons in the deep inversion layer and the holes in the deep accumulation layer were injected from the Si substrate into the CFAS NPs, so that the direction of the C–V loop is counterclockwise. High-k control oxide concentrates the electric field across the tunnel oxide, and releases it across the control oxide under program and erase modes. Fig. 2(b) shows a typical C–V loop for our MOS structure without CFAS NPs in the gate oxide layer. As expected, the sample without CFAS NPs did not display hysteresis after the gate voltage sweep. The disappearance of the memory widow indicates that a charging effect only occurs dominantly with CFAS NPs in our MOS structure. The carrier trap density was estimated to be about 8.79 × 1012/cm2 [gate electrode area was π × (200 μm)2] using a simple formula: N = [(CHfO2 + CMgO) / q]ΔVFB, where (CHfO2 + CMgO) and q have values of 3.8 × 10−10 F and

1.6 × 10− 19 C, respectively, and ΔVFB is 4.65 V. A comparison with the density of the CFAS NPs (2.90 × 1010 /cm2) inferred by examination of AFM images implies that each CFAS NP can store about 300 electrons or equivalent positive charges. The programming and erasing characteristics throughout the operation of the dynamic capacitance measurement technique are shown in Fig. 3. The charge endurance and retention characteristics of CFAS NPs embedded in the MOS are displayed in Fig. 3(a) and (c), respectively. The endurance measurement at RT was carried out with electron/hole programming at a + 8 V/−8 V sweep. The flat-band voltage (VFB) was obtained from the C-V curves measured after each stressing. The CFAS NPs embedded in the MOS structures display a memory window of 4.65 V. As shown in Fig. 3(b), the VFBs for electron and hole charged states were +1.697 V and −2.953 V, respectively, before endurance measurement. Only a small change of 0.26 V in memory window size was observed after 103 cycles, as shown in Fig. 3(a). Extrapolation of data up to 105 cycles as shown in Fig. 3(a) suggests that the voltage drop at the memory window levels are maintained within about 0.44 V, which satisfies the basic requirements for nonvolatile memory devices based on discrete charge traps. Fig. 3(c) presents typical charge retention characteristics for CFAS NPs with gate voltages of ±8 V for 10 s. As shown in Fig. 3(d), the decayed capacitance for the memory capacitor with CFAS NPs was only 1.54% within a 104 s duration, indicating an excellent level compared with the results of prior investigations [4,13]. These improved retention characteristics in our work may be related to the formation of AlOx or SiOx oxidized phases that might take place through the RTA annealing process, surrounding the CFAS NPs. It is expected that the Al or Si atoms inside the CFAS composite film will easily bond with oxygen atoms during the annealing process, resulting in the sufficient formation of AlOx or SiOx oxidized phases

Fig. 3. (a) Extrapolated endurance characteristics of CFAS NPs embedded in the MOS structure. (b) Flat band voltage shift after 103 cycles of writing/erasing processes. (c) Extrapolated retention characteristics of the same device up to 109 s and (d) Raw measured retention characteristics during 104 s.

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(data not shown). These AlOx or SiOx phases may be associated with additional increases in electron/hole barrier width. Extrapolation of retention data measured up to 109 s indicates that the decayed capacitance levels remain within about 6.02%, as shown in Fig. 3(c), providing better charge retention characteristics than those observed in the results of our previous work evaluating Al particles [14]. The improvement in retention may be due to reduced lateral channel leakage as proposed by Hao et al. [15] and coulomb repulsion in the NPs proposed by Kim et al. [4] As mentioned above, the AlOx or SiOx oxidized phases surrounding the CFAS NPs on the tunnel oxide layer may lead to a sufficiently large additional charge trapping probability due to the enhanced barrier, resulting in low lateral leakage [16]. However, while the addition of AlOx or SiOx phases leads to enhanced retention characteristics, the programming and erasing speeds might be decreased enough to compromise the use of CFAS NPs as charging traps. 4. Conclusion In conclusion, we studied memory characteristics of half-metallic Heusler material CFAS NPs grown by RTA process. The formation of the CFAS NPs was confirmed using the AFM measurements. A clear counterclockwise hysteresis was observed in the C–V curve due to the charging effect in CFAS NPs, providing a memory window of about 4.65 V. In addition, responses such as retention time and endurance coupled with small charge loss rate may explain the fact that magnetic CFAS NPs are promising candidates for use in nonvolatile memory device applications.

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Acknowledgment This research was supported by “Leading Foreign Research Institute Recruitment Program” through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST). (No. 2010-00218). References [1] H.I. Hanafi, S. Tiwari, I. Khan, IEEE Trans. Electron Devices 43 (1996) 1553. [2] S. Tiwari, F. Rana, H. Hanafi, A. Hartsein, E.F. Crabble, K. Chan, Appl. Phys. Lett. 68 (1996) 1377. [3] F.M. Yang, T.C. Chang, P.T. Liu, U.S. Chen, P.H. Yeh, Y.C. Yu, J.Y. Lin, S.M. Sze, J.C. Lou, Appl. Phys. Lett. 90 (2007) 222104. [4] J.H. Kim, J.Y. Yang, J.S. Lee, J.P. Hong, Appl. Phys. Lett. 92 (2008) 013512. [5] J.H. Chen, W.J. Yoo, D.S.H. Chan, L.J. Tang, Appl. Phys. Lett. 86 (2005) 073114. [6] Z. Liu, C. Lee, V. Narayanan, G. Pei, E.C. Kan, IEEE Trans. Electron Devices 49 (2002) 1606. [7] S.L. Zhang, U. Smith, J. Vac. Sci. Technol. A 22 (2004) 1361. [8] T.M. Nakatani, A. Rajanikanth, Z. Gercsi, Y.K. Takahashi, K. Inomata, K. Hono, J. Appl. Phys. 102 (2007) 033916. [9] T. Furubayashi, K. Kodama, H. Sukegawa, Y.K. Takahashi, K. Inomata, K. Hono, Appl. Phys. Lett. 93 (2008) 122507. [10] W. Wang, H. Sukegawa, R. Shan, K. Inomata, Appl. Phys. Lett. 93 (2008) 122506. [11] W. Wang, H. Sukegawa, R. Shan, T. Furubayashi, K. Inomata, Appl. Phys. Lett. 92 (2008) 221912. [12] M. Houssa, High-k Gate Dielectrics, Institute of Physics, Bristol and Philadelphia, 2004. [13] J.Y. Yang, J.H. Kim, W.J. Choi, Y.H. Do, C.O. Kim, J.P. Hong, J. Appl. Phys. 100 (2006) 066102. [14] J.S. Lee, J.Y. Yang, J.P. Hong, Appl. Phys. Lett. 95 (2009) 052109. [15] M.Y. Hao, H. Hwang, J.C. Lee, Appl. Phys. Lett. 62 (1993) 1530. [16] O. Winkler, F. Merget, M. Heuser, B. Hadam, M. Baus, B. Spangenberg, H. Kurz, Microelectron. Eng. 61 (2002) 497.