Embedded Stress Sensors for Strained Technologies Process Control

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 21, NO. 3, AUGUST 2008

Embedded Stress Sensors for Strained Technologies Process Control Moustafa Kasbari, Student Member, IEEE, Romain Delamare, Sylvain Blayac, Christian Rivero, and Roland Fortunier

Abstract—Mechanical stress management becomes a major issue for state-of-the-art CMOS technologies. Mechanical stress induced by the process steps is often at the origin of yield losses but also opportunities for technologies performance enhancement. Usual methods for mechanical stress measurement generally require offline measurements and are not compatible with fast correction of process parameters. We propose here embedded stress piezoresistive sensors to allow fast monitoring of mechanical stress and enable real time correction of the process parameters. The test vehicle presented here is dedicated to the gate structure stress monitoring. It is especially very sensitive to the nitride contact etch stop layer stress level. It is shown, in particular, that the structure is able to monitor process-related stress change in the nitride layer. Its feasibility, sensitivity, and relevance in an advanced process control scheme are investigated. Index Terms—Advanced process control (APC), mechanical stress, nitride film, piezoresistive sensor, strained technology.

I. INTRODUCTION

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T is well known that mechanical stress is developed during the manufacturing process of CMOS microelectronic circuits [1]. This residual stress plays an important role in the devices’ reliability and often generates fabrication yield losses [2]. This phenomenon becomes of increasing importance as the complexity (integration density, number of metal levels, thermal cycling, packaging effects ) is growing. Furthermore, for few years, mechanical stress has been used to improve the transistors performance. For instance, stress memorization techniques (SMT) [3] and contact etch stop layers (CESL) [4] have been used successfully to increase charge carriers mobility and to minimize power consumption. It is therefore of major importance to put parameters in correlation with mechanical stress under systematic control along process flow, as close to real time as possible. This APC approach [5] dedicated to stress evaluation requires convenient stress monitoring methods. Conventional local strain-measuring techniques, like X-ray diffraction [6]

Manuscript received December 20, 2007; revised February 28, 2008. Published August 6, 2008 (projected). This work was supported in part by “Communauté du Pays d’Aix”, in part by the “Conseil Général des Bouches du Rhône”, and in part by the “Conseil Régional Provence Alpes Côte d’Azur”, through the focused research program called “Rousset 2003–2008” in partnership with STMicroelectronics. M. Kasbari, R. Delamare, and S. Blayac are with Ecole des Mines de SaintEtienne, Centre de Microélectronique de Provence, 13541 Gardanne, France (e-mail: [email protected]; [email protected]; [email protected]). C. Rivero is with STMicroelectronics Company, 13106 Rousset cedex, France (e-mail: [email protected]). R. Fortunier is with Ecole des Mines de Saint-Etienne, SMS, F-42023 ST-Etienne cedex 02, France (e-mail: fortun[email protected]). Digital Object Identifier 10.1109/TSM.2008.2001209

or Raman microscopy [7], are not easy to implement in a standard process flow or are destructive. It is more convenient to control the global wafer shape in order to reduce the global mechanical stress impact, but the local information is lost. Thus, in response to industrial environment, data collection has to be nondestructive, fast, easy to perform, low cost, and process compatible. For these reasons, it was chosen to develop embedded stress microsensors with electrical monitoring to be performed during the standard electrical test stages. We developed a test structure dedicated to gate stack (polysilicon, spacer, nitride film) stress monitoring. The reason for this choice is that monitoring of strain induced by transistors gates takes a particular importance as strained silicon devices come into production. The aim of this paper is thus to report the results obtained with the new test structure and demonstrate its relevance in an APC scheme. Section II introduces the principles of this piezoresistive sensor and the test structure design which is based on a plain standard Wheatstone bridge. Section III details the fabrication process. The electrical results obtained on an individual sensor as well on full wafer mapping are presented in Section IV while Section V is dedicated to the sensor calibration: a finite element calculation is developed to analyze the sensor stress environment and propose a sensitivity model. This test structure was integrated in products wafers and some variability in the sensor response was identified. The aim of the discussion in Section VI is to assess the sensitivity of the sensor and analyze the origins of variability. The sensitivity of the sensor to process-related stress variation is then shown, this demonstrates the potential usefulness of the structure in the framework of an advanced process control scheme. II. GUIDELINES FOR SENSOR DESIGN Using standard CMOS process steps was the main guideline for the design of this gate stack stress sensor structure. To have total process compatibility, it was convenient to use the piezoresistivity effect of silicon and monitor the resistivity change induced by the presence of the transistor gate. A large literature exists on piezoresistive stress sensors which concerns mainly the monitoring of externally imposed mechanical stress (for monitoring of packaging stress for example) [8]. Usually, resistor rosettes are used, or more complex structures based on MOSFET devices [9]. In the present application, the source of stress is internal to the circuit stack. In this case, the main drawback is that the effective resistivity change may be due not only to stress but also to process variations. As it was stated in [10], the piezoresistive effect induces variations in the order of a few percent, as cumulated process variations, wafer to wafer or within wafer, may induce overall resistance changes in

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KASBARI et al.: EMBEDDED STRESS SENSORS FOR STRAINED TECHNOLOGIES PROCESS CONTROL

Fig. 1. Schematic representation of a stressed Wheatstone bridge. The arrows represent the stress modification.

the order of 2%. For this reason, single sensors cannot be used here. The solution to circumvent this problem is to make a differential measurement, in other words to measure the resistivity change between two closely matched resistors: one standard and the other one with internal induced stress. The test structure is therefore based on a Wheatstone bridge including four resistors with two strained and two unstrained resistors (Fig. 1). We suppose that the four resistors have the same nominal value , the resistance variation induced by the stress is is measured as the current noted . Only the offset voltage can be expressed versus is swept. The resistance variation ) the current and the offset voltage (i.e., the offset resistance regarding the following equations: (1) is on the order of According to the piezoresistive effect, a few percent and can be neglected. This expression is reduced to (2) The use of a Wheatstone bridge allows contact errors free measurements and gives a response proportional to the resistivity difference between strained and unstrained resistor. This measurement technique allows solving the problem of across wafer and wafer-to-wafer variability since the compared resistors are in close match. The remaining variability is thus related to the ultimate resistor matching, on the order of 0.2%, well under the 2% overall resistor variability. In order to investigate separately the resistor matching, a second structure with no stress modification was also investigated. III. TEST STRUCTURE FABRICATION Fig. 2 shows the layout of the embedded test structure. Two sensors are placed in a standard contact pads module [Fig. 2(a)]. The first one (on the left) is composed of four boron implanted p+ resistors connected in a Wheatstone bridge configuration: named “Ref”. The second one (on the right) is composed of the same resistors with the same Wheatstone bridge configuration except that two opposite resistors are stressed by two standard gates stacks: named “Gate” [Fig. 2(b) and (c)]. One can notice that the gates are not electrically connected. The two gate structures can only impact the environmental stress state of the active silicon resistors. The resistor dimensions are chosen with high aspect ratio: . Their main axis is oriented along the Length/Width [110] silicon crystal orientation. All the resistors are rounded by shallow trench isolation (STI) and special care was taken to ensure that each one has the same environment. The transistor gates are fabricated along a standard CMOS process and deposited on the STI silicon oxide. Polysilicon

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film is deposited by low pressure chemical vapor deposition (LPCVD) at 700 C and lines are then etched. The line etching is performed by a 193-nm photo-lithography process compatible tool. The obtained lines are placed on the STI and oriented along the main resistor axis. Then, the nitride double spacers are built and the 900- nitride etch stop layer is deposited by LPCVD process at 700 C and 300 mTorr. Finally, the backend structures are processed. The study of the two different structures (Ref and Gate) has been performed by scanning electron microscopy (SEM). Fig. 3 presents a layout and an SEM cross-sectional view of a stressed resistor. In the picture, only the right half resistor is represented. The cross section is made in the 110 plane perpendicular to the resistor main axis. Polysilicon lines are above the STI and oriented along the [110] silicon crystal orientation, i.e., parallel to the main axis of the resistor. The reference bridge (Ref) presents the same physical characteristics as the strained one except that the gate structures are missing. IV. ELECTRICAL RESULTS All electrical measurements are performed on a dedicated high precision measurement system, consisting of a Keithley 4200 precision semiconductor parameter analyzer and a Suss Microtec PA200 semi-automatic probe station. Fig. 4 compares I–V characteristics between an unstressed reference (Ref) bridge and a stressed one (Gate) performed on a golden wafer site. The linearity of experimental data allows us to extract the slope with a high accuracy and then to estimate accurate values . As expected, the unstressed bridge of the offset resistor presents a very low offset voltage. A significant increase of is observed in the case of the stressed structure, and this demonstrates the mechanical coupling between the gate structure and the resistor. An individual structure thus shows, with respect to a reference structure, a clear deviation, which can be attributed to the additional gate stress. To further investigate the accuracy of the structure, a full eight inches wafer mapping was carried out on 31 sites. The results of measurements for the test structures Ref and Gate give the thanks to (2). These the relative resistance variation values are shown in cumulative frequency form in Fig. 5. From this sketch, the median value can be extracted. This . The standard devalue corresponds to the value at viation of each population can also be estimated from the slope at the median value according to the following formula: (3) As expected, the reference bridge has a median value very close to zero. Its distribution shows some variability which can be associated to the ultimate matching between the unstressed resistors (see Section VI). The Ref and Gate populations are clearly separated. This indicates a stress-induced resistance . The results are reported in Table I. change The reference value for is 1130 . V. CALIBRATION OF NITRIDE STRESS SENSOR We assume that the gate system disturbs the mechanical stress generated by the STI surrounding the resistors. In the hypothesis of a biaxial stress state modification along and across the main

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Fig. 2. Layout of the test structures (a) the standard contact pads module, (b) the stressed bridge (Gate), and (c) detailed view of a stressed and an unstressed resistors.

Fig. 3. Layout top view of a stressed resistor and SEM cross-sectional view of a half stressed resistor. The gate structures are on the STI and their long axis is perpendicular to the cross-sectional plane in the [110] direction.

Fig. 5. Comparison of the relative resistance variation distribution between Ref and Gate Wheatstone bridge (exp 1). The shift is due to the stress impact on the strained resistors. According to Fig. 7, this electrical shift corresponds to a 1-GPa stress level in the nitride film.

TABLE I EXPERIMENTAL STATISTICAL DATA EXTRACTED FROM DISTRIBUTIONS

Fig. 4. I–V characteristic of Ref and Gate bridges on a golden site.

resistor axis, we can estimate the effective stress level in the active area according to [11], [12]

(4) and are the silicon piezoresistive coefficient along and across the [110] direction. Considering previously extracted piezoresistive coefficients, a numerical calculation was performed to estimate the additional stress induced at the resistor by the gate structure to calculate the relative resistance change. This simulation also permitted to describe the stress

field in the gate structure and the mechanical coupling between the gate components and the active area. To correctly evaluate mechanical stress in microelectronic structures, a simple finite element model study is not relevant. A precise simulation of fabrication process has to be performed in order to describe the dynamic mechanical equilibrium of the structure at different process steps (geometry modifications and thermal cycling). In order to describe the mechanical stress field induced by the gate structure in the active area we have performed a 2-D finite element analysis (FEA) with Y-2006.06 SENTAURUS software. All materials are considered with a purely elastic behavior, oxides only are visco-elastic dependent. The analysis is based on the comparison between two simulations: we systematically calculated the average stress components in the active area of a stressed and an unstressed resistor. The subtraction of the stressed value from the reference one gives the gate stress impact on the resistors. To reduce

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KASBARI et al.: EMBEDDED STRESS SENSORS FOR STRAINED TECHNOLOGIES PROCESS CONTROL

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Obviously, this is not the effective value of the stress in the thin nitride film. The correlation between these two stress values are made through the coupled process-mechanical simulation. The standard stress level in the nitride stop etch layer can be estimated to 1080 20 MPa. This result is in good agreement with the usual values given in the bibliography [13] for such nitride thin films. VI. ASSESSMENT OF STRUCTURE AND PROCESS VARIABILITY A. Relevance of Test Structure Fig. 6. Half stressed resistor cross section. Comparison between SEM and simulation.

Fig. 7. Relative resistance variation according to the stress levels in the nitride film.

time calculation, only a half resistor was simulated. Fig. 6 is a comparison between a cross section of a stressed resistor obtained with the simulation and a physical analysis. This model permits us to study the effect of geometrical variations and stress variations in the gate structure. The finite element analysis shows that the main impact on the active area comes from the nitride layer. The impact of the gate geometry, the polysilicon line, and the spacer stress levels is very small in comparison to the effect of a nitride layer thickness or stress variation. We propose to detail here the simulation results of the nitride etch stop layer stress modification in a standard gate system. In a standard process flow simulation we modified the intrinsic biaxial stress value for a 900- -thick nitride film, all the other parameters were identical and different stress values were tested. Equation (4) allows calculating, in a biaxial hypothesis, the resistance variation according to the biaxial stress field modification in the active area. Fig. 7 is a plot of these values in relation to the different nitride film stress values. The relation between the film stress variation and the resistance variation is linear. The experimental results, presented in Sections IV and VI, are plotted here (triangle-shaped). According to this FEA model the stress variation in the active area is compressive and can be estimated to 7.5 MPa along the [110] direction and 26 MPa across the [110] direction. These values were calculated with the data of the experiment one (exp 1) and show that the sensor is sensitive to very small stress variations in the active area. The extracted stress value represents the perturbation of the resistors by the stress in the gate structure.

In a process control approach this test structure was integrated on the product wafer in an industrial production line. It permitted us to collect enough data for statistical analysis. To assess the relevance of the sensor, the results presented in the previous sections may be discussed regarding three key points. 1) First, the reference structure presents a median value close to zero, showing that the bridge is balanced, as expected. 2) Secondly, the shift of median value represents the average resistance deviation due to stress. This value is in good agreement with the known stress modification induced by the nitride film. 3) The third key point is that a prior full mapping design of experiment on process parameters should permit us to correlate the sensor response to process variations. It should permit us to build and to validate a range model for process critical parameters which influences the mechanical stress in nitride thin films. This is essential to develop a process control model and to define how wide to set the control limits. Therefore, we showed that only a strategic five points measurement can replace the full mapping measurement. For instance, the curves presented in Fig. 5 can be simplified to the graph presented in Fig. 8. The five measurements allow us to calculate the electrical median shifts and permit us to check promptly if the control limits are respected. This new test procedure saves a costly testing time. B. Within Wafer Variability Analysis The Ref structure shows, however, some variability. This variability represents the ultimate matching of the four resistors (lithography, contacts, and via resistivity). The active layer indeed undergoes a level of stress imposed by the STI oxide that might be responsible for this scattering [14], [15]. To evaluate the standard deviation of the resistors (1) can be written taking the resistor mismatches into account

(5) where terms represent the ultimate mismatch on each resistor the stress variation. (2,3 and 1,4 opposite diagonally) and Considering that the standard deviation of each resistor due to mismatch is the same for all the resistors, the standard deviation can be written as of

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(6)

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Fig. 8. Test sites on a product wafer. Five points measurement in comparison to a full mapping measurement (exp 1).

This formula allows calculating the standard deviations of the as a function of the measured standard resistors deviation of a reference bridge (sd ref_bridge). In the case of a is zero. Then reference structure,

This value is in good agreement with the known mismatch value from the technology Design Rule Manual. Generally, the Gate structure could show additional scattering compared to the Reference one. If we assume that this additional scattering is entirely due to the fluctuation of stress level in the gate structure, the standard deviation of effective stress at the resistor is then (7) Equation (7) permits us to evaluate the across wafer stress variation. In this technology set of data the standard deviation for the Ref and Gate Wheatstone bridges are identical, which is in agreement with the hypothesis of a uniform nitride film stress. We demonstrated in a different technology that the Wheatstone bridge configuration allows tracking very small resistance variation and giving the sensor very high electrical sensitivity [16]. We also showed that the mismatch scattering is the main limitation, preventing a true local stress characterization. To overcome this limitation, the mechanical coupling between the gate structure and the resistor should be increased by an upgraded layout of the structure.

Fig. 9. Shift variation observed between test structures on two wafers of the same product.

film was deposited. The position in the furnace was very different for these two wafers. In other words, the local temperature and the chemical species concentrations were different. According to [17], we assumed that the modification of these process conditions, especially the gaseous ratio between silane and ammonia, changes the stress state in the nitride film. These results show that the test structure we developed is efficient for tracking process-related nitride-stress shifts in a process control scheme. We also can mention the sensor sensitivity to other parameters like shallow trench isolation (STI) step height, gate size, and metallization stress levels [18]. For all these parameters, the useful information can be obtained through a simplified electrical test which opens the door to an automatic testing procedure and to a systematic data collection.

C. Wafer-to-Wafer Variability Analysis Data collection on two wafers (exp 1 and exp 2) produced along the same production line shows a variation of the median shift on the Gate bridges but no modification on the Ref bridges. The graph (Fig. 9) clearly shows this variation. Because the Ref bridges are not affected, one can assume that the shift of median value is induced by the gate structure, especially by a variation in the stress level of nitride film. In this hypothesis, the numerical model allows to estimate an increasing of 200 20 MPa in the film between the two experiments. The results are reported in Fig. 7. Because the sensor response modification has to be linked to a process variation, an analysis of the process history was performed. It shows that all the process parameters were identical for these wafers except the furnace conditions during the LPCVD process when the nitride

VII. CONCLUSION Mechanical stress is a major issue for up-to-date microelectronic technologies. We demonstrated embedded sensors aimed at gate integrity and nitride thin films stress monitoring in an APC scheme. Unlike other stress measurement techniques, they allow fast electrical stress monitoring without any additional process cost. We were able to track very small resistor variations and to extract easily the average nitride film induced stress level. Those extracted values are in good agreement with our coupled process-mechanical simulation and assess the relevance of this structure in an industrial environment. Finally, the test structure is ready for its integration in process control strategies and will be of special interest for strain engineered silicon technologies control.

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KASBARI et al.: EMBEDDED STRESS SENSORS FOR STRAINED TECHNOLOGIES PROCESS CONTROL

ACKNOWLEDGMENT The authors would like to thank P. Fornara for useful discussions on process integration matters and L. Charrier for test procedures and implementations. They also would like to thank V. Serradeil-Luton and J.-L. Liotard, STMicroelectronics Rousset team managers, for their help and interesting discussions. REFERENCES [1] S. M. Hu, “Stress-related problems in silicon technology,” J. Appl. Phys., vol. 70, no. 6, pp. R53–R80, 1991. [2] P. A. Flinn, D. S. Gardner, and W. D. Nix, “Analysis technology for VLSI fabrication,” IEEE Trans. Elec. Dev., vol. 34, no. 3, pp. 689–699, 1987. [3] C.-H. Chen, T. L. Lee, and T. H. Hou et al., “Stress memorization technique by selectively strained nitride capping for sub-65 nm high performance strained-Si device application,” in Proc. Symp. VLSI Technology, Honolulu, HI, Jun. 2004, pp. 56–57. [4] S. Ito, H. Namba, and K. Yamaguchi et al., “Mechanical stress effect of etch-stop Nitride and its impact on deep submicron transistor design,” in Proc. IEDM Tech. Dig. Electron Devices Meeting, 2000, pp. 247–250. [5] J. Moyne, J. Kim, M. Beachy, and T. Parikh, “Determining RTR control deployment strategies from process run data,” in Proc. 2nd Eur. Advanced Equipment Control/Advanced Process Control (AEC/APC) Conf., Dresden, Germany, 2001. [6] I. Noyan and J. Cohen, Residual Stresss. Stuttgart, Germany: Springer Verlag, 1987. [7] I. De Wolf, V. Senez, R. Balboni, A. Armigliato, S. Frabboni, A. Cedola, and S. Lagomarsino, “Techniques for mechanical strain analysis in sub-micrometer structures,” Microelectron. Eng., pp. 425–435, 2003. [8] J. C. Suhling and R. C. Jaeger, “Silicon piezoresistive stress sensors and their application in electronic packaging,” IEEE Sensors J., vol. 1, no. 1, Jun. 2001. [9] R. C. Jaeger et al., “CMOS stress sensors on (100) silicon,” IEEE J. Solid-State Circuits, vol. 35, 2000. [10] O. Slattery, D. O’Mahoney, E. Sheehan, and F. Waldron, “Sources of variation in piezoresistive stress sensor measurement,” IEEE Trans. Components Packaging Technologies, vol. 28, no. 1, pp. 1–5, Jan. 2004. [11] C. S. Smith, “Piezoresistance effect in germanium and silicon,” Phys. Rev., vol. 94, no. 1, pp. 42–49, 1954. [12] Y. Kanda, “A graphical representation of the piezoresistance coefficients in silicon,” IEE Trans. Electron Devices, vol. ED-29, no. 1, pp. 64–70, Jan. 1982. [13] C. Ortolland et al., Electrical Characterization and Mechanical Modeling of Process Induced Strain in 65 nm CMOS Technology 0-78038478-4, IEEE, 2004. [14] S. M. Hu, “Film-edge-induced stress in silicon substrates,” Appl. Phys. Lett., vol. 32, no. 1, pp. 5–7, 1978. [15] V. Moroz, N. Strecker, X. Xu, L. Smith, and I. Bork, “Modeling the impact of stress on silicon processes and devices,” Mater. Sci. Semiconductor Processing VI, pp. 27–36, 2003. [16] M. Kasbari, R. Delamare, S. Blayac, C. Rivero, and R. Fortunier, “Embedded “Mechanical stress sensors for advanced process control”,” in Proc. ASMC, 2007. [17] P. Temple-Boyer, C. Rossi, E. Saint-Etienne, and E. Scheid, “Residual stress in low pressure chemical vapor deposition SiNx films deposited from silane ans ammonia,” J. Vaccum Sci. Technology A, vol. 16, 1998. [18] R. Delamare, S. Blayac, M. Kasbari, K. Inal, and C. Rivero, “Mechanical stress sensors for copper damascene interconnects,” in Proc. MRS Spring Meeting, 2007.

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Romain Delamare Romain Delamare is in charge of the coordination of the Wallonia Infrastructure for NanoFABrication (WINFAB) at the Université Catholique de Louvain. His previous work has included the study of nano-clusters properties in silicon and the fabrication of devices for sensing applications. Currently, his main area of interest is in micro-electro-mechanical-system structures, including involvement in a variety of projects concerned with sensors design, co-integrated SOI-CMOS/MEMS process development, nano-patterning and nano-assembling.

Sylvain Blayac was born in 1972. He received the M.Sc. degree in electronics from the University of Montpellier, France, in 1997, and the Ph.D. degree in electronics in 2001. His doctoral research was led at France Telecom-CNET laboratory, Bagneux, France, on high-speed Indium Phosphide Heterojunction Bipolar Transistors technology. He then moved to Alcatel (Marcoussis) as a device physical and electrical Modelling Engineer for high-speed fiber-optic communication circuits. In 2003, he moved to the Provence Microelectronics Center-Ecole de Mines de St Etienne, Gardanne, France, where he became teacher in semiconductor devices physics and launched a research activity around embedded stress sensors. His main research interests are now around sensors and hybrid printed electronic devices modelling.

Christian Rivero was born in France in 1973. He received the M.S. degree in electronics and the Ph.D. degree in electronics, both from Marseille University in 2001, and 2005, respectively. His doctoral research was led at TECSEN laboratory on first part 2005, he then moved to CMPGC Scool of Gadanne, France, where he carried out research on Advanced Process Control, and worked to reduce process variations. In 2006, he joined ST Microelectronics company, Rousset, France, were he became on TCAD engineer performing process and device simulation. His main research interests include semiconductor device physics, and the relation between the mechanical stress and the electrical properties.

Roland Fortunier is a Professor at the Ecole des Mines, St. Etienne, France. After earning his Ph.D. degree, he acquired industrial experience in the steel industry working on manufacturing processes before joining academic research in material science and mechanical engineering. He is now head of the division for materials and structures sciences.

Moustafa Kasbari (S’05) received the M.S. degree in engineering physics from the University Denis-Diderot, Paris, France, in 2003. He is currently pursuing the Ph.D. degree in microelectronics at the Ecole des Mines, Gardanne, France. His main research interests are concentrated on the integration of stress monitoring in an Advanced Process Control strategy.

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