Microelectronics Journal ELSEVIER
Microelectronics Journal 29 (1998) 845-853
High-speed autozeroed CMOS comparator for multistep A/D conversion Francesco Brianti a, Alessandro Manstretta b'*, Guido Torelli b aSGS Thomson Microelectronics, 2055 Gateway Place, Suite 300, 95110 San Jose, CA, USA bDepartment of Electronics, University of Pavia, via Ferrata 1, 27100 Pavia, Italy Accepted 14 November 1997
Abstract A CMOS comparator suitable for multi-step flash analog-to-digital (A/D) converters is presented. It includes a moderate-gain preamplifier, a gain stage and a final set-reset flip-flop. Fast operation and high resolution are achieved using regenerative loads in the gain stage together with reset and autozero techniques in both amplifying stages. To minimize residual offset, the regenerative structure is reset while still kept in its unstable configuration. The comparator was integrated in conventional single-poly 1.2 t~m CMOS technology. Experimental evaluations showed a better than 1.5 mV resolution with less than 400/~V offset at a larger than 30 MHz comparison rate after the sampling/autozero phase. Power dissipation is as small as 0.8 mW (VDD= 5 V) in static conditions, and within 2.2 mW at maximum operating frequency. © 1998 Elsevier Science Ltd. All rights reserved. Keywords:
CMOS comparator; A/D conversion
1. Introduction Comparators are key elements in analog-to-digital (A/D) converters. The performance of the whole converter in terms of speed and re,;olution very often depends strongly on the characteristics of the comparators used. This is the case, for example, of flail flash and multi-step flash topologies, where high-speed high-accuracy comparators are generally required [1]. Where possible, CMOS technology is the preferred choice for implementation thanks to its ability to integrate digital and analog functions on the same chip at low cost. However, CMOS comparators display large offset voltages. Offset compensation is therefore needed to achieve high accuracy. The separation between compensated and non-compensated CMOS converters is typically around the 7-bit level using a standard 2 V full-scale input voltage [2,3]. This paper presents an autozeroed comparator designed for use in a multistep CMOS A/D converter, where the same comparator bank carries out a number of successive comparisons on any given input sample. A whole conversion cycle requires a single autozero phase, which also samples the input signal. This minimizes conversion time overhead due to offset compensation. High comparison speed is * Corresponding author. Tel: +39 382 505598; fax: +39 382 505677; e-mail: aleman@ ele.unipv.it,
[email protected] 0026-2692/98/$19.00 © 1998 Elsevier Science Ltd. All fights reserved PII S 0 0 2 6 - 2 6 9 2 ( 9 7 ) 0 0 1 2 3 - 7
ensured by a regenerative structure [4-9], which is preceded by a preamplifying stage. To reduce residual input-referred offset to a minimum even with the relaxed gain requirements of the preamplifier, the comparator is autozeroed at the same time as the regenerative structure is forced into its unstable configuration. The paper is organized as follows. Section 2 briefly introduces the multistep A/D conversion topology for which the comparator has been developed. The circuit diagram of the proposed comparator is then described in Section 3, and its operation is discussed in Section 4. Finally, Section 5 presents circuit implementation, along with the results obtained from experimental evaluation.
2. Multistep conversion topology Before describing the proposed comparator, in this section we briefly explain the multistep A/D conversion architecture for which it is intended. A multi-step A/D converter performs m successive n r b i t flash conversions (k = l - m ) to achieve a resolution of Nbits, where N = n l + n2 + ... + n m [10]. Here, we will refer to a three-step subranging approach (m = 3), where we also set n ~ nl = na = n3 ~ N / 3 (Fig. 1). A complete conversion cycle is divided into four steps, i.e. a sampling step plus three n-bit conversion steps. The input voltage Vin is sampled during the first step and is then held.
F. Briantiet al./MicroelectronicsJournal29 (1998)845-853
846
I
COARSE
/
I
INTERMEDIATE n-bit FLASH ADC
n-bit DAC
n
SYNCHRONIZATION
~
N=3n
OUT Fig. 1. Operation principle of a three-step subranging A/D converter. A first flash A/D conversion (coarse conversion) produces the n most significant bits (MSBs) during the second step. In the third step, these bits are converted into an analog value and are then subtracted from Vin. This difference is applied to an n-bit A/D converter to obtain the n intermediate bits (ISBs). In the last step, the n least significant bits (LSBs) are determined following the same approach. A digital network
Vin
o
VrefC,i o
l eo1 f.--
Vrefl,i o
~2 /.--
VrefF,i o
provides the synchronization required to obtain the N-bit digital output word. The same voltage references are used to perform both the A/D and the D/A comparison referred to the same group of bits. Moreover, the same bank of comparators is successively used in each A/D comparison step of a complete conversion cycle. This ensures silicon area saving and reduced power consumption, making this
~0 J C1 OUT .
q~3
o
_L a)
~0
~1
~2
~3
t
b) Fig. 2. (a) Elementary ith cell of the mulfistep A/D converter. Cp1 represents the comparator input parasitic capacitance. (b) Nonoverlappingclock phases ~o-~3.
847
F. Brianti et al./Microelectronics Journal 29 (1998) 845-853 ~)STR
,Az,_~
o_.ooc,, _
*:__L_
t t
..t 1
,,_
crl
\
\
I
RES Q p OUT SRFF/ SET
~ [ [ - - O OUT
OAZ2
OAZl
a) J--I / I 5]
rl
J
11
]
rl
F1 II
I-I
(I)Az1 SAMPLING & AUTOZERO 1ST STAGE OAZ2 AUTOZERO 2ND STAGE
I-L_
(I)R1 RESET 1ST STAGE
I l--
fl
(I}R2 RESET & PRESET 2ND STAGE (DSTR STROBE
fl
ba,bT,b6 bs,b4,b3 b2,bl,bo 1 2
3
4
5 6
7
8
9 10 11 12
EUqEWYZU~UqYW~
MASTER CK START
F
"1
TM
"1
TM
"1
q
TM
b) Fig. 3. (a) Block diagram of the proposed comparator. (b) Timing diagram referred to three-step conversion.
approach very attractive when maximum conversion speeds are not necessary. The elementary ith conversion cell of our A/D converter is shown in Fig. 2. To achieve n-bit resolution at each conversion step, (2 n - 1) identical elementary cells are used simultaneously. Input capacitive coupling allows autoeroed operation of the comparator [11,12] and, therefore, offset compensation. During the first step of a conversion cycle (phase ~0) the capacitor C1 of each cell samples the input signal Vin together with the comparator offset. Each of the following m = 3 steps (~1-~3) performs an n-bit flash A/D conversion starting from the MSBs, as explained above, using charge balance techniques [12-14]. To this end, suitable coarse, intermediate and fine reference voltages VreeC,i, Vrefi,i , VrefF,i are successively applied to C1 at each step, where Vr~fl,i and Vr~,i are based on D/A conversion of the digital codes obtained from the previous steps. Our target for the comparator is high accuracy together with maximum comparison speed. To obtain a 9-bit converter (n = 3) with 2 V input range, we need a comparator
resolution better than 2 mV. It should be noted that input capacitive coupling introduces an attenuation Oil -- C1/ (C1 + Cp1), which adversely affects the comparator sensitivity (here, CpI is the total parasitic capacitance at the comparator input). Moreover, the operation speed of each conversion step must be higher than the overall speed required of the A/D converter by a suitable factor, which obviously depends on m. Very fast recovery from overdrive conditions is also required as each comparator is successively used in all conversion steps.
3. Circuit description The block diagram of the comparator is shown in Fig. 3 together with the command signals required for its operation in the above 9-bit three-step subranging A/D converter. In the A/D converter, the command signals are generated starting from an external master clock, CK. Moreover, a complete conversion cycle is started by the START pulse. The
848
F. Brianti et al./Microelectronics Journal 29 (1998) 845-853
%o
liP1
MP1'~._~
MP3~L~MP3' E ~R~ F SR2
A¢'~) Vin o--- ,~..~
~4,.~~$ NOR' TYPEr Q SRFF }--o"Q
__;l~~~_.qc~_C1 Sl 0303' Sl
S2dPAZ2F 04
04'
I ~AZ2
Vref°'--~---~ j Fig. 4. Circuit diagramof the proposed comparator. fully differential topology reduces charge injection effects and noise injection from uncorrelated signals. The comparator consists of a preamplifying stage (A 1), a gain stage (A2) and a set-reset flip-flop (SRFF). The preamplifier provides the extra gain needed to achieve the desired resolution despite the input signal capacitive attenuation due to parasitic capacitors in the comparison phases and residual offset in the gain stage. Moderate gain is sufficient for this purpose, while low output voltage swing is required to allow fast overdrive recovery in the reset phase and to minimize kickback noise effects [3] during the comparison phases. The second stage A 2 provides the high gain required through regenerative action, as explained below. The two stages A1 and A2 are provided with reset and autozero functions (signals ~}R1, (]}R2 and ~IaAZ1,~I~AZ2,respectively). Reset of both stages is carried out at the beginning of the autozero phase and before any comparison step to ensure fast overdrive recovery. In the A/D converter, reset is performed during the time required to settle the new voltage applied to the input capacitor at the beginning of each operating step. Therefore there is no appreciable delay overhead. It should be pointed out that the first stage must be reset without short circuiting its inputs, as in our conversion topology the sampled signal must be maintained on C1 during a whole conversion cycle. The detailed circuit diagram of the comparator is shown in Fig. 4, where for simplicity the reference voltage applied to the comparator input in each conversion step is referred to as Vref. The preamplifier is implemented with a differential stage. The load of this stage is made up of diode-connected MOS transistors, which provide the required amount of gain while avoiding the need for a common-mode feedback network and, hence, preventing the consequent operating speed degradation and area occupation. The use of a modest load impedance ensures fast overdrive recovery of the common-mode output voltage during reset and allows the charge injected when opening the reset switch to be quickly recovered. Obviously, the adopted choice leads to a limited
suppression in the residual offset of the second stage as seen at the comparator input. However, this drawback is overcome by suitably autozeroing the second stage, as shown in the next section. Two series load transistors (Mm, Mr,2 and Mp~,, Mp2,) are used in each branch to limit the maximum output voltage swing. Input capacitive attenuation is limited by small crosscoupled capacitors C3 and C3,, which reduce the Miller effect due to the gate-to-drain capacitance of the input transistors. The second stage includes an n-channel differential pair with a p-channel regenerative load (Mp3, Mpy) [7]. ~Ra acts as a preset command for this stage at each conversion step (~1-4}3). During the time interval when ~R2 = 1 and ~R1 = 0 (preset phase), a voltage depending on the input signal difference Vin -- Vrefis forced across the differential output of A2 (nodes E and F). This voltage acts as an initial imbalance for fast signal regeneration when S ~ is turned off (comparison phase). Regeneration speed is increased by enabling an additional n-channel latch MN3, MNy after a given delay time (~STR = 1). C4 and Ca, play the same role as C3 and Cy, limiting the input capacitive attenuation of this stage. At the end of each comparison step, the strobe signal cbSXR allows the comparison result to be latched in the final SRFF, which also ensures rail-to-rail output levels. Both set and reset commands of this flip-flop (signals SET and RES) are forced to a low level during the quiescent period of the flipflop (~STR = 0), and therefore a NOR-type SRFF (Fig. 5) was used to provide a valid output during this period.
4. Circuit operation We now describe the operation of the proposed comparator by referring to its operating phases.
4.1. Reset phase Reset is obtained by closing both reset switches SR~ and SRZ (~R1 = ~ = 1). This provides fast overdrive
F. Brianti et al./Microelectronics Journal 29 (1998) 845-853
D, assumed to be substantially constant during this interval (VcD = Otl0/2Al(Vin - Vref) , being 0/2 = C2/(C 2 -~-Cp2) the capacitive attenuation at the input of the second stage), VEF(0) is the value of V~F at the beginning of the preset phase, gR2 is the drain-to-source conductance of SR2, gmi is the transconductance of transistor Mi and
VDD
SET c
CL2
(3)
rpr -- 2gR2 _ gmP3 GND
RES o
Fig. 5. NOR-based set-reset flip-flop (SRFF).
recovery in both gain stages at the beginning of any operating step ~0 to CI~3. As shown in Fig. 3(b), reset is not needed at the beginning of step • 1, as the structure has not yet carried out any comparison after the reset/autozero phase.
The input analog signal is sampled on capacitor C1 during the first step of each conversion cycle (ffAZl = 1, ~R~ = 0). The offset voltage of the input stage is also sampled on C~, thereby providing autozero of the first stage. The second stage is autozeroed by setting ffAZ2 to a high level. It is worth pointing out that this stage is autozeroed while it is kept in its preset configuration (~R2 = 1), as will be highlighted below.
4.3. Preset phase We turn now our attention to the comparison steps (CI~I--~3). During each of these steps, the required reference voltage Vref is applied to the comparator input. After the initial reset, SR~ is open. When transients are over, the output voltage of the first stage VAB ~- VA -- VB becomes equal to VAB -~- 0 / l A l ( V i n - Vref), where
(11)
(1)
gmr~
where CL2 is the capacitive load at the outputs of the second stage. To prevent regeneration due to the cross-coupledp-channel pair (Mp3, MFy) during this phase, we set 2gR2,o n ~" gmP3. Thus, the exponential term in Eq. (2) goes to zero with a time constant equal to rpr, regardless of its initial value. If CI'R2is sufficiently long with respect to rpr, at the end of this phase (t = to) the voltage VEF becomes gmN2
VEF(t0 ) ~-- V c D
2gRz -- gmP3
is the open-loop gain of the first stage. After SR1 opens, SRz is kept closed for a given time interval (~R1 = 0, ~ 2 = 1). Meanwhile, the n-channel latch (MN3, MN3') is disabled (~STR = 0). Under these conditions, it is easy to obtain that the voltage across nodes E and F, VEF , as a function of time will result equal to
VEF(t0 ) = 0/10/2al(Vin _ Vref ) ,, gmN2 ZgR2 -- gmP3
= 0/lazA1azpro(Vin - Vref)
+
(
(5)
where (6)
gmN2 A2pr° - - 2gR2 -- gmP3
is the gain of the second stage in this state. The gain of the whole comparator in the preset state is obviously equal to: VEF(t0) Apr0 = Vi n _ Vref = 0/1 °t2AlA2prO
(7)
During reset and preset phases, as well as during the sampiing and autozero phase, both inputs of the SRFF (nodes SET and RES) are forced to a low level, and therefore its outputs are kept unchanged.
4.4. Comparison phase In this phase, the comparator produces the digital signal representing the result of the comparison between Vin and Vr~f. When SR2 opens (OR2 = 0), gR2 approaches zero, and the p-channel latch leaves its unstable configuration starting a regenerative action: VEF(t) = -- VCD gmN2 q_
VEF(t) ~ VC D
(4)
VEF(t0) therefore shows a linear dependence on the input difference (Vin - Vr~f):
4.2. Input sampling and autozero phase
A1 = ~ gmNl" gmP1
849
gmP3
gmN2 2gR2 -- gin:?3
VEF(t0 ) _4_ gmN2v~ x~(t-to)/rreg gmP3 C D ) ~
(8) gmN2
"VcD)e-t/rp~
VEF(0) 2gR2-- gmP3
(2)
where rr~g =
In the above equation Vco is the voltage across nodes C and
CL2
gmP3
(9)
850
F. Brianti et al./Microelectronics Journal 29 (1998) 845-853
After a suitable delay time, the strobe command OSTR is driven to a high level. This enables the n-channel latch, increasing regeneration speed. The offset of the n-channel latch does not substantially affect circuit operation, since it is enabled when an appreciable signal has already developed across nodes E and F. In practice, all nonideal contributions due to mismatches in this structure are further divided by the voltage gain obtained in the first part of the regeneration (¢g2 = 0, esTg = 0), and will be neglected in the following. The output signals of the second stage are applied to the inputs of the final SRFF, which switches accordingly providing fully digital output levels.
4.5. Offset minimization From Eq. (4), the voltage across nodes E and F at the end of the preset phase, VEF(t0), acts as the initial imbalance for the latch in the regeneration phase. The minimum detectable input signal Vin - Vref, as well as the switching speed, depend critically on its value. A sufficiently high preset gain Ap~0 must therefore be provided. Moreover, the accuracy of VEF(t0) is affected by contributions due to nonideal effects such as hysteresis, offset and charge injection. As shown above, hysteresis is prevented by resetting both amplifying stages before any comparison operation. Moreover, both stages are autozeroed at the beginning of each conversion cycle for offset compensation. Importantly, since only a single autozero operation is required for a complete conversion cycle in a multistep A/D converter (m comparison steps), the time overhead required for sampling and offset compensation is limited. The falling edge of eAZ2 is delayed with respect to eAZl [11]. The residual contributions coming from the offset of the first stage and the charge injection caused by the opening of its autozero switches are sampled on the interstage capacitors C2, and are therefore perfectly compensated so long as the autozero time constant of the second stage is adequately small. Mismatches in the charge injected into nodes A and B at the end of reset phases are quickly recovered through the modest load impedance (Mpl, Mp2 and Mpl,, Mp2'). Since moderate gain is provided by the preamplifier, as pointed out in Section 3, offset contributions of the second stage must be considered. To obtain the best accuracy, we must minimize the equivalent offset at the beginning of the regeneration phase. To this end, we provide autozero of the second stage while keeping it in its preset configuration (S Re on). Thus, the effective offset seen at its input (nodes C and D) when the regeneration process begins is
VosN2-~- VosP3(gmPa]gmN2) V°s2pr = A2pr0 + 1
Offset contributions deriving from the charge injected when opening $2, $2, and SR2 are minimized by the fully differential topology used. However, charge injection mismatches produce an equivalent offset. The main contribution comes from the charge injected into nodes C and D when opening autozero switches $2 and $2,. This gives an offset at the second stage input equal to
AQins2 Qs2 ACc Cc + Cc Cc
Vos2~nj
Qs2 f AQins2 ACc'~ Cc "\ Qins2 +'-~C/t" (11)
where Qins2 is the charge injected by $2 ($2,) into node D (C), Cc is the total capacitance at node C (D), and AQins2 and ACe are the mismatches between these parameters in the two differential branches. To minimize Qins2, dummy transistors were added to autozero switches. Offset contributions due to the charge injected into nodes E and F at the end of the autozero and preset phases can be neglected, as they are divided by factor gmNz/gmP3when referred to the input. Moreover, in our design we kept SR2 very small, thereby minimizing its charge injection. The equivalent offset referred at the input of the whole comparator results equal to
Vospr--
Voszpr+ Voszinj oq o~2A1
(12)
5. Circuit implementation and experimental results The described comparator was designed for a conventional 5 V single-poly implanted-capacitor 1.2/~m CMOS technology. Circuit design was optimized to obtain the best accuracy while still providing high comparison speed. For maximum speed, channel length was kept to a minimum for all transistors, except current sources MB1 and MB2. Cl and C2 were set at 0.1 pF. This was the best trade-off between autozero speed on the one hand, while maintaining acceptable capacitive attenuation factors c¢1, tx2 and ensuring adequate matching between the differential
Vrefl
AVI
Vin .
.
.
.
.
.
.
.
.
.
I ~'AVa Vref3
.
.
.
.
.
.
.
.
.
(10)
Vref2 where VosN2and VosP3are the offset voltages of the n-channel differential pair and the p-channel latch, respectively. VosN2 is minimized by a using a large value of Wry2and an interdigitized layout. This also results in a large value for gmN2, which reduces the term VosP3(gmP3/gmN2).
I"
"F
T
"1"
-I
Fig. 6. Inputwaveformfor inputsensitivityand overdriverecoveryevaluations. AVl = Vr~n- V i n ; A V 2 = Vref2 - V i n ; A V 3 = Vref3 - Vin.
851
F. Brianti et al./Microelectronics Journal 29 (1998) 845-853
Table 1 Component sizes (transistor width in #m) 1st stage
,,,,___/3 >
/3
(v)
~ 4i-
("i)~'l"
1~
~
i:
'
""
2nd stage
MN1 Mp1 Mpz Sl SRI
30 6 6 5 10
C1 C3
0.1 pF 10 fF
MN2
Mp3 $2 S R2 MN3 MN4 C2 Ca
SRFF 72 7 5 3.5 10 3 0.1 pF 24 fF
MN5 MN6 Mp4 Mp5
15 10 5 10
,,,I,,, I .... (vii)
0
>0
o
lo
20 30 40 50 60 70 80 time (ns)
Fig. 7. Simulated waveforms (VosP3 = 40 mV). Via = 100 mV; AVI ~ 1 V; £~V2= - 700 #V; AV3 = + 700 #V. (i) START; (ii) CI'srR;(iii) VE; (iv) VF; (v) Q; (vi) Q; (vii) Vin, Vref(cbAZa and ~Sa'R amplitudes not to scale).
branches on the other. The width of MN1 was chosen to ensure enough transconductance, and hence enough speed, at the first stage while; still keeping input parasitic capacitance reasonably small. The p-channel loads were sized to obtain A1 = 19 dB. SI, S r and SR1 a r e n-channel switches. Their sizes minimize parasitic effects such as stray capacitance and charge injection without heavily degrading speed performance. As explained in the previous section, a large value of WN2 was used to maximize the preset gain of the comparator and reduce its input-refen'ed offset. The transistors of the pchannel latch were sized to minimize input-referred offset, while still providing enough speed. In practice, we set grnp3] gmN2 ~-" 0.18. Moderate sizes were used in the n-channel latch to limit charge sharing between nodes E, F and G, H when the strobe command is driven to a high level. S 2, S 2' and SR2 are p-channel switches. SR2 was sized for the best trade-off between preset gain and speed to maximize the
imbalance VEF(t0) at the end of the preset phase. Its conductance gR2 was kept nominally equal to gmP3, to provide an adequate margin against any risk of regenerative feedback during preset. Minimization of charge injection was also a target when sizing switches SR2, $2, $2'. The logic threshold in the final SRFF was kept low ( - 1 . 7 V) to ensure fast switching even in the presence of non-negligible charge sharing at the output nodes of the second stage at the beginning of the strobe phase. Bias currents in the first and second stage were set at 60/~A and 100/~A, respectively, to achieve the required speed while keeping power consumption low. A summary of the component sizes used is shown in Table 1. With these choices, we obtained al = 0.58, c~2 = 0.42 and Azp~0 = 17 dB, which gives Apr 0 = 24 dB. Residual inputreferred offset remains smaller than 0.5 mV assuming typical process mismatches between the differential branches. To evaluate the comparator under worst-case dynamic conditions, the input signal shown in Fig. 6 was used. After sampling the input voltage Vin, a large input overdrive Vrefl -- Via = A V 1 was generated, which was followed by small differences VrefZ- Via ~ AV2 and Vref3 -- Vin = AV3 applied during the comparison steps tI~2 and cb3. Simulations at VDD = 5 V (Fig. 7) showed that a better than 1 mV resolution is achieved even after large overdrive at a comparison rate of 50 MHz after autozero. In these simulations, we assumed a p-channel latch offset Vo~p3as large as 40 mV. To show the output switching due to the first comparison
Fig. 8. Microphotograph of the integrated comparator.
852
F. Brianti et al./Microelectronics Journal 29 (1998) 845-853
TeK~
10 Acqs
500MS/s
Vin~
A: 1.2mV
Vref
@: - 5 6 9 . 0 m V
CK
1
START
2
Cl Freq 96.29214MHz Low resolution C2 Freq 7.999296MHz Low signal amplitude
Q 3-* Chl Ch3
5 . 0 0 V ~ Ch2 ~i.'o'ov' k~ M2b.Ons' 2.00 V ~ E 20.OmV%"w
=Cfi:~'.f
. . . . 2.'3'~/
(a) T@K ~
500MS/s
10 Acqs ........................... t] ................... -T-- ..................................................
A : 1.2mV @: - 5 6 9 . 0 m V
Vin, Vref
CK C1 Freq 96.29214MHz Low resolution
START +
.....................
ii ......................
. . . . . . . . . . . . . . . . . . . . . . .
-i . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C2 Freq 7.999296MHZ Low signal amplitude
Q Ch3
2.00V
~ E
20.0mV%~
(b) Fig. 9. Waveforms measured for input sensitivity and overdrive recovery tests (Vi, = 100 mV). (a) Output switching for AV2 = -- 1.2 mV after A V 1 ~ Jr- i V ; (b) output nonswitching for AV2 = + 1.2 mV after AV1 ~ + 1 V. Tracks: 1, Master CK (5 V div-1); 2, START (5 V div-1); 3, output Q (2 V div-l); 4, Vi,,, Vref(20 mV div-1).
result, the final s e t - r e s e t flip-flop was initially set to the state Q = 1. The comparator was integrated in a test chip (Fig. 8). Guard rings were also provided around the structure to m i n i m i z e noise injection from/into the surrounding circuitry.
The geometrical shape of the comparator, chosen to fit the pitch of the three-step A/D converter, leads to some penalty in area occupation (0.023 mm2). Fig. 9 shows the waveforms m e a s u r e d for a typical chip (VDD = 5 V). In all cases, Vref3 was set equal to Vren, to allow
F. Brianti et al./Microelectronics Journal 29 (1998) 845-853
an easy display of the comparator output waveform on the oscilloscope. Evaluation was performed using both input sequences where AV2 and AVt have an opposite polarity (output switching test) and input sequences where AV2 and AV~ have the same polarity (output non-switching test). To better appreciate small voltage differences, the input signal (Vin, Vref) is plotted with a magnified scale (20 mV div-1), and therefore only the negative peak values of this signal are visible in the graphs. Dashed/plain horizontal lines visible on the plots are referred to the meter of the applied AV2. These plots show that very good sensitivity (1.2 mV) is achieved even after large overdrive ( ~ 1 V) and no appreciable residual offset is present. Measurements on all samples analyzed showed a better than 1.5 mV sensitivity at a comparison rate; of 33 MHz after autozero and offset was negligible (smaller than 400/zV). Moreover, as expected, no appreciable offset dependence from input voltage was observed. Measured power consumption was 0.8 mW in static conditions (VDD = 5 V). It remained below 2.2 mW at the maximum comparison rate.
6. Conclusions An autozeroed CMOS comparator has been described. It features fast operation and high sensitivity thanks to the use of a preamplifier and a regenerative gain stage. Both autozero and reset techniques are used. Particular care was devoted to minimizing input-referred offset. This was obtained by keeping the regenerative structure in its unstable configuration during the autozero phase and optimizing component sizes. This approach allowed us to greatly relax the gain requirements of the preamplifying stage. Experimental evaluation showed the effectiveness of the topology proposed. The comparator described was optimized for a multi-step A/D converter. However, it lends itself for use in a full flash A/D conversion architecture, even though it is at the cost of a greater time overhead for the sampling and autozero phase.
853
Acknowledgement The authors wish to thank R. Scotti for his help with the design and experimental evaluation.
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