LOW-POWER DESIGN OF A MULTI-MODE TRANSCEIVER* D. Soudris1, M. Perakis2, X. Mizas1, V. Mardiris1, K. Katis3, C. Dre3, A.E. Tzimas4, E.G. Metaxakis4, G. Kalivas4 N. Zervas 5, S. Theoharis5, G. Theodoridis5, A. Thanailakis1, and C. Goutis1 1 VLSI Design and Testing Center, Dept. of Elec. & Comp. Eng., Democritus University of Thrace, 67100 Xanthi, Greece,
[email protected] 2 Dept. of Comp. Eng. and Informatics, University of Patras, 26110, Greece 3 INTRACOM S.A., 19,5 km Markopoulou Ave., 190 02, Peania, Greece 4 Applied Electronics Lab, Dept. of Elec. & Comp. Eng., University of Patras, 26110, Greece 5 VLSI Design Lab, Dept. of Elec. & Comp. Eng., University of Patras, 26110, Greece
Output Streams
FPGA 1 LPGD readIn
GMSK Digital Modulator
inData gsmDect
10
phi 8x1152kHz
b_clk
13.824MHz
EMI_clk
27.648MHz
bsclk r_en rec_data dpllsynchom slotsynchom
SELECT
WRITE
Data_Clock
*
CLOCK
Clock 4x1152kHz
Start_Detection Symbol
DECT Detector Receiver
preamble_detected
AD9761
2
Clock generator block
CLOCK
slot_detected SELECT
aux_fso_out aux_do
6
aux_fsin aux_fso_din
AD9281
6
I/F
FIR 8
8
Select FIR
6
Start_Detection
6
8
8
IQ 8bits
8
8
2. The Architecture of GSM/DECT Modulator/ Demodulator Figure 1 depicts the main building blocks of the implemented GSM/DECT Modulator/Demodulator as well as the interface links or signals with ASPIS processor [1,7], the chosen Analogto-Digital and Digital-to-Analog Converters, and Automatic Gain Control (AGC) & DC Offset. The main characteristics of each building block of GMSK/GFSK modulator/demodulator will be given in the next paragraphs. The system description will begin with the uplink path and through downlink path, will end up with the detailed implementation of FIR filters.
IQ 10bits
10
ASPIS Processor
aux_clk
1. Introduction In today’s portable communication systems the demand to integrate more and more services in one handheld unit creates the pressing need for dual mode low dissipation portable terminals. The purpose of this paper is to describe the main characteristics of the implemented GFSK/GMSK modulator/demodulator as well as the interface with ASPIS processor [1] and A/D & D/A converters. The main building blocks of the designed module are: i) the GSM/DECT modulator, based on a look- up- table principle which creates the GMSK waveforms, ii) the DECT demodulator, which is based in a zero -IF architecture and iii) the digital FIR filters. More specifically, the specifications and the detailed architecture implementation of the modulator and demodulator as a separate component, have been reported in [3,4,5]. However, the detailed description of the interface signals with ASPIS processor and chosen converters is not given. Here, the FIR design is also described in detailed manner. Concerning the block FIR&Select, we provide its detail functional description and the associated architecture implementation. The whole system has been implemented in VHDL [6].
MUX
t_en do H_mode
synReset
DEMUX
Abstract: Recent advances in electronic technology and integration coupled with increasing needs for more services in portable communications favors the development of high performance dual- mode terminals. Here, we present the complete architecture implementation of the GMSK/GFSK modulator/demodulator including the FIR filters design. The main features of the modulator/demodulator and the architectural implementation of FIR filters are described. The interface with ASPIS processor [1] and A/D & D/A converters is also described in detail manner. The whole architecture of the modulator/demodulator was described by VHDL hardware language, synthesised and implemented in Xilinx environment.
Clock 4x1152kHz
Aux Clock
Input Streams
FPGA 2
I/F
CS
AGC & DC offset block I/F
SCLK
MAX549A
OUT I
DIN b_clk 13.824MHz
OUT Q
Figure 1. FPGA Interface 2.1 GMSK Digital Modulator The architecture of the digital GMSK modulator designed to satisfy both GSM and DECT standards is shown in Figure 2. The modulator receives data from ASPIS processor and produces two output streams, I and Q, which are eventually the input of D/A converter. The input stream of GMSK Modulator, , comes from ASPIS processor, while the outcome of modulator is two GMSK modulated digital streams Iout and Qout of 10 bits. The input data of inData appear after (N+1/2)×Tb time units, where Tb is the period of Data_Clock and N integer ranging between 0 and 511. The inData are read either with falling edges of Data_clock or before the use of phi clock 8x1152kb/s (Fig. 1). It can be stressed that the time point where the data of inData will be read is not so critical (i.e. enable of read In). The signal SynReset is activated during a falling-edge of Data_Clock. The rate of inData stream is equal to the rate GSM/DECT standard. Regarding with GSM and DECT, an interpolation factor 16 (=4.33MHz) and 8 (=9.2MHz) is used, respectively. Then, using a suitable multiplexer, the multiplexed data are feed to a Digital-to-Analog converter (DAC). The demonstrator board uses the DAC AD9761 of Analog Devices. This particular DAC has one parallel port of 10 bits, which read the multiplexed data of I & Q every rising edge of clock. The value of SELECT determines whether the current input value belongs to I or Q output streams. During the idle state the signals CLOCK/WRITE are LOW.
This work was supported by European Commission and INTRACOM under the project No. 25256 LPGD ESPRIT.
F2 F2
F1
DAC w Binary data
Address Generator L
GMSK LUT
LPF
I
LPF
Q
F2
DAC w
Figure 2. The architecture of GMSK Modulator. 2.2 DECT Receiver The complete design of the implemented DECT receiver, shown in Fig. 3, consists of four blocks: • The Phase Difference Decoder Block (PDD) • The Automatic Frequency Correction Block (AFC) • The Phase Difference Transition Mapper Block (PDTM) • The Symbol Timing Estimation Block (STE) The circuit accepts at its input a quantized IQ stream consisting of a pair (I, Q) of 6-bit vectors in size-magnitude form received on each clock cycle. The processing of the above stream by the five blocks presented above yields the bit stream of the data section contained in a DECT slot. More specifically, the differential detector uses the symbol rate sampled streams of the in-phase, I, and quadrature-phase, Q, components of the received baseband GMSK signal and calculates the phase difference between the two sampling instants. The AFC system operates using one sample per symbol period and estimates the phase rotation between two successive symbols, and produces a phase error estimate that corrects the phase difference.The phase difference, after being corrected by the AFC block, is fed to the Phase Difference Transition Mapper (PDTM). This block, depending on the phase difference, will produce a 01, 10 or 00, which in turn, with the help of a simple FSM, will extract the estimated data. Finally, the functions of slot synchronization and symbol timing estimation block of the proposed receiver use the same basic principles. As a result, these functions are implemented by the same functional block and occur simultaneously, thus resulting in a joint slot Synchronization and symbol timing estimation. The detailed functional description of DECT detector were presented in [8]. In order to design efficiently the DECT receiver in terms of power consumption, we used existing low power techniques and developed two new power optimization techniques, namely the behavioural power management and the dynamic frequency reduction. These techniques can be applied on a large class of wireless communications algorithms. The power management discipline implies that when the output of a component becomes unobservable then this component can be shutdown [9]. The technique applied here is based on the fact that unobservability can be introduced for a behavioural cluster after the occurrence of an event. For example the outputs of a behavioural cluster responsible for the computation of a series become unobservable once the series converges. The same situations can be met in a behavioural cluster responsible for synchronization after the synchronization is achieved. The application of this technique achieves 31% power reduction for the DECT receiver circuit with respect to the power consumption of the DECT receiver circuit with no power management features. Detail description of this technique can be found in [10]. The second technique reduces the frequency operation depending on the input data streams. More specifically, adaptive sampling through oversampling imposes that the
whole receiving algorithm is computed on N input data streams, each one of which corresponds to a different sampling instance during the symbol period, while only one stream corresponds to the correct sampling instance. This introduces a significant power overhead. For this purpose a novel frequency reduction technique is introduced. Specifically, the operation frequency can be reduced to the symbol frequency after the synchronization pattern detection and up to the end of the frame. During this time interval, the receiver is forced to operate only on the input stream that corresponds to the correct sampling instance. After the end of each frame the receiver operates again at the oversampling frequency. For the design of the DECT receiver design, the application of dynamic frequency reduction lead to 65% power reduction, with an area overhead of 1,02%. Table 1 gives the area estimation, the number of equivalent gates and the power dissipation of each block separately as well as the total power consumption of DECT receiver.
CLOCK CONTROL
2
DECT RECEIVER
SYMBOL TIMING ESTIMATION
6 Bits 6 Bits
PHASE DIFFERENCE DETECTOR
8
AUTOMATIC FREQUENCY CORRECTION
8
PHASE TRANSITION MAPPER
Figure 3. The Architecture of DECT receiver. DECT Block
Area (mm^2)
# equivalent gates
Power dissipation (mW/MHz) 4.647729 1.826258 0.884459 0.019646 0.02 0,72 (*)
AFC 1.735 2670 PDD 0.758 1296 STE 0.733 783 PTM 0.001 20 CC 0.023 262 Total 3,477 (+) 5031 (+) 0.7 ìm technology (*) PTOTAL , AVERAGE = 1/90*PPDD + 1/360*(PAFC+ PPTM +PSTE) + PCC PCC=Clock Control
Table 1. Area and Power measurements of DECT receiver. 3. FIR Filter of DECT receiver 3.1 FIR Filter Description Filtering in most digital communication systems is accomplished by a combination of analog and digital lowpass filters. Digital lowpass filters are designed as Finite Impulse Response (FIR) filters. In this way there is more flexibility in the design and on the other hand it is a lot easier to obtain some very desirable characteristics like phase linearity and high accuracy in the response. Usually some windowing methods are used to derive the coefficients of the impulse response of the FIR filter. It should be stressed here that during the design of FIR filters the features of the analog filters of the uplink and downlink path were taken into account [3]. Particularly, the receiver part uses 4th order Butterworth antialiasing analog filter, with fc=0.8*R. After extensive
demux
demux_in(7:0)
rst in_i(7:0)
gclk
fir_circuit_i
fir_i(7:0)
gated_clk
clk4, rst
clk4, rst
clk4, clk8, rst
gclk gated_clk
fir_circuit_q
oagc_i(7:0) oagc_q(7:0) detector_in_select (1:0)
select_select agc_i(5:0)
DECT Detector
8
Detector_ in_select
FIR
8
FIR
8
Select 2 8
6
6
8
i(5:0)
6
IQ 8bits (Sign Magnitude)
TRANS
{
q(5:0)
agc_q(5:0)
DEMUX
6
{
To AGC
v.
From AGC
iv.
trans
In order to accomplish the design of the circuit a top-down hierarchical methodology and VHDL have chosen. More specifically, the top-level design uses structural VHDL, while the low-level blocks in behavioural VHDL. The DECT receiver design requires digital low pass filters [3], a FIR filter per input stream. A number of simple circuits between the DECT Detector and FIRs, ADC and FIRs, and, AGC and FIRs, are needed to perform accurate filtering. The corresponding block diagram is shown in Fig. 4, while the detailed architecture implementation in Fig. 5. For simplicity reasons, we named the whole system as FIR&SELECT block, which consists of: i) one demultiplexer (named DEMUX), ii) a conversion block from straight binary to signmagnitude (named TRANS), iii) two FIR filters, and iv) the SELECT block. The detailed features and implementation of each aforementioned block are given in the next paragraphs: DEMUX As it can be seen in Fig. 1, the I and Q signals coming from the ADC AD9281 are multiplexed. Thus, a block named DEMUX is used to demultiplex these signals. The input and output signals of DEMUX block are shown in Fig. 5.
fir_q(7:0)
iii.
3.2 FIR Filter & Select block Implementation
in_q(7:0)
ii.
Inputs from ADC data_in(7:0)
shift-add operation, which results into less switching activity [12]. Operation reduction. Exploiting the filter coefficients symmetry, i.e. identical filter coefficients, we performed seven(7) shift-add operations instead of the initial thirteen (13) operations. Use of sign-magnitude arithmetic. It has been proved [12] that this type of data representation results into smaller switching activity comparing with conventional arithmetic systems, e.g. binary, 2’s complement. Hardware redundancy. The number of the used hardware elements was directly depend on the number of filter coefficients. Employing the maximum inherent parallelism of FIR, the frequency operation is identical with clock frequency 4×1,152 MHz. The hardware redundancy allows continuous pipeline of data slots from ADC. Use of gated clock
rst
simulations we have reached the conclusion that a 13 taps FIR filters with interpolation factor 4 and cut-off frequency approximately 0.6*R(691xMHz) yields satisfactory performance (BER results vs. SNR or Eb/N0). In addition, they meet the specifications of the DECT standard. Finally, it should be mentioned that a Kaiser window with beta=3.5 has been used.
IQ 8bits (Straight Binary)
8
AGC & DC offset block
To DECT
Figure 5. The functional diagram of: i) DEMUX, ii) FIR streams, and iii) SELECT module. Input
Figure 4. Block diagram of FIR & SELECT Block. TRANS The format of the digital output of the ADC AD9281 is straight binary. Since the format of the input data of the DECT Detector is in sign magnitude, we need a conversion from the straight binary format to the sign magnitude one. This conversion becomes in the TRANS module, whose input is a 8bit straight binary number, while its output is a 8-bit sign magnitude integer (i.e. MSB is the sign and the seven LSBs is the value of signal). FIR filter The chosen architecture of the system is a straightforward FIR implementation [11]. The block diagram of the 13-taps FIR of the DECT receiver is illustrated in Figure 6. In order to reduce the power consumption of the FIR, we have embodied in the implementation the following low power design techniques/principles: i. Use of shift-add operation. Since we have a multiplication of a constant (i.e. filter coefficient) times a variable (i.e. sample), the standard multiplication can be reduced to a
-69
-306
X
-370
X Reg
+
364
X Reg
+
2091
X Reg
+
4035
X Reg
+
4899
X Reg
+
4035
X Reg
+
2091
X Reg
+
364
X Reg
+
-370
X Reg
+
-306
X Reg
+
-69
X Reg
+
X Reg
+
Output SNART
Figure 6. Block diagram of 13-taps straightforward FIR. The input and the output of FIR are 8-bit sign magnitude integer (MSB is the sign and the seven LSBs is the value of signal). To attain sufficient accuracy and avoid the overflow possibility the internal buses have 24-bit length. Since the given coefficients are real numbers between –1 and 1, possible filter implementation with these coefficients would require a floating-point architecture. For that purpose, to simplify the design, a scaling technique is used to convert the filter coefficients into integer numbers. Thus, all the coefficients are multiplied by 16384. Because of these multiplications, the output of FIR multiplied with 16384, the output should be divided by 16384. The corresponding frequency response is depicted in Fig. 7. We implemented the FIR filter using Cadence environment. After synthesis and simulation, we concluded that the FIR
operates with 4.608 MHz clock frequency, the area is 7.075mm2 using 0.7ìm technology. For power consumption calculation, we use the tool, which has been reported in [2], and the measured power dissipation is 3.568 mW/MHz. 10
dB 0
-10
Frequency response after multiplication by 16834
-20
-30
-40
Initial Frequency response
-50
-60 0
0.5
1
1.5
2
2.5 6
x 10
Hz
Figure 7. Frequency responses comparison. SELECT Block The SELECT block functions as a multiplexer, depending on the value of 2-bits external signal Detector_in_Select_Signal. Table 2 describes the relationships between the input and output signals, given the values of Detector_in_Select_Signal. 4. Technical Features of GMSK/GFSK MoDem Having a large number of data streams, we construct a board for making actual measurements. For that purpose, we implemented the whole modulator/demodulator in a certain FPGA. A RTL description of the design was implemented using behavioral VHDL. The correct functionality of this model was verified using the HDL simulator ModelSim. The VHDL code was synthesized with FPGA-Express of Synopsys, and mapped to a XILINX FPGA using the Alliance distribution of the Xilinx tools (Design Architect). Implementation constraints were set in order to achieve the required frequency specifications while keeping the area required below the capacity of the selected device. Various aspects of the design implementation can be seen in Table 3. Detector_in_ Select Signal 00 01 10 11
Input data of DECT Detector 6 MSBs of FIRs output AGC output 6 MSBs of DEMUX output AGC output
Input data of AGC FIRs output FIRs output DEMUX output DEMUX output
Table 2. The functions of "SELECT" block. 5. Conclusions The implementation of an integrated GFSK/GMSK modulator/demodulator was presented. The main functional characteristics of the various modules (modulator, demodulator, FIR), the new low power techniques, and the FPGA implementation features were provided. More specifically, we applied existing low power techniques and used a new low power design methodology [4]. The modulator and FIR filter were designed employing existing techniques, while the demodulator, the most complex part, was designed using introduced power optimization techniques. References [1] D. Moolenaar, 'Building Blocks Preliminary Design Report (Processor Core)', ASPIS project deliverable, EP20287/IMEC/VSDM/DS/D4.2.R1/a1, May 1997.
[2]
N. Zervas, S. Theoharis, D. Soudris, C.E. Goutis, and A. Thanailakis, “Generalised Low Power Design Flow,” LPGD/WP1/DUTH/D1.3R1, Jan. 1999.
Target Device/Package # of External IOBs Number of CLBs Total CLB Flops 4 input LUTs: 3 input LUTs: # of clock IOB pads # Global Buffer IOBs Total # gate count Number of paths Minimum period Maximum frequency Maximum path delay Average Clock Skew Technology I/O voltage Core voltage
x4062xla /hq240 65 out of 193 33% 2304 out of 2304 100% 1516 out of 4608 32% 4211 out of 4608 91% 505 out of 2304 21% 2 out of 12 16% 2 out of 8 25% 49931 1,491,869,119 91.396 ns 10.941 MHz 91.396 ns 0.512 ns 0.35ìm 3.3 V 3.3 V
Table 3. Characteristics of the implemented FPGA. [3] G. Kalivas, A. Tzimas, E. Metaxakis, and K. Katis, “Study, Analysis, and Exploration of Candidate Algorithms,”Report, LPGD/WP2/UP/D2.1R1, June 1998. [4] N. Zervas, D. Soudris, C.E. Goutis, and A. Thanailakis, “Low-Power Methodology for Transformations of Wireless Communications Algorithms,” Deliv. Report, LPGD/WP2/DUTH/ D2.2R1, Jan. 1999. [5] M. Perakis, D. Soudris, C. Goutis, and A. Thanailakis, “Low-Power Architecture Design of GSM/DECT Algorithms,” Report, LPGD/WP3/DUTH/D3.3R1, Dec. 1998. [6] M. Perakis, et al “The Synthesizable HDL-based description of GSM-DECT Application,” Deliverable Report, LPGD/WP3/DUTH/D3.4S1, Dec. 1998. [7] H.C. Karathanasis, V. Bella, S. Blionas, D. Dervenis, C. Dre, 'Market Input Report for Multi-mode Terminal Specifications', ASPIS project deliverable, P20287/ ICOM/DPD/DS/D6.1.R1/a1, Version 4, 15 June 1996. [8] M. Perakis, et al “The VLSI Implementation of a Baseband Receiver For DECT-Based Portable Applications,” in Proc. of Int. Symp. on Circuits and Systems (ISCAS), Orlando, USA, May 30 - June 2, 1999, Vol. I pp. 198-201. [9] L. Benini, G. De Micheli, “DYNAMIC POWER MANAGEMENT. Design Techniques and CAD tools”, Kluwer Academic Publishers, 1998. [10] N.Zervas, et al, A Methodology for the BehavioralLevel Event-Driven Power Management of Digital Receivers,” accepted for presentation at ISCAS 2000, May 28 - 31, Geneva, Switzerland [11] Neil H.E. Weste and Kamran Eshraghian, “Principles of CMOS VLSI Design, A Systems Perspective”, AddissonWesley, 1994. [12] A. Chandrakasan and R.W. Brodersen, “Low Power Digi-tal CMOS Design,” Kluwer Academic Publishers, 1995.
