Micro power CMOS analog cells

June 24, 2017 | Autor: Marley Vellasco | Categoria: Power Consumption, Mixed Mode, Design Methodology, Low Power, Level
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Micro Power CMOS Analog Cells Fabio A. Salazar,COPPE/UFRJ, Júlio C. G. Pimentel, Member, IEEE, Marco A. Pacheco, Member, IEEE, Marley Vellasco, Member, IEEE

Abstract Low power supply consumption has become one of the main issue in electronic industry for many product areas such as cellular telephones, portable personal computers and biomedical implants. The aim of this work is to investigate the main drawbacks involved in the design of CMOS analog cells biased in weak inversion. Biasing a cell in weak inversion makes it possible to achieve a power consumption that is one thousandth lower than common analog cells designed to operate in strong inversion. This work has involved the following subjects: a study of models for MOS transistors operating in weak inversion and strong inversion regions; a methodology to convert LEVEL 2 Spice model to EKV model; study of basic analog cell blocks suitable to low power mixedmode IC design; design methodology for low power analog cells; comparison between these cells and some commercial ones; study of analog layout techniques.

1. Introduction Low power IC design technology was developed originally for electronic wristwatch industry [1]. However, this technology is now being also used to develop many types of battery operated devices such as pocket calculators, pacemakers, hearing aid devices and so on. Recently, new applications were reported in instrumentation and massively parallel systems based on neural networks [2]. Mostly, all these applications involve low voltage power supply, typically in the 1V to 3V range, and very small power supply current usually lesser than 50uA. CMOS is likely the best technology to address these requirements because of its low manufacturing cost, high reliability and capability to integrate low power digital and analog circuit in the same IC [1]. Though there are some high technology centers in Brazil with expertise in mixed-mode application specific integrated circuit, they do not have enough experience on micro power integrated circuit design. Since this technology is potentially useful to solve some power system problems, it is very important to train people on this new technology. This work was done under the

cooperation agreement established between CEPELPower System Research Center, and the Electrical Engineering Department of PUC/RJ. The aim of this paper is to investigate the potential of MOS transistors operating in weak inversion in the development of micro power analog cells, and understand the various tradeoffs involved. Chapter 2 presents the modeling equations of a MOST biased in weak inversion and its fundamental characteristics. Chapter 3 presents an example design of a micro power operational amplifiers and an OTA. Chapter 4 compares their simulation results with a paper reported amplifier and some commercial ones. Finally, chapter 5 presents the conclusions and propose some future works.

2. The weak inversion Region The operating region below sub-threshold voltage is called weak inversion region (WI). In a MOST biased in WI the most part of drain current is due to diffusion current, related to thermal generation of minority carriers in the PN junction, instead of drift current, generated by electric field under the gate [4]. Thus, drain current is strongly dependent of bulk temperature [3]. Equation 2.1 is the drain current Id of a MOST in WI[1]:

I

D

=

VG  VS V D  − U U T T I D0 e  e eU T  n

(2.1)

where:

KT termical voltage q K Boltzmann constant(1.38x10-23 J/°K ) T Temperature in degrees Kelvin q Charge of an electron ( 1.6 x 10-19 C ) n Slope factor of curve Vg x Vp in this equation Id0, the characteristic current, is defined as follows:

U

I

T

=

D0

 Vto   −    n T

= 2 nβ U T e U 2

where:

(2.2)

β=µCOXW/L (SI transfer parameter), µ=electron mobility in the channel, W=channel width, L=channel length. Id0 is a parameter strongly dependent on temperature [5]. Therefore MOST in WI is generally biased by a fixed Id current instead of Vg voltage, as in traditional design technique. A MOST biased in WI must comply with the following requirements [3]: Saturation: VD − VS > 3U T (2.3)

I D < 2n

WI:

K PW 2 UT L

(2.4)

We may notice that a MOST in WI needs a much lower VDS voltage to guarantee saturation than SI MOS transistors. The minimum W/L ratio to guarantee WI operation can be calculated from eq. 2.4. Therefore, we usually use much more area for WI circuits than for SI one. From eq. 2.1 we may determine the transcondutance gm of MOST operating in WI [3]:

∂II D I gm = = D ∂VG nU T

VE =

ID VE

(2.6)

2qN A VDS + Φ

ε

L

(2.7)

Where VE is the Early voltage [6] [7]. From eq. 2.5 and 2.6 and from characteristic equations of MOST in strong inversion (SI) we may draw the comparative graphic of figure 2.2 where we can see that MOSTs achieve their maximum gain in WI, and it decreases continuously after the transistor comes deeper into SI. Moreover, we may also notice that the WI gain is independent of drain current Id. Furthermore we may expect higher output resistance due to the small Id current. On the other hand a higher W/L ratio implies a lower noise resistance Rn for the same Id. gm α ID1/2 log gm α ID gds α ID

A M AX =

V nU

Figure 3.1 below shows a design flow for micro power CMOS analog cells. Since low power consumption is the main requirement there is an upper limit for power supply current. Firstly, we determine the biasing current based on the total current allowed and slew rate constraint. Then we may calculate the minimum size for WI transistors. Afterwards we must check if we achieved the gm, DC gain and GBW for the specified capacitance CL.

Start gm=ID/nUT

gm=ωTC

(high freq. gain.)

ID

ID SR1. Defining the amplification factor B as I7/I5 we may write:

SR1 =

I5 Cc

(3.1)

SR2 =

I7 Cc

I5 I7 I * B I5 ⇒ CL < B*CC > ⇒ 5 > CL CC CL CC g I5 GBW ≅ m1 ⇒ GBW ≅ 2nU T CC CC

(3.2)

(3.3)

(3.4)

where the maximum value for Cc, and hence CL, should comply with SR and GBW requirements above. The actual value for Cc and Rz may be calculated according to the well-known pole-splitting compensation technique. Since M1, M2 and M6 are in WI, this requirement imposes an lower limit to their aspect ratio. The SI transistors may not have an extremely large aspect ratio in

order not to violate the SI constraint. On the other hand they can not be too much small so parameter manufacturing variations do not become a serious problem.

Fig. 3.3 - Basic CMOS OTA

Fig. 3.2 - Basic CMOS Op Amp In order to achieve a reasonable noise figure, designers should provide at least a 10 µm channel length for transistors M1, M2 and M6. Also, there is a lower limit to M5 channel length imposed by CMRR constraint. Equation 3.5 for DC gain ADC below tells us that for the circuit of figure 3.2, ADC depends mainly on channel length of M1,2, M3,4, M6 and M7. So, we are not free to choose any value for those parameters as we would like to. Considering all these constraints we may now determine the geometry for the transistors. However, some applications need higher output drive capability than we can achieve with Op Amp shown in figure 3.2. For these applications we may use an class AB output Op Amp as proposed in [9].

g m2 g m6 * ADC = g ds 2 + g ds 4 g ds 6 + g ds 7 1 1 * ADC = nUT  1 1  2 2  +  +   VE2 VE4   VE6 VE7 

⇒ (3.5)

3.2 – Op. Transcondutance Amplifiers (OTA) OTAs are usually a better solution to micro power analog circuits because they do not need an extra compensation capacitor that would increase power consumption and decrease its speed. Actually load capacitor works as a compensation capacitor [1] [3] [5]. Besides, Op Amps become unstable when CL increases while OTAs behave actually the opposite. Also, high quality OTAs aimed to drive capacitive loads can be realized by very simple circuit topologies. Micro power designers should avoid using cascaded topologies when designing low voltage and low current circuit due to the extra voltage drop involved. Figure 3.3 shows a simple OTA topology suitable to low power circuit realization.

Once more, the design starts at the slew rate requirement. Parameter B below is defined as the ratio I7/I5. It should be higher than unity to achieve the highest slew rate and GBW for the same total bias current. In practice B must be lower than 4 because of current mirror mismatch and increased capacitance in the inner nodes [5][10]. Let us choose B=2, which is a reasonable choice. So we may write:

SR = B *

I5 CL

(3.6)

So, the slew rate of an OTA depends entirely on bias current, while Op Amp slew rate depends on compensation capacitor also. From eq. 3.6 above and the maximum power supply current constraint we may now determine the bias current for each transistor. In order to increase DC gain and input voltage range we must bias M1 and M2 in WI choosing W/L ratio as follows:

(

W I5 )(1,2) ≥ 5 * 2 * n * KP * (Ut ) **2 L

(3.7)

Since all the other transistors are current mirrors they must be biased in SI to achieve a better matching. Thus the expression for the GBW and DC gain becomes:

g m1 + g m 2 B BI5 * = 2 CL 2 nCLU T 1 gm1( 2) gm6 nUT = = 1 1 gm3( 4) ( gd 6 + gd 7 ) + VE 6 VE 7

GBW =

(3.8)

ADC

(3.9)

W5 and L5 are determined from CMRR requirement and SI condition for M5. The OTA above can achieve a DC gain as high as 70dB. However, some applications need an even higher gain. For these applications we may use the cascaded-OTA. It can achieve a higher gain due to the extra load imposed by transistors at second stage.

4. Results This item compares the behavior of a micro power OTA designed according to the methodology above to a

previous work [8] and to some commercial ones [6]. Table 4.1 summarizes the results. OTA1 is a cascaded OTA (Ip=0.25µA) designed according to the methodology presented above. OTA2 was designed by Krummenacher [7]. We may notice that OTA1 and OTA2 have roughly the same electrical characteristics for the same power consumption and same output capacitance. However, OTA2 has a much higher offset voltage, since OTA1 results come from simulation and hence do not take into account manufacturing parameter variations. Table 4.2 compares some electrical characteristics for the OTA and Op Amp designed. The OTA is faster than the Op Amp, as we had foreseen, and has a better phase margin. The Op Amp is also more power hungry than the OTA. Besides, the OTA improves its dynamic behavior when the output capacitance increases. The Op Amp, on the other hand, becomes unstable when the output capacitance increases.

Load Cap. Ibias Itotal Ao fo phase margin offset SR pos SR neg CMRR Noise 1khz

Krumme nacher OTA2 10 0.5 2.5 97 135 ------

OTA1 cascode

OTA1 cascode

Unity

10 0.5 2.5 123 152 57

15 0.25 1.25 122 60 70

pF uA uA dB Khz °

5m 100 -----84 150

2µ 92 93 91 174.7

2µ 32 32 86 209.4

V mV/uS mV/uS dB nV/√hz

Table 4.1 - OTA comparative results Load standb Cap. y (pF) consu mp (mA) class A 3 0.75 Op Amp class 10 0.82 AB Op Amp basic 3 0.75 OTA OTA 10 1.25 cascod

dynamic consump (mA)

Ao fo phase Over SR (dB) khz margin shoot mv/µ (º) (%) s

1.53

115

170

43.5

50

126

1.92

116

125

28

50

100

1.12

71 183.5

28

40

138

1.65

122 84.5

62

8

48

Table 4.2 - Comparison between Op Amp and OTA

5. Conclusion This work presented a design methodology suitable to analog micro power CMOS cells which consists in biasing some MOST in WI region. OTAs achieve a better performance than Op Amps when biased at small power

supply currents typically in the 1µA range. Biasing MOS transistors in weak inversion region has proved to be a valuable technique when designing micro power analog CMOS circuits, but circuit performance becomes strongly dependent of the stability of the biasing current source. Some future work has still to be done to improve micro power circuits bandwidth while keeping its consumption low. References [1] E. A.Vittoz, "Micro Power Techni ques", in Design of MOS VLSI Circuits for Telecommunications, P. Antognetti and Y. Tsivids editors, Prentice-Hall,1985. [2] E. A. Vittoz, “Low-Power Design: Ways to Approach the Limits”, Paper WA 1.1, ISSCC 94. [3] E. Vittoz and J. Fellrath, “CMOS Analog Integrated Circuits Based on Weak Inversion Operation“, IEEE Journal of Solid State Circuits, Vol. SC-12, No.3, June 1977. [4] S. M. Sze, "Semiconductor Devices, Physics and Technology", John Willey & Sons editors, 1985. [5] E. A. Vittoz, "Micro Power Techni ques", in Design of Analog-Digital VLSI Circuits for Telecommunication and Signal Processing, J. E. Franca and Y. Tsivids editors, PrenticeHall,1994. [6] EM Microelectronics - MARIN S.A. - EM Cell Libraries, Analog Cells HCMOS-LV3 Revision C, 02/92. [7] F. Krummenacher, “High Voltage Gain CMOS OTA For Micro Power SC Filters“, Electronics Letters, vol.17, No.4, Feb. 1981. [8] T. Fiez, R. Croman, E. Schneider and M. Goldenberg, “Current-Mode Signal Processing”, in Analog VLSI Signal and Information Procesing, Edited By M Ismail and T. Fiez, McGraw-Hill 1994. [9] F. de A. Salazar, “Design of CMOS Micro Power Analog Cells Based on MOS Transistors Biased in Weak Inversion”, M Sc. Thesis Dissertation, DEE-PUC/RJ, August 28th, 1996. [10] W. Sansen, “Design of Analog CMOS Building Blocks”, 4th Brazilian Workshop on Microelectronics, pp 149-155.

Fabio de A. Salazar

received the B Sc. In Electric Engineering from USU in 1990 and the M Sc. from PUC-RJ in 1996, both at Rio de Janeiro, RJ, Brazil. Acutualy is working on his PHD degree at COPPE/UFRJ e-mail [email protected] Julio C. G. Pimentel received the B Sc. In Electronic Engineering from EE-UFRJ in 1984 and the M Sc. In Computer Science from COPPE/UFRJ in 1990, both at Rio de Janeiro, RJ, Brazil. He has been with the Electronics Department of CEPEL - Brazilian Power System Research Center (Eletrobrás) since 1985 where he has been engaged in the design of electronic equipment for electric energy measurement and mixed-mode ASIC designs. Marley Vellasco and Marco A. Pacheco ICA Research Group in Applied Computational Intelligence Electrical Engineering Department-PUC/RJ Rua Marquês de São Vicente 225 CEP 22453-900,Rio de Janeiro- Brasil E-mail: [email protected]

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