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SDRAM controller for real time digital image processing systems Tomasz Szymanski, Rafak Kiekbik, Andrzej Napieralski A h t n i c t - Nowadays a lot of modern digital systems are based on processor-memory architeclure. Additionally when large capacity and data transfer rate i s required, SDKAM memory is used. Moreover there is a trend to combine multi-chip systems into one device, so called on-chip systems. In such defined systems a built-in SDRAM controller is needed. This paper presents a SDRAM controller adapted to work in fast digital image processing systems. Interface of controller was simplified to give more flexibility in usage for designers. Keywords - Digital image processing, SDRAM controller.
I n other words price will incrcase. For this reason an optimization of controller in dependence of problem type being resolvcd must be taken into account. As in specific system not all functions of SDRAM must be supported, connected with it controller can be area reduced without performance decreasing. Other advantage of such solution is that memory controlling' becomes easier.
I. INTRODUCTION
In this article a SDRAM controller optimized for real timc Rapidly
growing development of silicon technology
increases performance of digital systems and logical capacity of devices. Level of nowadays technology provides designers with integrate multi chip systems into one device. Many parts of old-systems can now coexist on a single silicon wafer. I t
causes dramatically increase of performance with cost.
digital video stream servicing is described. Adaptation to digital video stream makes the controller easier in use and less resource consuming. Moreover access to the memory is easier by choosing only two commands (read and write) along with cell address. All other necessary fimctions, as initialize or rcfresh, are executed automatically without user interference.
reduction. Indispensable part of today's systems is a processor
11. SYNCHRONOUS DRAM BASIS
connected to a memory. Performance of such architecturc mainly depends on clock speed and data access time. .The best
SDRAM memory is a next generation of silicon data
results are obtained with a static mcniory but capacity is very
storage after common DRAM'S. The main difference between
small. For solution, which requires big data storage and
them is a clock. In new generation type of DRAMS, data,
relatively short random access time, SDRAMs (Synchronous
address and control lines are latched on the clock. Because of
The
synchronous access style in SDRAMs, controlling and
disadvantage of that is an extra logic called SDRAM
performance can be better in comparison with standard
controller needed to operate. The controller is being used not
DRAM's. New generation of memory supports also new
orily for read and write operation but also acts as an cxccutor
features makes the functionality much more efficient.
Dynamic '
Random
Access
Memory)
are
used.
of another necessary functions like refrcsh, sleep or initialize after power-on. Because of additional logic existence, the onchip system that uses SDRAM in comparison with system that uses SRAM (Static Random Access Memory) will be bigger.
SDRAM controlling is made by latching special commands applied on the control lines. All supported commands with logic states of control lines are given in TABLE 1 and shortly described below. For more precise information look at [ I ] and
Tomasz Szymanski E-mail:
[email protected] Rafat Kielbik E-mail: RKI ELB I K(6Jdmcs.p. lodz.pl Andrzej Napieralski E-mail: NAPIER~dincs.p.lodz.pl Technical University of Lodz. Department o t Microelectronics and Computer Scicnce (K-25). AI.Politechniki I I , 93-590 Lodz, POLAND. This paper was supported by grant No. 8TI I BO3618 of Statc Committee for Scientific Research.
PI. 'fwo NOP Commands prevents other commands from being cxccuted by the SDRAM. The first onc makes a chip disabled for the clock. Second one prevents unwanted commands from
being registel-ed during idle or wait-states. ACTIVE prepares
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desired data to be accessed. During this operation one part of
rcduction. In this application controller is based on finitc state
the address is loaded. READ and WRITE exchangc data by
machine. All states of it are divided into four function paths
applying second part of address. Onc of supported featurcs of
and one ‘Idlc State’ (Fig. I )
SDRAM memory is Burst Mode. In this modc SDRAM lcts to transfer data in so called packets. One packet can include iiiore than one data word, which appears one by one. In this
/-
way consecutive data in memory can bc accessible faster. BURST TERMINATE command breaks a Burst Mode while packet is reading or writing. Each access to the data must be
lnit Path
Refresh Path
finished by PRECHARGE. This command lets the memory to Read Path
be prepared to the next operation. Because of dynamic character of data storage, cells have to be refreshed periodically
by
executing
REFRESH.
LOAD
Write Path
MODE
REGISTER is applied during initialization process at the beginning of m e m o y usage. With this command a special Fig. 1 Controller functionality
attributes are set (i.e. Burst packet length, access type, CAS latency and other). From this moment the functionality of the memory is,detemiined.
i,
Each path is made up of consecutive states without branches and flow conditions. While inserting into specific state,
memory is loaded with certain command. At ‘Idle State’ the
TABLE 1
SDRAM COMMANDS Command m m e
I csx
/Command inhibit (NOP)
I H
IN^ operation (NOP)
I L
NOP command is executed. Below detailed functionality of paths is described. ‘Init Path’ - After power-on, SDRAM have to be prepared
and configured to be ready to operate. This process is carried out, by executing thirteen commands s h o k in Fig. 2.
..
.L
, i.
’
The main aim of-that path is to.configure memory during LMR command preceded by two refresh cycles.
/BURSTTERMINATE (BTR)
I
IPRECHARGE
I L
called refresh procedure to renew data stored in capacitors.
REFRESH (REF)
L
This operation must be done for. all memory cells once per
LOAD MODE REGISTER (LMR)
L
specific time period. For application discussed in this paper,
(PRE)
L
‘Refresh Path’. Dynamic type of memory requires so .
.
refresh is done in four clock periods represented by states given in Fig. 3 .
111. CONTROLLER SPECIFICATION As the controller being described in this article is intendcd to work within real time digital picture processing system, some of SDRAM features can bc oinittcd without performance
Lviv-Slavsko, Ukraine. VI-th International Cotifercticc llic tiupcricncc 1 1I i h i g i i i t i g atid Applicntioii ofC.4D Systems
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NOP
NOP
0
-Valid data
Fig. 5 Write process
Fig. 2 Initialize process
cF> begin
Controllcr moves between discussed above four paths but sometimes stays in ‘Idle State’. Decision “Where to go” is taken in ‘Command Resolving’ box (Fig. I ) . This box is responsible for refresh time counting also. The most
Fig. 3 Refresh process
importance has ‘Init Path’, which is called once after poweron. After initialization is done the ‘Refresh Path’ captures a priority over other paths. Whenever resolving box calculates that refresh is needed and the last path is done controller enters into ‘Refresh Path’. If refresh is not required user CMD line is sampled to determine if the read or write path should be executed. When no access to the memory is needed CS (Chip Select) must be deselected and than controller goes into the ‘Idle State’. Deselecting CS signal prevents executing read or write operation only. It does not affect on initialization or
Fig. 4 Read process
refresh processes.
‘Read Path’ and ‘Write Path’ are responsible for data
The architecture defined in this chapter makes the controller
exchanging. T o increase performance of memory, data is read
interface simpler and easier to apply in a large system. The
or written in four word packets (‘Burst Mode’), so the address
only signals required to control SDRAM are shown on the left
is given once per packet (Fig. 4 and Fig. 5). The only
edge of the box given in Fig. 6. CMD determine if the data
requirement is that all words in packet have to be consecutive
will be read or written. CMD is sampled (when C S is active)
in address space. In the event of video systems it is not
at the end of executing of any path or while the controller
onerous because in most cases algorithms are executed on
stays a‘t the ‘Idle State’. RD-VAL indicates valid data to be
neighboring pixels. As it can be seen boot paths are very
read. WR-VAL demands data to be written. ADDR indicates
similar and executes in eight cycles each. The first path diffcrs
location of first word to be read or written. In Fig. 6 the data
form second one in third command and in location of valid
bus is not shown.
data presence. While reading, the first word is valid during transition to state five and while writing, the first word must be valid before transition to state three.
Lviv-Slavsko. Ukrdiiic. V I - t h Intcrnalional Conference the Expcricncc cif Designing and
.Application of CAI) Systems i n
Microelectronics
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appioxnrlgtcly*Fan obtain 400 Mbytes pcr second It means
csx
that data corresponding to pixel can be transfcrrcd to or from
CAS RAS
D
iiicniory fifteen times during pixel presence. Such ratlo in most cases is sufficient
A[11:0] DQMB[7:0]
(ADOR
v. CONCLUSION In this papcr SDRAM controller optiniizcd to digital vidco
Fig. 6 Controller interface
strcain transferring was presented. As it was shown in chapter IV performance of the controller mostly dcpends on clock
Iv. PERFORMANCE ESTIMATION
frequency. Bccause amount of resources needcd to controller
Because lengths of paths described in previous chapter are
building is very low, clock frequency as large as 100 MHz is
constant, performance of controller can be calculated in
very easy to obtain even in obsolete technologies. As a
fiinction of clock frequency. Execution tiines of significant
practical application “The Reprograillnlable Digital Image
paths are:
Processing System” can be mentioned. This application is trcf=
Le,.
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,
based on FPGA technology. Details are available in [4].
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