Ultra-low power Digital System Design using Sub-threshold logic styles

Ultra-low power Digital System Design using Subthreshold logic styles

Abstract— The paper shows the implementation of digital circuit design using ultra-low power logic components. Fundamentals of Source coupled logic (SCL) gates are used with running at subthreshold regime with the purpose of achieving low power consumption while keeping a satisfactory output swing. The digital systems designed for this paper are 4x4 array multiplier and a 55th order FIR filter. Later on in this paper the STSCL (sub-threshold source coupled logic) circuit is added with controllable voltage-level feature to minimize overall leakage current flow, including both gate leakage and sub-threshold during. To test the proposed technique a seven-stage ring oscillators is designed in CMOS, STSCL and the proposed logic at similar supply voltage to observe the differences with power consumption. Consumption for the proposed technique came at nW range. All measurements are shown using both 45nm and 65 nm process technology, with scaling at a supply voltage as minimum as 0.4 V. Keywords-component; sub-threshold source couple controllable voltage level, gate leakage, PDP, FIR filter

I.

sub-threshold source coupled logic (STSCL) and STSCL with controllable voltage level attributes for the reduction of overall total leakage consumption within a system.

logic,

INTRODUCTION

Digital circuits and systems at current nano-scale processes is highly in need of running at ultra-low power configuration. Most of the current techniques that are used in reduction over leakage current flow, mainly deals with minimization subthreshold leakage and consumption due to dynamic leakage. But as silicon process technology is getting lower than 65nm the gate leakage phenomenon [1] causes more threat in terms of leakage current flow than the other components. The gate to channel component [2] of the gate leakage for an NMOS for example, at 45nm and 65nm as given in figure 1 clearly shows the prominent rise in gate leakage to the whole power dissipation due to leakage compare to sub-threshold leakage current flow when moved from 65nm to 45nm process. The gate leakage increased by 10 factors whereas sub-threshold leakage increases by 3 factors for scaling from 65nm to 45nm technology. CMOS logic with current techniques mostly ignores the significance of gate leakage contribution and hence new techniques and logic styles need to be implemented and put into limelight in the digital field where constraints over power consumption is off high priority. The demand for ultra-low power is enormously high in fields of bio-engineering and low power sensor development. The focus of this paper clearly points towards those fields with the motivation of utilizing differential logic techniques such as

Figure 1. Gate leakage for NMOS at 45nm (left) and 65nm (right) process

Normally for CMOS gates power consumption is lowered by dynamic scaling of supply voltage, however this has a drawback as it substantially degrades the output voltage logic swing. Along with this delay of the logic gates also increases thus further worsen the performance. The analysis of performance of the system for this paper is measured with respect to power consumption and PDP (power delay product). Hence lowering supply voltage for CMOS logic has its limitation also the logic not performs or function at very low supply. Now running STSCL logic used in this paper runs at subthreshold region to scaling of supply voltage to a very low value very much possible and also due to operation at substhreshold region causes the elimination of sub-threshold leakage current contribution from the total leakage current flow thus leaving gate leakage as the sole significant contributor to overall leakage current. Figure 2 shows the gate leakage current flow for STSCL inverter (circuit diagram given in Figure 3).

only come during wiring of gates in designing a whole system. For STSCL, the N-MOSFETs in it functions at weak inversion region, thus it requires very low voltage as small as off value 0.15 V to completely switch the output of a next logic stage, even though in practical aspect the input supply has to be above 0.2 V for the logic to operate properly, figure 4 shows the reason with no drain current flowing through the STSCL inverter below at 0.2 V. Now even if the supply is above 0.2 V it is still low and allows power consumption level to be extremely low, but one thing has to be kept in mind about the fact of not endangering the output swing. One drawback that might arise is the with the operation time which is directly proportional to the bias current, Ibias, (equation 1). It is generated from the bias circuit as shown in figure 2 whereas the overall power consumption is reversely dependent on Ibias. This forces a trade-off at choosing the correct bias current for achieving an optimum PDP value.

τ = Vswing * CL / Ibias

()

Figure 2. Gate leakage current for STSCL

The total current flow equals (349.6 – 156.9) = 192.7 fA. II.

STSCL – SOURCE COUPLED LOGIC AT SUB-THRESHOLD REGION

Figure 4. Id Vs Vdd for STSCL Inverter

Figure 3. STSCL Inverter [1]

Figure 3 depicts a basic STSCL inverter [3] with differential input/output gates. Complexity with this kind of logic styles

To run the STSCL circuit an additional bias circuit (figure 5) is necessary it has to be kept in mind that there is a limitation over the number of gates that can be run by the bias circuit also sensitivity of the bias circuit is important factor to be concerned as it may harm the swing and degrade performance. For the circuit diagram shown below we used an ideal amplifier and gain has been kept under a very small very otherwise the Vpn node with generate high negative voltage which is significantly above the magnitude of the supply voltage range. Figure 6 shows the Vpn node variation with respect to amplifier's gain.

high gate oxide to create a virtual ground above the actual reference level which lowers the overall supply to ground voltage. The larger channel length MOSFET with high gate oxide further avoids gate leakage flow. The additional PMOS diode connected allows the virtual ground voltage to be adjusted. This causes any off-state current flow to be low causing gate leakage to be less.

Figure 5. STSCL Bias Circuit

Figure 7. STSC-CVL Inverter (Sub threshold source coupled contrlled volteg level logic)

A. Seven Stage ring oscillator

Figure 6. Variation Vpn node due amplifier’s gain

III.

RING OSCILLATORS IN STSCL AND ON A NEW TOPOLOGY

Figure 7 shows the STSCL inverter logic with a controllable voltage level attribute (STSC-CVL). The NMOS fed with Vbn from the bias can also be used with larger channel length and

Figure 8. Output respose for the seven stage STSC-CVL ring oscillator

To understand the sub-threshold logic and compare its advantage over CMOS logic, seven stage ring oscillators are designed using the three different logic circuits. The output frequency was measured along with power consumption at different supply voltage and results are shown tabulated in table 1.

TABLE I.

COMPARISON OF POWER CONSUMPTION FOR THE SEVEN STAGE RING OSCILLATOR USING THREE DIFFERENT LOGIC

Supply = 0.7 V

CMOS

STSCL

STSC-CVL

Frequency (GHz)

1.67

0.99

0.95

Power Consumption (uW)

12.98

6.48

4.17

Supply = 0.5 V

CMOS

STSCL

STSC-CVL

Frequency (GHz)

0.678

0.540

0.399

Power Consumption (uW)

3.21

1.03

0.89

Supply = 0.4 V

CMOS

STSCL

STSC-CVL

Frequency (GHz)

0.298

0.228

0.190

Power Consumption (uW)

0.73

0.36

0.27

B. Implemented logic blocks in STSCL for 4x4 multiplier and 55 order FIR Filter

The previous figures (in figure 9) shows few of the STSCL logic gates , used to form logic blocks including a Full adder (FA), d-flipflop (DFF), 4x4 array multiplier, 5bit SerialParallel multiplier and 55 order FIR filter. Figure 10 and 11 shows the array multiplier and the delay versus biasing current plot. The biasing current is chosen due to the fact as mentioned before, the dependency of power consumption for STSCL on Ibias.

Figure 10. 4x4 array multiplier

In this section we look at the different gates implemented using STSCL. The circuit level diagrams of all the gates are given. All the circuits are simulated and analyzed at conditions from worst case to normal. The performance of each gates are tested under conditions which will allow us to understand the limitations of STSCL, so that during designing of systems we can use the nominal parameters of STSCL that will generate a optimum level output for the corresponding system.

Figure 11. Ibias Vs Delay

C. FIR filter using STSCL

Figure 9. STSCL OR gate (left) XOR gate (right)

Further justifying the sub-threshold logic styles for digital circuit implementation a 55 order FIR filter was constructed with a sampling frequency of 20 MHz. The filter response along with its block diagram is shown in figure 12 and figure 13 respectively, with designing done in CMOS and STSCL. A 8bit serial-parallel multiplier [4] is designed as a requirement for the filter design, with fixed coefficient values. Ibias, is maintained above 10nA for obtaining the desired filter output.

Figure 13. Block diagram of 55 order Filter Figure 12. Filter Magnitude and Phase Responce

The PDP results for the simulation for the two logic are shown in Table 2 and 3 respectively for 0.5 V and 0.7 V power supply. TABLE II.

CONCLUSION The design of the FIR filter certainly meets the motivation behind choosing sub-threshold logic styles over CMOS for achieving ultra-low power criteria, as the results clearly show it.

SIMULATION RESULT FOR 0.7V SUPPLY

CMOS

STSCL

Power Consumption (uW)

191.32

89.2

Delay(ns)

2.86

4.13

PDP(fJ)

547.17

368.39

Logic Vdd = 0.7 V

ACKNOWLEDGMENT The authors would like to thank Lars Wanhammar and Oscar Gustafsson for their contribution to the completion of this paper. REFERENCES

TABLE III.

SIMULATION RESULT FOR 0.5 SUPPLY

Logic

CMOS

STSCL

Vdd = 0.5 V

[2]

[3]

[4]

Power Consumption (uW)

98.52

21.23

Delay(ns)

10.13

17.03

PDP(fJ)

998

361.55

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[1]

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