VLSI

25 nm CMOS Omega FETs

Nanoelectronics / VLSI / Leakage Current / Low Power Electronics / Iedm / Low voltage / Hot Carriers / Low voltage / Hot Carriers

A polyhedral approach to an integer multicommodity flow problem

Applied Mathematics / Vlsi Design / Integer Programming / VLSI / Telecommunication / Algorithm / Feasibility / Network Flow / Imp / Discrete Applied Mathematics / Algorithm / Feasibility / Network Flow / Imp / Discrete Applied Mathematics

Smart cameras as embedded systems

Computer Vision / Image Processing / Embedded Systems / Image Analysis / VLSI / Motion Analysis / Video Processing / Video Compression / Face Detection / VERY LARGE SCALE INTEGRATED CIRCUITS / Very Large Scale Integration / Feature Extraction / Low Power / Real Time / Layout / DESIGN SPACE / Streaming Video / Embedded System / Computer / Smart Cameras / Motion Analysis / Video Processing / Video Compression / Face Detection / VERY LARGE SCALE INTEGRATED CIRCUITS / Very Large Scale Integration / Feature Extraction / Low Power / Real Time / Layout / DESIGN SPACE / Streaming Video / Embedded System / Computer / Smart Cameras

Datapath design for a VLIW video signal processor

Signal Processing / VLSI / Very Large Scale Integration / VLIW / Real Time / Cycle Time / Compiler Design / DESIGN SPACE / Registers / Instruction Sets / Register File / Cycle Time / Compiler Design / DESIGN SPACE / Registers / Instruction Sets / Register File

A design study of a 0.25-μm video signal processor

Signal Processing / VLSI / Video Compression / Modules / Very Large Scale Integration / Network Design / Process Design / PMOs / VLIW / Circuit simulation / High performance / Cycle Time / High Speed / Sram / Area / Electrical And Electronic Engineering / Network Design / Process Design / PMOs / VLIW / Circuit simulation / High performance / Cycle Time / High Speed / Sram / Area / Electrical And Electronic Engineering

A method for linking process-level variability to system performances

Informatics / Statistical Analysis / Response Surface Methodology / VLSI / Very Large Scale Integration / Process Variation / System performance / Phase Locked Loops / Phase Lock Loop / Process Variation / System performance / Phase Locked Loops / Phase Lock Loop

A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations

Scheduling / VLSI / Very Large Scale Integration / Time Complexity / Circuits / Job shop scheduling / Logic Design / Logic Synthesis / Registers / Process Parameters / Cost Function / Quadratic Programming / Euclidean Distance / Integrated Circuit Design / Job shop scheduling / Logic Design / Logic Synthesis / Registers / Process Parameters / Cost Function / Quadratic Programming / Euclidean Distance / Integrated Circuit Design

A-Diagnosis: A Complement to Z-Diagnosis

VLSI / Fault Detection / Sequential Circuits

Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm

Combinatorial Optimization / VLSI / Assignment / Applied information technology

A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations

Scheduling / VLSI / Very Large Scale Integration / Time Complexity / Circuits / Job shop scheduling / Logic Design / Logic Synthesis / Registers / Process Parameters / Cost Function / Quadratic Programming / Euclidean Distance / Integrated Circuit Design / Job shop scheduling / Logic Design / Logic Synthesis / Registers / Process Parameters / Cost Function / Quadratic Programming / Euclidean Distance / Integrated Circuit Design

Two-dimensional digital filtering using a linear processor array

Computer Vision / VLSI / Parallel Processing / Nonlinear filters / Very Large Scale Integration / Dimensional / Digital Filter Design / Electronic Control Unit / Alu / Filtering / Input Output / Digital Filters / Speedup / Linear Array / Finite Impulse Response Filter / Dimensional / Digital Filter Design / Electronic Control Unit / Alu / Filtering / Input Output / Digital Filters / Speedup / Linear Array / Finite Impulse Response Filter

New 2 Gbit/s CMOS I/O pads

VLSI / Frequency / Impedance Matching / High performance / Voltage / Capacitance / Electrostatic Discharge / Low Complexity / Capacitance / Electrostatic Discharge / Low Complexity

Two-dimensional digital filtering using a linear processor array

Computer Vision / VLSI / Parallel Processing / Nonlinear filters / Very Large Scale Integration / Dimensional / Digital Filter Design / Electronic Control Unit / Alu / Filtering / Input Output / Digital Filters / Speedup / Linear Array / Finite Impulse Response Filter / Dimensional / Digital Filter Design / Electronic Control Unit / Alu / Filtering / Input Output / Digital Filters / Speedup / Linear Array / Finite Impulse Response Filter

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