60 GHz power amplifier utilizing 90 nm CMOS technology

RFIT2011-IEEE International Symposium on Radio-Frequency Integration Technology, Nov. 30 - Dec. 2, 2011, Beijing, China

60 GHz Power Amplifier Utilizing 90 nm CMOS Technology A. Hamidian1, V. Subramanian1, R. Doerner2, R. Shu1, A. Malignaggi1, M. K. Ali1, G. Boeck1 1. 2.

Microwave Engineering Lab, Berlin Institute of Technology, Berlin, Germany

Ferdinand-Braun-Institut, Leibniz-Institut für Hoechstfrequenztechnik (FBH), Berlin, Germany

Abstract— This paper presents a fully integrated 60 GHz two stage power amplifier for wireless applications using common source topology and power combining. The PA is implemented in a 90 nm low power CMOS technology. The output power of the amplifier has been improved with the help of Wilkinson power combining technique. Also the Wilkinson power combiner has been utilized as a part of input and output matching networks to match the 16 Ω at the terminals of the power amplifier to 50 Ω at the output of the Wilkinson network. At 60 GHz the power amplifier achieves 11 dBm saturation output power, 9 dBm output power at 1dB gain compression point and more than 8 dB small signal gain with a peak power added efficiency of 6%. The broadband performance of the gain has been achieved utilizing the cascaded structures. The matching networks are based on high quality factor shielded coplanar transmission lines and fixed 300 fF MIM-capacitors. The detailed design procedure and the achieved measurement results are presented in this work. Index Terms— 60 GHz, CMOS technology, Power amplifier, High data rate wireless applications.

I. INTRODUCTION

(a) (b) Fig. 1 a) Shielded coplanar transmission line. b) Quality factor and inductance.

11 dBm Psat, 9 dBm of output power at 1 dB gain compression (P1dB) and ~6% peak PAE from 55 GHz to 65 GHz. Also the small signal measurement showed a broadband performance of the PA. The rest of the article is divided into three sections. Section II discusses the PA design procedure. In section III the measured results are presented and compared with the simulated values. Section IV concludes the article with a summary and comparison.

The unlicensed bands on the millimeter wave (mm-wave) frequency range and the new technologies which provide cheap and reliable transistors with high ft and fmax give an opportunity to the circuit designer to realize circuits for various wireless applications. These applications are in all the ranges from high data rate short-range communication to automotive radar. In mm-wave range, 60 GHz (57 GHz to 66 GHz band) is mainly targeted for high data rate short-range communication while around 77 GHz are widely considered for automotive radar applications [2]. The advanced CMOS technologies (like 90 nm, 65 nm and 45 nm) enable CMOS circuit designs for 60 GHz and 77 GHz band. Circuit designers have utilized these new technologies to realize high performance mm-wave front-end circuits [1]. One of the most challenging circuits is power amplifier (PA). For high data rate communication at 60 GHz a broadband PA with high power and high linearity is required. The requirements of high output power obliged the circuit designers to utilize large transistor sizes, optimize the passive structures and employ various power combining techniques [1] - [4]. In this paper the design of a 60 GHz PA employing Wilkinson power combining has been investigated. To minimize the losses in the passive structures and Wilkinson power combiner a shielded coplanar transmission line has been designed (Fig. 1 a). Fig. 1 b presents the HFSS simulation results for transmission line with the width of 8 µm, spacing of 9.5 µm and length of 40 µm to 160 µm with 20 µm steps. The realized 60 GHz CMOS PA achieves

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II. THE DESIGNED POWER AMPLIFIER TOPOLOGY Common source (C.S.) and cascode topologies are the two common topologies utilized in the PA design. The cascode topology provides a better isolation between output and input ports which will improve the stability of the circuit and facilitate the matching network design. Also cascode topology in the HBT technology improves the gain and the output power of the PA [5]. The increase in output power is mainly due to the nature of the (a) (b) breakdown voltage in bipolar transistors which Fig. 2 The maximum voltage swing a) C.S. varies by the base b) Cascode

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impedance [6]. Unlike the HBTs in CMOS the cascode topology does not help in improving the breakdown voltage and hence the output power. Also to increase the drain voltage (more than 1.2 V) the triple well CMOS transistors are necessary which introduces more parasitic elements and deteriorate the transistor performance. By having the drain voltage fixed at 1.2 V the C.S. topology can deliver a better voltage swing (Fig. 1) at the output and hence a higher output power than the cascode topology. Due to these issues the C.S. topology is selected for this design. The simplified block diagram of the complete power amplifier is presented in Fig. 2 a. The symmetrical input and output Wilkinson power combiner-divider (Fig. 2 b) are designed with the transmission line introduced before. The complete structure has been simulated with the help of the 3-D electro-magnetic (EM) simulator HFSS. The design shows a combiner loss of less than 1 dB and better than 10 dB output

(a)

(b) Fig. 4 a) Schematic of the single PA. b) Chip photo. (a)

(b)

(c) Fig. 3 a) The PA block diagram. b) Wilkinson combiner. c) Simulation results

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matching from 55 GHz till 65 GHz (Fig. 2 c). The Wilkinson power combiner is designed to have 16 Ω impedance at the input ports and 50 Ω impedance at the output. This facilitates the matching network design and improves the output power of the amplifier. The total on-chip size of the Wilkinson combiner is 0.15 mm2. The schematic of the realized PA is shown in Fig. 4 a. The designed PA is matched at the output for the maximum linearity while the input matching is designed for broadband performance. The matching has been performed utilizing the low loss transmission lines presented before. The width and the spacing of the transmission line in the matching network are fixed to 8 µm and 9.5 µm. Although increasing the transmission line spacing to the ground walls increases the impedance and the quality factor, due to foundry restrictions on metal density extra fillers within the coplanar ground walls would be required. Also, to avoid the critical impact of the capacitor quality factor on the PA performance, the DC block capacitors are fixed to 300 fF. The size of the PA transistor has been selected for the optimum matching network design to 16 Ω with maximum power performance. Unlike the PA transistor, the preamplifier transistor is selected in such a way to avoid any distortion in the PA performance. After these optimizations the PA and pre-amplifier transistor sizes are fixed to 75 µm and 60 µm. Also as a trade off between gain and output power the drain current is fixed to 0.3 mA/µm. The chip micrograph of the complete PA is presented in Fig. 4 b. The total chip size including all the RF and DC pad structures is 0.76 mm2. The active area of the total chip (without pads) is 0.45 mm2.

Both large and small-signal measurements have been performed on-wafer. The measurement setup is the same as the one introduced in [5]. All the measurements have been carried out at the room temperature (23°C) for various bias points. The following sections describe the small and large signal measurement results and their comparison with the simulation.

Also the output matching values better than 10 dB is achieved for the frequencies above 60 GHz. Due to the low isolation in the C.S. topology, as expected the PA shows 20 dB isolation between output and input (Fig. 5 b). Finally, by utilizing the design technique introduced in [9] the broadband performance of the transducer gain is achieved. As shown in Fig. 5 b the PA shows almost a flat gain from 57 GHz till above 70 GHz with peak gain of 8.7 dB at around 59 GHz.

A. Small-Signal Results Fig. 5 presents the simulated and measured small-signal results of the realized PA. The PA and the pre-amplifier have been biased at 1.2 V with 1 V gate voltage. Due to the good small signal model of the transistors [7] and accurate modeling of the passive components [8] the comparison between simulation and measurement shows a good agreement. The main discrepancy between small signal simulation and measurement results has happened in the output matching of the PA. This can be mainly due to the large signal matching at the output of the PA and the low accuracy of the transistor’s large signal model. As shown in Fig. 5 a, the input matching values better than 15 dB is achieved for the whole band (57 GHz to 65 GHz).

B. Large-Signal Results The large signal measurement has been performed at three different operating frequencies (55 GHz, 60 GHz and 65 GHz). Fig. 6 presents the large-signal measurement results at 60 GHz with the same biasing condition as the small signal measurement. The large signal measurement results also showed a good agreement to the simulation results up to P1dB of the PA. From, Fig. 6 a it can be seen that the PA shows more than 8 dB gain with 9 dBm P1dB and more than 11 dBm Psat. Also, under this biasing condition PA consumes around 100 mW DC power at the saturation level resulting in more than 6% peak PAE and 10% drain efficiency (Fig.6 b). The detailed performance of the PA for each measured frequency is presented in Fig. 7.

III. MEASUREMENT VS. SIMULATION

(a)

(a)

(b) Fig. 5 Small signal simulation and measurement.

(b) Fig. 6 Large signal simulation and measurement. a) Power. e) Efficiency.

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TABLE I. COMPARISON OF OUR WORK WITH PREVIOUSLY PUBLISHED PAS*

Ref.

Topology

Voltage (V)

Gain (dB)

P1dB (dBm)

Psat (dBm)

PAE (%)

Total Size (mm2)

This Work

2 way power combining

1.2

8

9

11

6

0.76

[1]

DAT

1.8

26.1

10.5

14.5

10.5

0.64

[3]

Diff.

1

5.6

9

12.3

8.8

0.25

[4]

4 way power combining

1.2

20.6

18.2.

19.9

14.2

1.76

[10]

3 stages C.S.

1

10.

8.8

12.6

6.9

0.64

[11]

4 way power combining

1

4.4

12.1

14.2

5.8

1.2

* All results are at 60 GHz and the PAs are realized in 90 nm CMOS technology

ACKNOWLEDGMENT The authors would like to thank Heinrich Hertz Institute (HHI) for their support in measurements and all the project partners for their co-operation. This project is financially supported by Federal Ministry of Education and Research of Germany (BMBF) under the project frame of WiONet (No. 10033322): Wireless Communication and Networks (WN). REFERENCES [1]

Y. Jen, J. Tsai, T. Hunag, H. Wang, “A V-Band Fully-Integrated CMOS Distributed Active Transformer Power Amplifier for 802.15.TG3c Wireless Personal Area Network Applications,” in IEEE CSICS, pp.1-4, Oct. 2008. [2] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri, “A 77-GHz Phased-Array Transceiver with On-Chip Antenna in Silicon: Transmitter and Local LO-Path Phase Shifting,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2807-2819, Dec. 2006. [3] W. Chan, J. Long, M. Spirito, J. Pekarik, “A 60GHz-Band 1V 11.5dBm Power Amplifier with 11% PAE in 65nm CMOS,” in IEEE Int. SolisState Circuit Conf., pp. 380-381, Feb. 2009. [4] Chi Y Law and Anh-Vu Pham, “A high-gain 60GHz power amplifier with 20dBm output power in 90nm CMOS,” in IEEE Int. Solis-State Circuit Conf., pp. 426-427, Feb. 2010. [5] A. Hamidian, V. Subramanian, G. Boeck, “A 60 GHz 18 dBm Power Amplifier Utilizing 0.25 μm SiGe HBT,’’ IEEE EuMW, Oct. 2010. [6] H. Veenstra, G. A. M. Hurkx, D. van Goor, H. Brekelmans, and J.R. Long, “Analyses and design of bias circuits tolerating output voltages above BVCEO,” IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2008-2018, Oct. 2005. [7] A. Hamidian, V. Subramanian, Ran Shu, A. Malignaggi, G. Boeck, “Device Characterization in 90 nm CMOS up to 100 GHz” in IEEE SCD, Sept. 2011. [8] A. Hamidian, V. Subramanian, Ran Shu, A. Malignaggi, G. Boeck, “Extraction of RF Feeding Structures for Accurate Device Modeling up to 100 GHz” in IEEE IMWS, Sept. 2011. [9] A. Hamidian, V. Subramanian, G. Boeck, “Design of SiGe Broad-Band mm-Wave Power Amplifiers Applying Full EM Simulation” in IEEE IMWS, Sept. 2011. [10] N. Kurita, H. Kondoh, “60GHz and 80GHz Wide Band Power Amplifier MMICs in 90nm CMOS Technology,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 39-42, June 2009. [11] M. Bohsali, A. Niknejad, “Current Combining 60GHz CMOS Power Amplifiers,” in IEEE Radio Frequency Integrated Circuits Symp., pp. 31-34, June 2009.

Fig. 7 Large signal measurement results at three different frequencies.

IV. CONCLUSION In this work the design, optimization and realization of 60 GHz PA based on 90 nm CMOS technology has been presented. For achieving a maximum output voltage swing and hence a better output power the realized CMOS PA utilizes a common source topology. To improve the output power a Wilkinson combiner has been designed and the outputs of two single PAs have been combined. The designed Wilkinson combiner transfers the 16 Ω at the input ports to 50 Ω at the output which facilitates the matching network design and optimizes the power performance of the PAs. All the matching networks and Wilkinson combiners are designed with the help of low loss shielded coplanar transmission lines. These transmission lines showed a high quality factor while the coplanar ground removes the effect of the fillers on the transmission line. Utilizing a full chip EM simulation led to a good estimation of all the parasitic elements and resulted in a good agreement between simulation and measurement results. Finally, the PA has achieved comparable results to the other published 60 GHz 90 nm CMOS PAs (Table I).

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