Analog Integrated Circuits and Signal Processing, 41, 137–145, 2004 c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.
A 1 V Micropower FGMOS Class AB Log-Domain Filter ´ ´ RUBEN ´ FERNANDEZ, ´ ANTONIO J. LOPEZ-MART IN, CARLOS A. DE LA CRUZ BLAS AND ALFONSO CARLOSENA Department of Electrical and Electronic Engineering, Public University of Navarra, Campus Arrosad´ıa, E-31006 Pamplona (Spain) E-mail:
[email protected];
[email protected]
Received December 31, 2002; Revised July 2, 2003; Accepted February 12, 2004
Abstract. A novel first-order CMOS log-domain filter is presented. The internal voltage swing compression due to its instantaneous voltage companding nature, together with the use of Floating-Gate MOS transistors and its class AB differential topology, allows operation with a single 1 V supply while maintaining at the same time a large input range. Moreover, operation in weak inversion leads to very low power consumption. The filter can be tuned in more than one decade through its bias currents. Simulation and measurement results of an experimental prototype fabricated in a 0.8 µm CMOS technology demonstrate on silicon the feasibility of the proposed technique, which can be readily extended to higher-order filters. Key Words: analog CMOS circuits, continuous-time filters, log-domain filters, floating-gate transistors, lowvoltage analog design
1.
Introduction
Reliability and power consumption issues in modern submicron digital CMOS circuits, as well as increased demands of battery-operated portable equipment, are forcing analog circuits aimed to mixed-mode design to operate at supply voltages close to the MOS threshold voltage, and to consume at the same time very low power. In this context, current-mode filters employing voltage companding techniques are receiving much interest due to their suitability for achieving a large dynamic range in a low voltage environment, thanks to their internally nonlinear voltage compression [1– 12]. Several promising topologies have been reported using BJT and/or MOS transistors, being differential log-domain filters where such benefits are achieved at a larger extent [13–16]. An interesting alternative, particularly for very low voltage applications, is the use of Floating-Gate MOS (FGMOS) transistors [17], both in log-domain [18, 19] and square-root domain [20] companding filter implementations. This paper presents a novel first-order log-domain filter based on FGMOS transistors in weak inversion. A very low supply voltage is obtained by implementing such filter using FGMOS transistors, that allow the reduction of their “effective” threshold voltage via ca-
pacitive voltage division when they are properly biased. Moreover, such FGMOS transistors are operated in weak inversion, so that the Translinear principle [21] can be employed for implementing the filter, leading to a compact implementation based on a novel fourtransistor multiplier/divider. In addition, the resulting power consumption is very low due to the low currents involved in this device operating mode. A class AB fully-differential topology has been implemented, thus further extending the input range and strongly reducing even-order distortion.
2.
Floating-Gate MOS Transistor
The n-input Floating Gate MOS (FGMOS) transistor is characterized by the fact that the gate electrode which extends over the channel is left floating; an array of n control gates are formed over this electrode using a second polysilicon layer [17]. Figure 1 shows a simplified layout of a three-input Floating Gate NMOS transistor, as well as its symbol. The n-input FGMOS transistor equivalent circuit is shown in Fig. 2, where the capacitive coupling between the n input gates and the floating gate is illustrated. Since the total charge at the floating gate must be
138
L´opez-Mart´ın et al.
Fig. 2. Fig. 1.
(a) Layout of 3-input FGMOS transistor and (b) Symbol.
3. conserved, the floating gate voltage will be given by [17]: n Ck Vk + CGS VS + CGD VD + CGB VB VFG = k=1 CT (1) where the total capacitance C T can be approximated by CT =
FGMOS equivalent circuit.
n
Ck + CGS + CGD + CGB ≈
k=1
n
Ck
Filter Design
Let’s assume that we want to implement a first-order low-pass filter having transfer function H (s) =
Iout (s) K = Iin (s) 1+τs
(5)
K being the DC gain and ω−3dB = 1/τ . As an alternative, (5) can be rewritten in the time domain as τ I˙out + Iout = KI in
(2)
(6)
k=1
if input capacitances are chosen such that their sum is much larger than the parasitic capacitances, i.e., n
Ck CGS , CGD , CGB
Therefore, the floating gate voltage VFG is a weighted sum of the Vk input voltages (being the k-th weighting factor equal to the capacitance ratio Ck /C T ) plus some additional terms originated from the contribution of parasitic capacitances. Assuming that the FGMOS transistor is operating in weak inversion and saturation, its drain current shall be given by nVGS Id = I0 · exp UT
= I0 · exp
Iout = I B eαVcap
(3)
k=1
i.e., a linear differential equation. Assuming that the output current Iout is nonlinearly related to a certain voltage Vcap by
n·
CGD CT
· VD +
where I0 is a constant current dependent on transistor geometry and technology, n is the slope factor and UT = kT /q is the thermal voltage. If the Vk input voltages and capacitance ratios are properly chosen, the required VGS can be obtained by using lower supply voltages without compromising the input range.
(7)
I B and α being constants (with dimensions A and V−1 , respectively), and assuming that τ = C/g (C and g being capacitance and transconductance values, respectively), Eq. (6) results in α Iout C · V˙ cap · + Iout = K · Iin g
CGS CT
· VS +
CGB CT
UT
· VB +
n
Ck k=1 C T
· Vk − VS
(8)
(4)
Constants K and g determine the DC gain and cutoff frequency (once C set), respectively. We can replace them by two constants with dimensions of current, which will lead to bias currents able to tune the frequency and DC gain of the filter: Kg g I B1 = I B2 = (9) α α
A 1 V Micropower FGMOS Class AB Log-Domain Filter
Using (9) in (8) and rearranging,
From Fig. 3, and using (3)–(4), I4 can be expressed as n
C · V˙ cap
I B1 · Iin = − I B2 Iout
I4 ≈ I0 e UT
(10)
= I0 e
n UT n
= Io e UT
Equation (10) describes a low-pass filter whose DC gain and cutoff frequency are given by K =
4.
I B1 I B2
ω−3dB =
139
α I B2 C
n
= Io
Identifying (7) and (4) with I B = I0 and α = n/U T , a possible implementation of (10) results, where the filter output current Iout is the drain current of a MOS transistor in weak inversion and saturation whose gateto-source voltage VGS is the capacitance voltage Vcap that results from injecting into the capacitor C a current nonlinearly related to the input and output currents (first term in the RHS of (10)) minus a bias current (second term in the RHS of (10)). It should be noted that these equations are nothing but a particular case of the general method presented in [12] by the authors, which allows the extension of the synthesis method to higherorder filters. Note also from (11) and the value of α that like in all log-domain filters the cutoff frequency is temperature-dependent. Such dependence would be ideally eliminated generating a bias current I B2 proportional to absolute temperature (PTAT). The current multiplier/divider required in (10) can be efficiently implemented by using Translinear loops of FGMOS transistors. The circuit that we propose is shown in Fig. 3, where four 2-input FGMOS transistors with identical capacitance ratios (C1 /C T = C2 /C T = 0.5) and operating in weak inversion are employed.
e UT
I1 · I2 = I3
(11)
Class A Filter Implementation
Vd1 2
+V
Vd1 2
+
Vd2 2
Vd1 2
+
Vd3 2
Vd1 2
+
Vd3 2
d2 2
+
e
Vd3 2
+
n
e UT
n
e UT nVd3 UT
Vd3 2
−Vd3
Vd2 2
+
Vd3 2
Vd2 2
+
Vd3 2
e
−
nVd3 UT
·
Io Io
(12)
Therefore, the required current multiplier/divider operator is obtained. A direct implementation of (10) using the proposed multiplier/divider is shown in Fig. 4(a). An alternative class A log-domain filter implementation of the transfer function (5) was devised in [19], using the so-called Multiple-Input Translinear Element (MITE). Such element produces an output current that is exponential in a weighted sum of its input voltages, so that a particular instance is the FGMOS transistor shown in Fig. 1. The method proposed in [19] allows the class A implementation of (5) without an explicit multiplier/divider circuit, but four FGMOS transistors are still required. However, the two additional NMOS transistors shown in Fig. 4(a) are not needed in [19], but a reference bias voltage is required instead. 5.
Class AB Differential Filter Implementation
A more practical realization can be obtained by duplicating the circuit and adding redundant terms as done in [13], leading to a class AB differential filter featuring an improved dynamic range. In order to obtain a class AB differential log-domain implementation of the first-order LPF transfer function (5), and proceeding similarly to the class A case of Section 3, (5) can be alternatively rewritten in the time domain as τ ( I˙out+ − I˙out− ) + (Iout+ − Iout− ) = K (Iin+ − Iin− ) (13) where K and τ have the same meaning as in (6), Iout+ − Iout− is the differential output current and Iin+ − Iin− is the differential input current. Equation (13) can be split in the following equations:
Fig. 3.
FGMOS multiplier/divider.
τ I˙out+ + Iout+ − f (I ) = K Iin+ τ I˙out− + Iout− − f (I ) = K Iin−
(14a) (14b)
140
L´opez-Mart´ın et al.
Fig. 4. FGMOS log-domain filter (a) single-ended and (b) differential class AB.
Note that (13) can be obtained by subtracting (14a) and (14b). The nonlinear function f (I ) cancels in such subtraction, and therefore does not affect the differential transfer function. This function f (I ) is introduced to keep the MOS transistors forward-biased [14]. In order to obtain a class AB operation, all the input and output currents in (14a)–(14b) should be positive, and the input currents can be chosen in such a way that their ge2 ometric mean remains constant, i.e., Iin+ · Iin− = Iconst . Concerning current f (I ), it should be strictly negative. Several approaches for f (I )have been proposed [14], but a convenient strategy which leads to simple topologies and low power consumption is f (I ) = −m Iout+ · Iout−
(15)
m being a constant with units of A−1 . Substituting (15) in (14a)–(14b) and using the same procedure than for the class A log-domain filter in Section 3, the class AB log-domain filter equations can be obtained. Thus, assuming that the output currents Iout+ and Iout− are nonlinearly related to capacitance voltages Vcap+ and
Vcap− by Iout+ = I B eαVcap+
Iout− = I B eαVcap−
(16)
I B , α, and τ = C/g being as in Section 3, and choosing m = α/g, substituting in (14a)–(14b) and rearranging, the following equations result, Iin+ · I B1 Iout+ Iin− · I B1 = Iout−
Icap+ + I B2 + Iout− =
(17a)
Icap− + I B2 + Iout+
(17b)
where capacitor currents are Icap+ = C V˙ cap+ and Icap− = C V˙ cap− . Bias currents I B1 and I B2 are defined as in (9). These equations can be implemented with the circuit shown in Fig. 4(b). Due to its differential class AB operation, currents can be driven well beyond their quiescent levels while preserving linearity, and commonmode currents are rejected. The log-domain filter can be readily cascaded, leading to higher-order structures.
A 1 V Micropower FGMOS Class AB Log-Domain Filter
Fig. 5.
6.
141
Complete schematic.
Simulation Results
The complete schematic of the filter is shown in Fig. 5, where the multiplier/dividers described in Section 4 have been employed. The circuit was simulated using BSIM3v3 models for a 0.8 µ DPDM CMOS technology. Supply voltage was 1 V, and 150 pF capacitances were chosen. FGMOS input capacitances were 1 pF. The MOS aspect ratios employed are shown in Table 1. The frequency response of the filter for bias currents I B1 = I B2 ranging from 50 to 600 nA was evaluated using a small-signal AC analysis. An independent frequency tuning over more than a decade was observed, from approximately 1.2 to 19 kHz. The time response of the circuit was subsequently evaluated, using 50 nA bias currents. The differential input current employed was a 100 Hz sinusoid with a peak-to-peak amplitude ranging from 1 to 240 nA. Figure 6 shows the THD obtained in the output waveform as a function of the peak-to-peak input current amplitude, normalized to its maximum value (240 nA). Table 1.
Fig. 6.
THD vs. normalized input amplitude.
It can be noticed how for input current swings as large as 240 nA (4.8 times the bias current) distortion is still low (
