A CMOS analog-digital audio processor for a portable radiotelephone

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 5, MAY 1993

A CMOS Analog-Digital Audio Processor for a Portable Radiotelephone J. Guilherme, Student Member, IEEE, F. P. Martins, Joao C. Vital, Student Member, IEEE, and JosC E. Franca, Senior Member, IEEE

Abstruct- This paper describes a mixed analog-digital integrated circuit specifically designed to realize the audio processing functions needed for a portable radiotelephone (PRT) application. Multirate signal processing techniques are used to reduce the capacitance spread, and hence the overall silicon area of the chip, as well as to minimize the settling requirements of the amplifiers for lower power consumption. This, together with a programmable power-saving control circuitry also incorporated on-chip, considerably extends the lifetime of the battery. A semicustom design methodology is employed to implement such an application-specific integrated circuit (ASIC) in a 3-~rmCMOS double-poly processing technology. Experimental results are presented to demonstrate the correct operation and functionality of the prototype chips.

I. INTRODUCTION

A

UDIO processing application-specific integrated circuits (ASIC’s) for portable radiotelephones (PRT’s) have to meet stringent specifications in comparison to their line-fed counterparts, namely with respect to the low power consumption which is essential to save the lifetime of the battery, and the large dynamic range that is necessary to maintain a good signal-to-noise ratio in a noisy environment [ 11-[3]. Such ASIC’s are usually required to realize voice-band filtering, subaudio tone generation, output signal amplification, and buffering, and also to incorporate a programmable powersaving control circuitry to extend their operating lifetime. Those functions are implemented using a combination of both analog and digital circuit techniques that can be implemented on the same CMOS silicon chip. The exact partitioning between such analog and digital circuit solutions must be carefully defined and efficiently tailored to the specific application and corresponding specifications in order to reduce the silicon area and power consumption, and even minimize the number of external components that might be necessary to support the full operation of the circuit. In this paper we describe the design of a mixed analog-digital ASIC suitable for the audio processing unit of a portable radiotelephone. After this introductory section, we present in Section I1 an overview of the overall architecture and functional building blocks of the ASIC as well as a brief Manuscript received July 21, 1992; revised January 1 1 , 1993. J. Guilheme, J. C. Vital, and J. E. Franca are with the Integrated Circuits and Systems Group, Department of Electrical and Computer Engineering, Instituto Superior Tecnico, 1096 Lisboa Codex, Portugal. F. P. Martins is with Dep6sito Geral de Material de Transmissnes, 2795 Linda-a-Velha Lisboa Codex, Portugal. IEEE Log Number 92081 15.

discussion of the semi-custom design methodology which was adopted to realize it in integrated circuit form using a 3-pm CMOS double-poly processing technology. Then, in Sections 111 through V, we describe in more detail the design and experimental results obtained for each one of such functional building blocks. Section I11 concems the building blocks for the implementation of the audioband signal processing functions, including a speech channel decimating filter and a three-input adder and interpolating filter. Section IV describes a mixed-signal analog-digital waveshaping network for the generation of a subaudio signaling tone, and Section V presents another mixed-signal analog4igital circuit solution for implementing a programmable power-saving control network where the period of the generated ON-OFF waveform can be as long as a few seconds. Section VI summarizes and concludes the paper. 11. ASIC ARCHITECTURE AND DESIGN METHODOLOGY

A . Architecture The ASIC described in this paper has been designed for high-frequency (HF) PRT, and performs all the basic audio processing functions indicated in the block diagram of Fig. 1. Under the control of an external microprocessor, the ASIC operates in half-duplex mode. When the system is in the receive mode, the input signal AR, coming from the frequency modulator (FM) detector goes through the channel filter and preamplifier, whose gain can be controlled by the digital inputs VM and VH, and then follows on to a loudspeaker through an external power amplifier. Alternatively, the signal can also go to the output AUSC, which connects to a hearphone via a low-power driver. The input GA controls the squelch of the system via an external circuit. In the transmit mode, the input signal MiclAltif coming from the microphone goes through an external automatic gain control circuit and then is directed through the channel filter and the three-input adder and interpolating filter to the FM modulator input. In this operating mode, the signal conveyed to the FM modulator input combines the microphone signal, a 150-Hz subaudio signaling tone, and the signal at the input X M T , , which can be, for example, transmitted data from a modem. In Order to reduce power consumption* the incorporates a power-saving control network realized as a lowfrequency voltage-controlled oscillator (VCO) with a digital output, and through which we can control the ON-OFF waveform period and duty cycle by means of the input signals VRI

00 I8-9200/93$03.OO 0 1993 IEEE

GUILHERME er al.: CMOS ANALOG-DIGITAL AUDIO PROCESSOR FOR RADIOTELEPHONE

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.............................................................................. System Specifications

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Prototype Testing Fig. 2.

Illustration of the methodology adopted for designing the PRT ASIC

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Fig. 1.

Block diagram of the specific audio processor IC for a portable radiotelephone.

and VR2. The information produced at the output stage of this oscillator is conveyed to the external microprocessor unit to place the system in the standby mode via the power-down input. In standby, only the power-saving control network, some glue logic, and the reference crystal oscillator are ON, while the remaining circuitry is OFF. Finally, a simple Schmitt trigger circuit is included to monitor the state of the battery.

B. Design Methodology The framework established for the development of this ASIC led us to adopt the semi-custom design methodology schematically illustrated in Fig. 2. For each one of the functional blocks described before, we developed first the corresponding high-level architecture solution whose functionality is verified using commonly available simulators (e.g.. Switcap I1 [4], Fideldo [ 5 ] ) where the basic circuit components are initially represented by ideal functional macromodels. Once the high-level architecture solution is defined, we carry out a computer-based evaluation procedure whereby real values are assigned to the high-level parameters of those macromodels, e.g., finite dc gain and bandwidth of the amplifiers, and which leads to determining the worst-case values such parameters should take to obtain deviations of the nominal responses within the specified limits. Then, from the manufacturer’s cell

Fig. 3 .

Photomicrograph of the CMOS semi-custom ASIC for a portdbk radiotelephone.

library [6] we fetch the circuit components, both analog and digital, which best match those specifications and insert them into the circuit using an appropriate schematic capture tool. Then, by employing placement and routing tools jointly with judicious techniques for minimum coupling of digital noise onto analog signal lines, we generate the complete layout of the chip. This is finally transferred to the manufacturer where appropriate electrical and design-rule checkings are carried out. The complete mixed analog-digital integrated circuit could not be fully and extensively simulated at the low electrical level, owing to the complexity arising from the combination of continuous-time and multirate analog and digital signals. However, the adopted design methodology combining correct and functionally verified full-custom architecture solutions for the functional building blocks together with correct and electrically verified components fetched from the manufacturer’s

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 5, MAY 1993

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TABLE I RELEVANT CHARACTERISTICS

OF THE

ENTIRE IC

Technology

3 pm CMOS

Power supply

f5V

Power consumption :

-w

-m

5.5 mW 38 mW

Voltage supply rejection ratio (in band) :

- Maxir" -Mink"

45 dB 22 dB

Maximum output voilage swing

0.2 vpp

Dynamic range

>73 dB

Sinal - lo - noise ratio

>50 dB

Active area

6.75 mm2

Passbandoffset voltage