Microelectronics Journal 29 (1998) 277-281 © 1998 Published by Elsevier Science Limited Printed in Great Britain. All rights reserved 0026-2692/98/$19.00
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A compact temperature sensor for a 1.0/ m CMOS technology using lateral p-n-p transistors Enric Montan~, Sebastian A. Bota* and Joselp Samitier Enginyeria i Materials ElectrOnics,Facultatde Fisica, Universitatde Barcelona, Avinguda Diagonal 645-647, 08028 Barcelona Spain
A compact temperature sensor using lateral p-n-p bipolar transistors has been fabricated and tested in a standard 1.0#m digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p devices exhibit good lateral /3. The accuracy of the temperature sensor is close to the performances obtained in bipolar technology, an output proportional to absolute temperature is obtained (0.54mV/K) from 0 to +70°C, although the sensor can be used in wide-ranging applications after curvature correction. The device has an area of only 0.018mm 2. © 1998 Published by Elsevier Science Ltd. All fights reserved. 1. Introduction
I
C temperature sensors made in bipolar (or B i C M O S ) t e c h n o l o g y are used extensively.
*Author to whom correspondence should be addressed. Tel: 34-3-402 90 68. Fax: 34-3-402 11 48. E-mail:
[email protected].
But, because C M O S is the m o s t extensively used technology, the integration o f temperature sensors m standard high performance digital C M O S processes is also desirable. T h e advantage o f IC sensors is that signal conditioning can be p e r f o r m e d o n the same chip, so that temperature can be measured and the o u t p u t used directly by another electronic system [1]. Desirable features o f the sensor element include temperature sensitivity, linearity, longterm stability and relative i n d e p e n d e n c e o f variation in process technology. M o s t standard c o m p o n e n t s available in C M O S t e c h n o l o g y fail to satisfy all these criteria. For example, M O S transistors have p o o r l o n g - t e r m stability and are impractical for wide-ranging temperature measurements [2], and resistors behave in
277
E. Montan6 et al./Compact temperature sensor
a non-linear way with temperature. A better approach lies in using bipolar devices that can be made with existing CMOS technology [3, 41. 2. Lateral p-n-p transistors
The schematic shown in Fig. 1 is a CMOScompatible lateral bipolar transistor. The structure (Fig. 2) is an annular MOS transistor, which is operated in the bipolar mode with a gate voltage negative enough to prevent the formation of a surface channel. It is reported that the temperature behaviour of the lateral bipolar transistor is the same as for the vertical one fabricated in bipolar technology [4].
Gate Base
(
Emitter
Collector
Fig. 1. Diagram of the lateral p-n-p transistor.
I
I
Lateral bipolar n-p-n transistors, LNPN, have been successfully fabricated in p-well CMOS processes, but modem high-performance digital CMOS processes generally use n-well diffusions in a p-type substrate to maximize the performance of the faster N M O S transistors. Only lateral p-n-p transistors, LPNP, can be constructed in a standard digital n-well technology. Since integrated p-n-p transistors usually have lower forward current gain, r, than n-p-n transistors, an initial question was whether LPNP transistors would have sufficiently good fl to be used in the construction of a temperature sensor. An LPNP transistor is formed by creating a rectangular PFET structure in which a p-diffusion emitter is surrounded by a p-diffusion lateral collector. The n-well serves as the base, and the minimum polysilicon gate length sets the base width. To reduce the unavoidable parasitic vertical collector current, these transistors were laid out as multiemitter devices [3]. This technique maximizes the ratio of lateral collector current to vertical parasitic collector current and improves the lateral collector current efficiency and noise characteristics of the transistor [5]. For proper bipolar operation, the polysilicon gate of the LPNP transistor must be zero-biased with respect to the emitter to prevent the PFET transistor between the collector (drain) and emitter (source) from turning on.
I
N-WELL
(A)
Figure 3 shows results for lateral fl for an LPNP transistor. As is shown, the LPNP transistor operated over more than two decades of collector current with a minimum lateral/3 of 20. 3. The temperature sensor circuit
Fig. 2. (a) Cross-section of a minimum-size concentric LPNP. (b) Layout.
278
Given sensor 1.0#m circuit
the LPNP transistor, a temperature was fabricated and tested in the ES2 n-well CMOS process. The sensor design is based on a straightforward
Microelectronics Journal, Vol. 29, Nos 4-5
35.0
VG 30.0
Q1
Q2
25.0 ¢D
rn
R1
20.0
l
15.0 "
M1
10.0
=
i
=1===
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i
g
= i=ll|
1.0E-5
1.0E-6
I
=
i
1.0E-.4
i
hi.i,
M2
J
Fig. 3. 3 versus Ic for the LPNP transistor. topology adapted from a previous design [4, 6], in which the original n - p - n transistors are replaced with multiple dot L P N P transistors (Fig. 4). T h e circuit was designed for a voltage supply o f 5 V. Basically, the circuit is formed by two L P N P transistors and a current mirror. If base current can be neglected, the collector currents o f QI and Q2 are given by Icl = NIs eq~l
(1)
qVEB2
Ic2 = MIs e kr
N I
M4
$
1
Fig. 4. Schematic of the temperature sensor. the current mirror. T h e current mirror formed by the n-channel M O S transistors M1, M2 and M3, M 4 forces Ic1=Ic2=I, which give S:
I = qR1
T h e sizes of n-channel transistors were adjusted to ensure that L P N P transistors were working in their m a x i m u m fl region (Table 1).
(2)
where T is the absoliute temperature, q is the electric charge and k Boltzmann's constant. Then, = ~ r c2
M6
1.0E-3
Ic (A)
Icl
I
e~ B
N I
=
~
qlclR1
c2 e kT
(3)
As with their L N P N predecessors, L P N P transistors suffer from low Early voltages (typically 16V), so some type o f cascode topology may be desirable to increase output resistance in
TABLE 1 Transistor MOS transistors M1 M2 M3 M4 M5 M6 LPNP transistors
(W/L) (#m)
100/2 100/2 100/2 100/2 100/2 100/2 M=I, N=8
279
E. Montand et al./Compact temperature sensor
Fig. 5. Photomicrographof the sensor. A second current mirror formed by transistors M5 and M6 was used to induce an output current proportional to absolute temperature (PTAT current). A modified version of this design, containing a second on-chip resistance, R2, was also implemented. In this case, the P T A T output bias is not degraded by any temperature dependence of the resistances if R1 and R2 have the same temperature behaviour. It is important to note that eq. (4) is independent of LPNP device parameters. Highly reproducible characteristics of these system are reported for L N P N transistors, in agreement with known theories predicting slight non-linear variations [7]. Figure 5 corresponds to a photomicrograph of the sensor. The total area is about 0.018 m m 2. To calibrate the sensor, the circuit response was compared with a platinum R T D temperature sensor located at very similar environmental conditions. Measurements on the temperature sensor are shown in Fig. 6. The P T A T output voltage Vout, corresponding to the design version with two on-chip resistances, is
280
V
out
Cv')
-0.13
-0.14
\\ -0.15
-0.16
280
i
i
i
I
I
290
300
310
320
330
T E M P ¥ . R A TIIR E
340
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Fig. 6. PTAT voltage output. reported as a function of temperature. This plot shows a linear response of the sensor from 0 to +70°C, and the P T A T coeflacient is - 0 . 5 4 m V / K (for N=8 and R2=2R1). The total current is about 0.15 mA. These results are in agreement with the expected values. This circuit is also useful for high-precision, wide-ranging temperature measurement if
Microelectronics Journal, Vol. 29, Nos 4-5
V~3Enon-linearities are c o m p e n s a t e d . C u r v a t u r e c o r r e c t i o n can be simple in a digital a p p r o a c h [6,7]. 4. Conclusions Provided current densities are kept low, LPNP bipolar transistors fabricated in the ES2 ECPD10 n-well CMOS technology exhibit good characteristics. The experimental results demonstrate that a compact sensor can be readily constructed in a standard digital n-well CMOS process using LPNP transistors obtaining small area circuits (0.018 mm2). Many potential applications are foreseen for this sensor block in application-specific integrated circuits.
Acknowledgements This work was supported by Spanish projects CICYT TAP 94-1047 and TIC 95-1708-CE.
References [1] Krummenacher, P. and Oguey, H. Smart temperature sensor in CMOS technology, Sensors and Actuators, A21-A23 (1990) 636-638. [2] Zhu, J.Y., Rasmussen, W., Richard, S. and Cheeke, D. Ultrastable integrated CMOS oscillator, Int. J. Electron., 70 (1991) 433-441. [3] Holmann, W.T. and Connelly, J.A. A compact low noise operational amplifier for a 1.2/lm digital CMOS technology, IEEEJ. Solid-State Circuits, SC-30 (1995) 710-714. [4] Vittoz, E.A. MOS transistors operated in the lateral bipolar mode and their application in CMOS technology, IEEE J. Solid-State Circuits, SC-18 (1983) 263-279. [5] Pan, T.W. and Abidi, A.A. A 50-db variable gain amplifier using parasitic bipolar transistors in CMOS, IEEE J. Solid-State Circuits, SC-24 (1989) 951-961. [6] Ristic, L. (ed.), Sensor Technology and Devices, Artech House, Boston, 1994, pp. 287-315. [7] Tsividis, Y.P. Accurate analysis of temperature effects in Ic--VBE characteristics with application to bandgap reference sources, IEEEJ. Solid-State Circuits, SC-15 (1980) 1076-1084.
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