A DTMOS–BASED 1 V OPAMP H. F. Achigui, C. J.–B. Fayomi, M. Sawan PolyStim Neurotechnology Laboratory Electrical Engineering Dept., Ecole Polytechnique de Montreal E-mail: {herve.achigui-facpong, mohamad.sawan} @polymtl.ca;
[email protected] ABSTRACT In this paper, we present a new opamp based on dynamic threshold voltage (DTMOS) transistors for low voltage applications (1–V). The opamp is a two stages configuration, with differential input pairs followed by a single ended class AB output. The input stage uses DTMOS devices for input common-mode range enhancement. The performed simulation shows a dc open loop gain of 64.4 dB, a phase margin of 64o and unity gain frequency of 35.7 MHz under a 10 KΩ and 5 pF load, using the 0.18 µm CMOS technology. The opamp has a CMRR of 84 dB, input and output swings of 0.7 V and 0.9 V respectively. Index terms – DTMOS, CMOS analog integrated circuit, low voltage operational amplifier, differential amplifier.
1. INTRODUCTION
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ESIGN OF ANALOG IC’s operating at low voltages with high performance features has been gaining more and more importance during last decay, especially for applications such as medical electronic implants devices, portable and battery powered electronic devices. Communication large–scale integrations are predicted to target 1–V operation, and even less. However, the trends towards lowering the power supply voltage of circuitries in mixed-signal (digital/analog) signal environment often sacrifices their analogues counterpart in terms of speed, noise requirements and linearity. This poses a great challenge to CMOS mixed-signal circuits design. Reduction of threshold voltage is necessary for low voltage operation; on the other hand, the threshold voltage does not scale down with supply voltage of future standard CMOS technologies [1]. An obvious solution could be the use of multi-process threshold technology, but unfortunately, this kind of technology is more expensive and frequently not easy to reproduce. Some design advantages could be obtained by using BiCMOS technology, but at the expense of additional cost. Several design techniques have been
proposed for realization of 1–V operational amplifier. In [2] the authors presented a design technique for facilitating 1–V operation based on bulk-driving architecture. However, substantially small input transconductance (gm) is obtained compared to a conventional gate-driven MOS transistor and furthermore, the equivalent input referred noise is larger. Other rail-to-rail design techniques are presented in [3]–[5] using standard CMOS technology process. In [3], the authors used a level shifter, based on switched capacitors to provide the required dynamic bias voltage to the PMOS input transistors pairs, which is quite tremendous and tedious, even if it is suitable for switched capacitors applications. The major problem with other architectures in [4]–[5], based on the use of N-P complementary rail-to-rail input stage is the increase of the total harmonic distortion (THD) due to the dependence of the input offset voltage on the common mode input voltage swing. Since the first introduction of dynamic threshold voltage MOSFET (DTMOS) in 1994 [6], many novel interesting proposal circuits operating at low supply voltage have been made [7] and most of them achieved low threshold voltage by modifying the fabrication process, using the SOI technology. In this paper, a new class AB opamp is proposed for low-voltage applications. The circuit makes use of the DTMOS folded cascode differential input pair to increase the input common mode range (ICMR). Standard Miller compensation is used for bandwidth enhancement as illustrated in Figure 1. Following this introduction, section 2 focuses on the description of the opamp architecture with a focus on the DTMOS transistor. Section 3 is related to preliminary results and we conclude with section 4. 2. LOW-VOLTAGE DTMOS BASED OPAMP The proposed implementation includes a differential input stage and a class AB output stage capable of driving off chip resistive load. Biasing circuit consists of standard current source using a resistance and a NMOS transistor. A wide swing current mirror with high output impedance, is used to produce bias voltages VBP and VBN as presented in Figure 2 and Figure 3.
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2.1. DTMOS Transistor 3. INPUT STAGE DESIGN In CMOS digital circuit, the delivered power is proportional to the square of power supply voltage, as shown by equation (1) P = CLVdd2 f (1) where P is the power consumed by one gate, CL the total load capacitance of the gate, Vdd the power supply voltage, and f the average operating frequency of the gate. Therefore, an effective method for reducing power consumption is to reduce the power supply voltage (Vdd). That is one of the reasons behind the technology scaling. In other words, technology scaling is driven by digital circuit requirement. A limitation to implementing digital and/or analog circuits at low voltage is the threshold voltage (Vth). One possible solution is to implement CMOS transistors with dynamic Vth, which is the basic idea behind DTMOS. The body and the gate are biased at the same potential. When the gate voltage is high, the front channel of the device is turned on. Then, the body potential becomes high too, due to the body-tied-to-gate structure. Due to the body effect, the threshold voltage becomes low and thus the driving capability of the front channel increases. When the gate voltage becomes low, the front channel turns off. Since the body voltage also becomes low, via the body effect, the threshold voltage of the front channel is recovered, thus the leakage current is small. As the gate and body voltage increase, the threshold voltage reduces. Moreover, this could be expressed with equation (2), which present the threshold voltage Vth as a function of the bulk source voltage VBS
Vth = Vth 0 + λ
(
2Φ F − VBS −
2Φ F
)
The input stage is shown in Figure 2. Typically PMOS threshold voltage is around –0.7 V, which is much large than NMOS threshold voltage. Consequently, to achieve 1-V operation or less, we used PMOS based DTMOS transistors pairs (M1, M2) in the differential input. Hence, this enables us to take advantage of the maximum input range, while having all transistors operating in the strong inversion region. The proposed input stage also used a folded cascode wide swing current mirror MN1–MN4. Transistors M1B, M3B (M2B, M4B) are designed to provide adequate bias voltage to MN3 (MN4) respectively. In fact, they implement the gain boosting technique as described in [9] for high dc gain enhancement. Transistors MPS1 and MPS2 have been added to enhance the slew-rate limitation of the folded cascode configuration. When the operational amplifier is slew-rate limited, these transistors prevent the drain of MN1 and MN2 from having large transients that change their small signal voltages to level close to the positive power-supply voltage. DTMOS transistors MP1–MP3 provide the required bias current for the differential input transistors and for the cascode current mirror.
(2)
where Vth0 is the zero bias threshold voltage, λ the bulk effect factor and ΦF the Fermi potential. For p-channel transistors, 2ΦF ≈ –0 .7 V, λ ≈ –0.5 V , and typically Vth0 ≈ –0.6 V, and a bulk bias voltage VBS is normally > 0 V, which increases the threshold voltage. However, by biasing VBS < 0 V we can actually decrease numerically the threshold voltage [8]. Even if some measurements and modeling of DTMOS devices were done with the SOI technology, they are still valid for the standard CMOS technology. It should also be mentioned that no extra area is needed for the DTMOS devices. In our design, we achieve an average threshold voltage of –0.35 V for PMOS based DTMOS transistors.
Figure 2. Low Voltage DTMOS pMOS input stage.
3.1. Class AB Output Stage The output stage is a key point in the design of low-voltage amplifiers since it greatly affects the final features of the amplifier itself. The low-voltage class AB output stage that we used is similar to the design reported in [10] and is shown in Figure 3. The signal is splited to the output by the output transistors MOA, MOF and current mirrors M0E–M0D, and M0C–M0B, which provide a low impedance signal path to the output. Quiescent current control is based on the current comparison performed at the drain of MP01.
Figure 1. Low-voltage DTMOS opamp block scheme.
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Figure 3. Class AB low-voltage output.
(a) Simulated opamp input common-mode range (ICMR).
4. PRELIMINARY RESULTS The proposed implementation has been simulated with Cadence using Spectre in a 0.18 µm CMOS standard technology. Nominal values for the threshold voltage are approximately 0.5 V and –0.6 V for NMOS and PMOS transistors respectively. 4.1. Input/Output Swing Measurement An important issue about the DTMOS device is the input impedance. There is a current path from the gate to the substrate. Compared to its counterpart standard PMOS based input differential pairs, the input impedance is not infinite. Plot in Figure 4 is the input impedance versus common mode (CM) signal. This has to be taken into account when using a DTMOS based opamp. From Figure 4, we can see that for very low input voltage, the input impedance could be less than 100 KΩ, however it can reach values higher than 1 MΩ for input CM.
(b) Simulated opamp output voltage swing (SWG).
Figure 5. Characterization of the DTMOS opamp.
4.2. Frequency Response, CMRR and PSRR The frequency response presented in Figure 6(a) and Figure 6(b) gives the open loop gain and the phase of the proposed opamp respectively. The preliminary results obtained show a dc open loop gain of 64.4 dB, a phase margin of 64o, and a unity gain frequency of 35.7 MHz. The opamp has a common mode rejection ration (CMRR) of 84 dB. The positive and negative power supply rejection ratios (PSRR+) of 56 dB and (PSRR –) of 34.8 dB are achieved.
(a) Simulated opamp open loop gain.
Figure 4. Simulated opamp input impedance.
The input common mode range voltage (ICMR) of the opamp has been simulated using a unity gain configuration. The obtained result is shown in Figure 5(a). The linear input range is limited to almost 0.7 V. It should be noted that large leakage current is generated for ICMR larger than 0.7 V [7]. Output swing simulation is performed in a non-inverting configuration using a gain of 10 V/V, in order to avoid limitation of the linearity of the transfer curve due to the ICMR, and it is shown in Figure 5(b). A fully railto-rail output swing is obtained which confirm the class AB operation.
(b) Simulated opamp phase. Figure 6. Opamp frequency response.
4.3. Step Input Response The opamp step input response of the proposed opamp is shown in Figure 7(a), also Figure 7(b) depicts the opamp response to 0.7 VPP sinusoid input signal.
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MHz unity gain frequency and a 64o phase margin with a load condition of 5 pF and 10 kΩ. The circuit dissipates 522 µW. The overall circuit layout is in progress. Applications of the circuit should extend from sample-data systems to switched-capacitor filters and data converters, to name just a few examples. ACKNOWLEDGEMENTS
(a) Opamp step input response.
(b) Opamp sine response.
Figure 7. Opamp transient simulation.
4.4. Harmonic Distortion Analysis With the use of a class AB output stage, it is important to outline how far the proposed opamp can faithfully reproduce the signal applied at its input. Evaluation of the mis-shaped between the fundamental frequency at the input and the one at the output is done by calculating the harmonic and inter-modulation distortion level between coherent sample data. This computation is done using a coherency testing method. A 1024-point over 10.24 ms (1024/100 KHz) time period were collected, using a sampling frequency of 100 KHz with an input sinusoidal signal frequency of 4.0039625 KHz, and an amplitude of 0.7 VP–P. An FFT analysis was performed and the power spectral density of the opamp output signal is shown in Figure 8. The signal–to–noise–and–distortion ratio (SNDR) is measured to be 32.75 dB.
The authors would like to express their thanks to the “Natural Sciences and Engineering Research Council” (NSERC) of Canada and the “Le Fonds québécois de la recherche sur la Nature et les Technologies” (NATEQ), for their support during this project, as well as the “Canadian Microelectronics Corporation” (CMC) for providing the CAD tools. REFERENCES [1]
Hu C., “Future CMOS Scaling and reliability,” Proc. IEEE, vol. 81, pp. 682-689, May 1993. [2] Blalock, B.J.; Allen, P.E.; Rincon-Mora, G.A., “Designing 1-V op amps using standard digital CMOS technology,” Proc. IEEE Int. Symp. Circuit Syst. vol 45, Jul 1998, pp. 769-780. [3] Fayomi, C.J.B.; Roberts, G.W.; Sawan, M. “A design strategy for a 1-V rail-to-rail input/output CMOS opamp”, Proc. IEEE Int. Symp. Circuit Syst, vol. 1, May 2001, pp.460-463. [4] Bahmani, F.; Fakhraie, S.M.; Khakifirooz, A., “A rail-torail, constant-Gm, 1-volt CMOS opamp,” IEEE Trans. CAS part I, vol. 2, 2000, pp. 669 -672. [5] Duque-Carrillo, J.F.; Ausin, J.L.; Torelli, G.; Valverde, J.M.; Deminguez, M.A., “1-V rail-to-rail operational amplifiers in standard CMOS technology”, IEEE J SolidState Circuits, vol. 35, Jan 2000, pp. 33-44. [6] Assaderaghi, F.; Sinitsky, D.; Parke, S.; Bokor, J.; Ko, P.K.; Chenming Hu., “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,” IEDM Trans, vol. 44 Mar 1997, pp. 414-422. [7] James. B. Kuo and Shih-Chia Lin. “Low-Voltage SOI CMOS VLSI Devices and circuits,” Wiley & Sons 2001. [8] Lehmann T and Cassia M “1-V Power Supply CMOS Cascode Amplifier”, IEEE J Solid-State Circuits, vol. 36, Jul 2000, pp. 1082-1086. [9] Bult, K.; Geelen, G., “A fast settling CMOS Op Amp for SC Circuits with 90 dB DC gain,” IEEE J Solid-State Circuits, vol. 25, Dec 1990, pp. 1379 -1384. [10] Silveira, F.; Flandre, D., “Analysis and design of a family of low-power class AB operational amplifiers,” Proc. IEEE Int. Symp. Circuit Syst, 2000, pp. 94 -9.8
Figure 8. Simulated opamp output spectrum.
5. CONCLUSION A new operational amplifier for 1–V applications has been proposed. It makes used of dynamic threshold PMOS transistors, which permit implementation of analog circuits at very low supply voltage. The amplifier is capable of operating with a power supply as low as 1–V while providing a 35.7
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