IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000
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A High-Performance Multibit
16 CMOS ADC
Yves Geerts, Student Member, IEEE, Michel S. J. Steyaert, Senior Member, IEEE, and Willy Sansen
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Abstract—The design of a multibit converter is presented. It uses a third-order 4-bit topology with data weighted averaging (DWA) to reduce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to minimize the delay introduced in the feedback loop, resulting in clock frequencies up to 100 MHz. Behavioral models are used to determine several building block specifications. An accurate model is used to analyze the combined effect of the dominant closed loop pole of the operational transconductance amplifier (OTA), the slew rate and the nonzero switch resistance. It is shown that the offset requirements for the quantizer result in a large input capacitance of the quantizer. Therefore scaling of the OTAs, as classically employed in single-bit converters, can no longer be used. For an oversampling ratio of only 24, the converter achieves a signal-to-noise ratio of 95 dB, a signal-to-noise-plus-distortion ratio of 89 dB and an input dynamic range of 97 dB after comb-filtering. The converter is sampled at 60 MHz, resulting in a 2.5 MS/s output rate. It is implemented in a standard 0.65- m CMOS technology, occupies 5.3 mm2 and consumes 295 mW from a 5-V power supply. When clocked at 100 MHz with an oversampling ratio of 8, a 12-bit resolution is achieved at an output rate of 12.5 MS/s.
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Index Terms—Analog-digital conversion, CMOS integrated circuits, sigma–delta modulation, switched capacitor circuits.
I. INTRODUCTION
ADSL, the entire signal band of 1.1 MHz containing a discrete multi-tone (DMT) signal needs to be converted to the digital domain. The sophisticated decoding is performed completely in the digital domain by means of Fourier transforms. Depending on the topology of the receiver, 12 to 16 bits of accuracy are needed in the ADC [1]. converters are used in these kind Typically, pipelined and of demanding applications. Pipelined converters need some kind of (background) calibration or error correction techniques to achieve accuracies of 12 bits or more, resulting in an increased converters on the other hand, are very complexity [2], [3]. suitable to achieve resolutions up to 16 bits. Due to the oversampling, the specifications for the anti-aliasing filter are much more relaxed than for pipelined converters. These are typically oversampled 2 or 4 times to reduce the requirements on the converter with a low anti-aliasing filters [4]. Therefore, a oversampling ratio is a very suitable architecture for these high performance ADCs. The outline of the paper is as follows. In Section II, the topology selection is discussed. Section III treats several converter. Design issues concerning nonidealities in the the different building blocks are treated in Section IV. The next section contains the measurement results and finally in Section VI some conclusions are presented.
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N TRADITIONAL communication receivers, the channel selection is performed in the analog front-end, requiring much filtering and gain. This type of receiver imposes very relaxed requirements on the dynamic range and bandwidth of the analog-to-digital converter (ADC) since it only needs to digitize one channel and most of the blocking signals are filtered out in the analog front-end. This approach is often used in handsets. A different approach is used in wide-band receivers, where the gain and filtering for the channel selection in the analog front-end is minimized. The ADC converts all the channels simultaneously to the digital domain, where all the channel selection and filtering is performed. This type of receiver is often used in base-stations, since only one receiver can be used to decode all the channels simultaneously. Naturally, this type of receiver requires an ADC which combines high accuracy and high bandwidth since large blocking signals can be present and many channels need to be converted simultaneously. The demand for broadband internet access over twisted-pair is another driving force for the development of high-performance ADCs. In digital subscriber line (xDSL) systems such as Manuscript received April 10, 2000; revised July 6, 2000. The authors are with the Katholieke Universiteit Leuven, Department of Elektrotechniek, Heverlee B-3001, Belgium (e-mail:
[email protected]). Publisher Item Identifier S 0018-9200(00)10046-0.
II. SYSTEM-LEVEL CONSIDERATIONS A. Topology Selection In order to combine high resolution with high speed, a small oversampling ratio should be selected to limit the clock speed of the converter and thereby the bandwidth requirements of the integrators. converters would require Classical single-loop single-bit a high order of the loop filter to achieve a good accuracy at a low oversampling ratio. Unfortunately, increasing the order seriously degrades the stability, resulting in a serious deterioration of the signal-to-noise ratio (SNR) compared to an ideal order structure [5], [6]. Cascaded or MASH topologies [7], [8] can combine high order noise shaping with the excellent stability of a second order converter. The main drawback of these topologies are the high building block specifications in order to avoid noise leakage from the first stage to the output. Finally, multibit converters can achieve a significant improvement in performance by employing a multibit quantizer. Besides the 6-dB improvement in SNR for each extra bit in the quantizer, they offer improved stability. This allows a more aggressive noise shaping which results in an additional accuracy improvement [5], [6], [9].
0018–9200/00$10.00 © 2000 IEEE
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Fig. 1.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000
System diagram of the multibit
16 converter.
The main problem of multibit converters is the linearity requirement of the DAC. Since it is in the feedback loop, its acconverter in order curacy needs to be at least as good as the not to deteriorate the performance. Several solutions to alleviate the linearity requirements have been proposed [5]. Dual quantization techniques [10], [11] employ single-bit feedback to the first stages, and multibit feedback to the last ones. This reduces the linearity requirements a lot. However, is not a fully multibit one, less aggressince the resulting sive noise-shaping functions have to be used, resulting in a loss of performance. Besides this, dual quantization techniques are often used in cascaded topologies. The output of the first stage, which is single-bit, contains much more quantization noise than the subsequent multibit stages. Therefore, the already severe building block specifications of cascaded topologies are increased even further to avoid degradation due to noise leakage. Several dynamic element matching (DEM) techniques [5], [12], [13], such as data weighted averaging (DWA) [14], offer a way to use fully multibit structures with reduced requirements for the DAC. These techniques convert the noise and distortion introduced by the nonideal DAC into a noise shaped error. These DEM techniques require an additional digital block in the feedback loop of the converter to scramble the used unity elements in each clock period. The additional delay associated with this scrambler can limit the clock-frequencies of practical implementations. The designed converter employs a single-loop multibit topology to combine a high accuracy with a low oversampling ratio. The third order 4-bit topology uses DWA to reduce the accuracy requirements of DACs in the feedback loop of the converter. The block diagram is shown in Fig. 1. The coefficients of , while mainthe loop are optimized to maximize the SNR taining stability using the methods described in [6]. Compared to a single-bit third-order design, the accuracy improves by 40 dB for two reasons: 1) The accuracy of the converter increases by 6 dB for each additional bit in the quantizer since the amplitude of the quantization error is halved. This results in a 18-dB accuracy improvement for the 4-bit quantizer. 2) The stability of the converter is greatly improved due to the more linear quantizer. Therefore, a more aggressive noise shaping function can be used, which results in an
Root locus of the poles of the third-order modulator with 1 = 0 2 2 = 0 5 3 = 0 5 (inner curve) and 1 = 0 3 2 = 0 8 3 = 2 3 (outer
Fig. 2. a
a
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a
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a
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a
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curve).
better suppression of the quantization noise. Using the variable gain model presented in [15], a root-locus plot is shown in Fig. 2 for a single-bit (inner curve) and a multibit (outer curve) third-order converter. The larger loop coefficients of the multibit converter result in a more aggressive noise shaping and a large accuracy improvement. Despite the more aggressive noise shaping, the overload level is , which is much larger than in the single bit still 0.95 ). The increase of the overload level version (0.55 and the more aggressive noise shaping result in another 22-dB accuracy improvement for the multibit converter. This clearly shows the importance of the stabilizing effect of the multibit converter. The architecture achieves a simulated ) of 97 dB for an signal-to-quantization-noise ratio (SNR oversampling ratio of 24. Table I shows the required signal swings at the output of the integrators. The first two integrators require a swing slightly . When the input signal is close to the oversmaller than load level, the swing of the last integrator is slightly larger than , to make full use of the input range of the 4-bit quantizer. The output of the DWA-block has to be distributed over the
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TABLE I TRACKING OF THE FEEDBACK SIGNAL THE CONVERTER
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OF
entire chip to the local drivers of the feedback DAC switches. Therefore, a buffer is inserted to deal with the large gate and wiring capacitance (Fig. 1). B. Integrator and DAC To limit the power consumption of the converter, it is of the utmost importance to keep the size of the capacitors as low as possible since this reduces the capacitive load on the integrators. Therefore, the integrator and the feedback DAC are combined by splitting up the sampling capacitance into 16 parallel unity capacitors, which can be connected separately to either or . This allows the implementation of the multibit feedback without additional capacitances, thereby avoiding addinoise and capacitive loading of the integrator. Furtional thermore, the circuit is implemented fully differentially, since by 3 dB. Besides this, differential this improves the SNR implementations offer other advantages such as reduced even harmonics, improved power-supply-rejection ratio and better cancellation of clock feed-through. noise floor sufficient for a 16-bit converter, the For a total sampling capacitance needs to be 3.2 pF, resulting in a 200 fF unity capacitance. The matching requirements of these unity capacitances is sufficient thanks to the implementation of the DWA algorithm (Section III-C). This means that the sampling noise requirements capacitance is still determined by the and not by the matching requirements of the DAC. So, compared to a classical single-bit implementation, the multibit DAC requires no extra power in the operational transconductance amplifiers (OTAs) and the extra hardware is very limited. The implementation of the integrator and DAC is shown in Fig. 3(a). During clock-phase , the input signal is sampled on the sampling capacitance, which is split up in 16 unity capacitances. During , the feedback DAC operates by connecting the bottom terminal of each unity capacitance to either or . Since all the switches are implemented as transmission gates, this requires four control signals for each unity capacitance. These 64 signals need to be distributed from the output of the DWA-block to each feedback DAC. This would require much power in the buffers (due to the wiring capacitance) and a large area-overhead for the wiring. In order to reduce the number of feedback signals and the power to drive them, the local switch driver shown in Fig. 3(b) is used in front of each unity capacitance. This circuit generates the control signals for (a slightly advanced verthe two transmission gates from ) and one feedback signal for each unity capacitance. sion of Note that the timing of is critical for the correct operation of the integrator: a zero-zero overlap should be maintained between the outputs of the driver and . The drivers can be
Fig. 3. Implementation of the integrators and feedback DAC. (a) Integrator. (b) Local switch driver.
minimum size since the load capacitance is quite small. Consequently, their power consumption is limited. The main drawback of this implementation of the DAC is the signal dependent load on the reference voltages. For a singleended implementation, each unity capacitance is charged to during the sampling phase . At the end of , the charge , depending on the feedon a unity capacitance is equals the total number of back of the quantizer. If ( ), the charge that has capacitances connected to voltage-buffer during a certain clock to be delivered by the . The charge drawn from cycle is equals . This shows that the capacitive loading of the reference buffers is signal dependent due to and . Furthermore, the charge drawn from the buffer also depends on the input voltage. This signal dependent loading of the buffers can generate severe harmonic distortions.
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Fig. 4.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000
Full model of a switched-capacitor integrator. (a) Sampling Phase. (b) Integration Phase.
By employing differential circuits, this problem can be alleequals viated. The charge drawn from . The capacitive loading of the reference buffers is no longer signal dependent. However, the charge drawn from the reference voltages still depends on the input signal. Therefore, to avoid harmonic distortion, special attention should be paid to the circuit used to buffer the reference voltages. Furthermore, the power consumption of the buffer can become an important part of the total power consumption of the converter [16]. This converter uses external symmetrical reference voltages of 1 V.
the nonzero resistance of the switches is included, to
reduces
(3) and the switch resistance should be This shows that treated together when the frequency performance of the conresults in more power in verter is optimized. Increasing the OTAs, while a smaller results in larger switches and therefore more clock feed-through and larger capacitive loading on is approximately the clock drivers. In this design equal to 1. B. Slew Rate
III. BEHAVIORAL SIMULATIONS A. Integrator Nonidealities Behavioral models for several nonidealities [8] are used to determine the specifications for the different building blocks. The main nonidealities are the finite OTA gain, finite dominant ), the nonzero switch resisclosed-loop pole of the OTA ( tance and the nonlinear resistance of the switch used to sample the input signal. of a switched-capacitor integrator As shown in [8], the can be written as (1)
(2) and are the where is the coefficient of the integrator, and are the sampling and integrator capacitances and parasitic capacitances at the input and output of the OTA. When
Another important nonideal effect in switched-capacitor integrators is the slewing of the OTA. A detailed model of the integrator and DAC of Fig. 3(a) is shown in Fig. 4. It includes all the parasitic capacitances on the input and output node of and ). In order to be consistent with the notathe OTA ( tions used in [8], the total resistance in the signal path equals . Therefore, the switches in the 16 parallel branches with the . The slewing effect of unity capacitors have a resistance of the OTA is incorporated by the current characteristic shown in Fig. 5: for a large voltage on node , the OTA delivers its max. and depend on the feedback imum output current code from the quantizer. They represent the number of unity caand . and pacitors connected to respectively represent a simplification of the sampling network of the next stage. Its importance will be discussed later. The required slew-rate values can be calculated as (4) with
given by (2).
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Fig. 5. Modeling of output current of OTA with slew rate.
Slewing is most likely to occur at the beginning of the integration phase. The voltage sampled on the sampling capacitance of the OTA, causing a is then switched to the input terminal large voltage spike on node which can drive the OTA into the slewing condition. Several attempts have been made to derive an analytical model [17], [18] without including the switch resistance. These models show that it is very important to include the and into the model, since the initial voltage parasitics peak at the input node of the OTA ( ) is seriously reduced due to an immediate charge redistribution at the start of the integration phase. However, two important extensions should be added to this model to make it more accurate: inclusion of the nonzero switch resistance and the sampling operation of the next stage. The resulting model of Fig. 4 gives rise to very tedious analytical expressions since the number of nodes is significantly increased. Therefore, the differential equations describing Fig. 4 are solved numerically in Matlab. Fig. 6(a) shows the transient waveforms of the input and output node of the integrator without the resistance of the switches, while Fig. 6(b) includes the resistance of the switches. The thin lines in Fig. 6(b) are the waveforms from a full circuit simulation. This clearly shows the models matches the circuit simulator very closely. The full horizontal lines indicate the .A limits for the slewing condition, given by comparison of these waveforms clearly shows two important effects of the resistors. First, the peaks at the beginning of and are reduced since there is no longer an immediate charge redistribution between the capacitances. Instead, the peak is more smooth due to the RC-time constants in the signal are smaller, the OTA will be path. Since the peaks at node slewing less frequently and less current will be delivered by the of the OTA is OTA. Furthermore, due to the resistance, as explained in Section III-A. These effects reduced to result in a slower settling. The waveforms also show that it is necessary to include the sampling operation of the next stage. At the beginning of , is connected to the output of the OTA and a voltage drop of the output is observed. Note that shows the same drop, so
Fig. 6. Waveforms of the full model of the integrator. (a) Without resistors. (b) Including resistors. The thin lines are the waveforms from the full circuit simulation.
the charge on the integration capacitance is not affected. Due to this peak, the OTA can also be in the slewing condition during . To ensure the correct voltage sampled on , this peak should also settle. Therefore, the sampling of the next stage needs to be included. Extensive simulations have been performed for five different values of the switch resistance and several maximum currents converters, while of the OTAs. Fig. 7 shows the SNR of the Fig. 8 indicates in how many clock periods slewing occurs for the first OTA. When the switch resistance increases, a larger is required to get the full performance of the value of converter, but slewing occurs less frequently since the peaks degrades for an increasing are smoothed out. Since the switch resistance, more time is required for the settling. This means that the time spent in slewing during one period should be decreased to leave enough time for the linear settling of the is required. When the switch OTA and therefore a larger resistance becomes to high, the settling becomes to slow and deis very large and grades the SNR of the converter, even if slewing no longer occurs. Compared to single-bit converters, the integrator requireconverters since the ments are relaxed in a multibit feedback signal tracks the input much more accurately. This
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Fig. 7. SNR versus switch resistance and maximum output current of OTA.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000
Fig. 9. Required matching of the unity capacitances of each stage.
Fig. 10.
Fig. 8. Relative number of clock periods in which slewing occurs.
is illustrated in Table I. This means that the integrator only needs to integrate small voltage differences. Simulations for the first integrator show a required maximum current of 0.75 mA, resulting in a slew rate of approximately 100 V/ s. The requirements for the other integrators are a bit less. Note that a slightly different model is used for the third integrator, since this stage is sampled by the quantizer during the integration phase ( ). C. DWA DWA is a DEM technique which reduces the matching-requirements of the DAC unity elements. The DWA algorithm converts the noise and distortion introduced by the nonideal DAC into a first order high-pass noise shaped error [14], [19]. One of the main advantages of the DWA algorithm is its simplicity. All the DAC-unity elements are sequentially used and one pointer is required to remember the first unused unity element. The operation is illustrated in the inset of Fig. 9 for a
Timing of the building blocks.
3-bit DAC. The shaded boxes indicate which of the 8 unity carepresents the pacitances are used in each clock period and output of the ADC. converter with DWA algoA behavioral model of the rithm and a nonideal DAC is used for Monte Carlo simulations. Fig. 9 shows the worst-case signal-to-noise-plus-distortion ratio converter versus the required matching of (SNDR) of the the unity capacitances of the different integrators. The first curve shows the performance without the DWA algorithm for the first integrator, while the other curves include the DWA algorithm in the model. These simulations show the reduced linearity requirement of the DAC due to the DWA algorithm. For the first integrator, a sigma of 0.2% is required, while the second and third integrator only need a sigma of 1% and 10%, respectively. This clearly shows that the nonidealities of the second and third integrator are suppressed by the gain of the preceding integrators. A known problem of DWA algorithm, is the occurrence of in-band tones, dependent on amplitude and signal frequency of the input signal [14]. This can degrade the SNR performance at lower input levels. Extensive Monte Carlo simulations with various input amplitudes have been performed to find the largest in-band tone. These simulations show that the largest in-band noise floor of the converter. tone is below the level of the Therefore, these tones will not be visible in the output spectrum of the converter and will not degrade the performance of the converter. This is confirmed by the measurement results. When a converter with a higher resolution (e.g., 20 bit) is required for
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Fig. 11. Implementation of the DWA algorithm, optimized for speed.
the same matching performance of the capacitances, these tones can become a problem and different shuffling algorithms should be used [20]. IV. DESIGN CONSIDERATIONS OF THE BUILDING BLOCKS A. DWA Implementation The implementation of the DWA algorithm is critical for the achievable clock speed of the converter, since it adds additional delays in the feedback loop of the converter. A detailed timing diagram of all the building blocks of the converter is shown in Fig. 10. During , all the integrators sample a charge onto their sampling capacitance, which is integrated during . At the same time, the feedback signal is also integrated by connecting , depending on the feedback the unity capacitances to signal. In the meantime, the quantizer samples the output of the last integrator. During the next phase, the quantizer generates a thermometer output code, which is rotated by the DWA-block, depending on the pointer of the DWA algorithm. Since the feedphase, only back signal needs to be available during the next half a clock period is available for the regeneration of the quantizers and the rotation of the thermometer code. Therefore, it is of the utmost importance to minimize the delay introduced by the DWA-block. The pointer of the DWA algorithm is updated during .
The implementation of the DWA algorithm, shown in Fig. 11, is optimized for a minimum delay in the feedback-path of the converter. A logarithmic shifter is used in the signal path to provide the rotation of the thermometer code required by the DWA algorithm. The rotation pointer is stored in the 4-bit pointer register and incremented each clock-cycle by the output-code of the quantizer. The incrementing of the binary pointer register with the thermometer output-code of the quantizer is performed with dynamic logic. Extreme care has been taken to ensure the proper timing of all the signals. Fig. 12 shows the timing of the different parts of the DWA implementation. As explained in Section IV-B, all the quantizer outputs are high during the reset phase ( ). All the nodes of the logarithmic shifter are charged during this phase. During , the comparator regenerates the initial imbalance established during the previous phase. The resulting thermometer-output ripples through the logarithmic shifter, the level restorer and the transmission gate. Note that the control-signals of the shifter should be stable during this phase. At the same time, the CON-block converts the thermometer code to a 1-of-n code. Since the only possible transition of the quantizer output is from high-to-low, the four-stage logarithmic rotation shifter is implemented with only nMOS transistors to achieve a minimal delay in the logarithmic shifter.
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of the MOS regeneration transistors and switches M3 can be neglected. The offset of the quantizer can be calculated as (5) (6) where the mismatch factor is neglected [23]. From this, a relation between the lengths of transistors M1 and M2 results for optimal matching: (7) Fig. 12.
Timing of the DWA implementation.
The pointer of the DWA algorithm is stored in the 4-bit binary pointer register. To this binary number, the thermometer output code has to be added. To minimize the delay, no explicit conversion of the thermometer code to binary is performed. Instead, the dynamic logic block directly adds the 1-of-n code of the CON-block to the binary pointer register during . This also guarantees that the control signals of the shifter remain stable during . The second dynamic logic block converts the therconverter. mometer-code to the binary output code of the The output bits are send through a clocked register to ensure proper synchronization. The feedback signals FB1 FB16 are buffered since they need to drive the large wiring loads. These signals are distributed over the entire chip to all the integrators. To reduce the number of feedback signals, local decoders are used to drive the feedback switches. This results in a reduction of the digital power and area, as explained previously. Simulations and measurements show that clock-frequencies up to 100 MHz are possible with this implementation. B. Comparator Since the nonidealities of the quantizer are suppressed by the loop gain of the preceding integrators, the offset specification of the quantizer is generally very relaxed and does not degrade converter. However, in high-accuthe performance of the converters, this in no longer true [21]. Monte racy multibit Carlo simulations with a behavioral Matlab model of the converter with nonzero offset in the quantizer reveal the folmV. lowing offset specification: The schematic of the fully differential comparator is shown in Fig. 13 [22]. The comparator is designed to combine a high regeneration speed with a low offset and hysteresis, while the input capacitance and the power consumption should be kept as low as possible. During clock phase , the top and bottom regeneration loop are reset and the differential pairs inject a current which generates an initial voltage imbalance across the on resistance of switch M6. The polarity of this imbalance deterregeneration phase. Since mines the outcome of the goes down just before rises, the imbalance is first regenerated by the bottom regeneration loop [22]. Therefore, if the gain during this first regeneration is large enough, the mismatch
To combine high-speed, low input capacitance, and low power, minimum dimensions are selected for . Each differential pair is biased with 200 A. During the reset phase of the quantizer, all the outputs are high. Therefore, the only possible transition of the quantizer output is from high to low during the regeneration phase. The implementation of the shifter of the DWA algorithm is optimized for this transition (Section IV-A). However, for small input signals, the initial imbalance will be very small and the voltages on the two nodes of the top-regeneration loop will start to drop together toward a meta-stable point before the regeneration starts. This situation could switch INV1A twice, resulting in a high-to-low followed by a low-to-high transition at the output. To avoid this, the of inverters INV1A and INV1B is lowered below the meta-stable point, which is determined by the relative size of the top and bottom regeneration loop. This ensures that the only possible transition is from high-to-low during the regeneration phase. Note that INV1B is only used as a dummy, to provide a symmetrical loading on the regeneration loops. The quantizer is composed of 16 comparators and a resistance ladder to generate the reference voltages. Due to the large input capacitance, a considerable amount a kickback noise is injected during the regeneration phase into the resistance ladder and the last integrator. To reduce this, both the reference voltages and the input-signals of the quantizer are sampled during , when the quantizer is being reset. C. Integrators and Scaling The size of the unity capacitances of the first stage determines noise and the matching the white noise floor due to the of the unity elements of the DAC, as explained in Section II-B. Since both requirements are suppressed by the gain of the preceding integrators, the integrators and capacitances are scaled converters [7], [8]. down in classical single-bit In Section III, behavioral models are used to determine the specifications for each OTA such as gain, dominant closed loop pole, slew rate, and the maximum allowed resistance of the switches. A folded-cascode topology with gain-boosting stage (Fig. 14) is used to combine an excellent frequency performance with high gain [7], [24]. The first OTA achieves a dominant ) of 220 MHz with 80 phase margin and closed loop pole ( a slew rate of 145 V/ s. It consumes 34 mW and uses a dynamic common mode feedback. The second OTA is scaled to 0.75 times the first one.
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Fig. 13.
Schematic of the comparator.
Fig. 14.
Schematic of the OTA.
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In contrast to classical single-bit converters, the last OTA is given by (1) and is not a scaled version of the first OTA. is boosted up by the approximately . (2). Note that Due to the large input capacitance of the quantizer (1.3 pF) and ), the equivthe large coefficient of the last integrator ( alent closed loop capacitance of the last integrator is even larger as much as than the one from the first integrator. To reduce possible, the output transistors are reduced in size compared to the first OTA.
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Thanks to the multibit feedback, the difference between the input and the feedback signal of the last integrator is much smaller than the one of the first OTA (Table I). Therefore, the slew-rate requirement for the last OTA is significantly reduced. This can also be concluded from the behavioral simulations, of the which show a slightly smaller requirement for the is much larger, resulting is a much last integrator, but the lower slew rate value which is given by (4). Therefore, the of the input transistors can be reduced. This increases the
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Fig. 16.
Fig. 15.
16 microphotograph.
transconductance and at the cost of the slew rate. The last of 160 MHz with 83 phase OTA achieves a simulated margin and a slew rate of only 60 V/ s, which is still more than sufficient. The power consumption is 45 mW.
V. LAYOUT AND MEASUREMENT RESULTS The converter is implemented in a 0.65- m CMOS process, operating from a 5 V supply. During layout, special care has been taken to provide identical surroundings for the unity capacitances of the DAC. Furthermore, the analog part is fully symmetrical, keeping the digital feedback signals separated from the analog part and the sampling capacitances. Shieldings are provided to the most sensitive nets such as the reference voltages. It is of great importance to reduce the inductance of the bondwires and provide sufficient on-chip decoupling to avoid severe voltage-drops when the clock-buffer is switching. The micro-photograph of the chip is shown in Fig. 15. For measurement purposes, the fabricated die is mounted on a ceramic substrate. The substrate is encapsulated in a copperberyllium case to provide shielding from external noise sources. The power supplies are carefully decoupled, on chip as well as on the substrate. Great care has been taken to avoid cross-talk
Measured SNR and SNDR.
problems of the digital supplies onto the analog supplies and reference voltages. Using a clock frequency of 60 MHz and on oversampling ratio of 24, the output bit-stream of the converter is processed in Matlab using a sinc comb-filter [5]. Fig. 16 shows the measured SNR and SNDR for a 25-kHz input signal. A dynamic range of 97 dB is achieved in a 1.25-MHz signal bandwidth. The power consumption is 295 mW, of which 152 mW is consumed in the analog part. The digital power consumption is mainly due to the clock-buffer, which generates the nonoverlapping clocks for the switch-capacitor circuits from one external clock-signal. The power spectral density of the measured output is shown in Fig. 17. Up to the edge of the signal band, the noise floor , and quantization noise limited is white noise limited afterwards. The third-order noise shaping is clearly visible. Also note that the total power of the quantization noise is converter. Fig. 17(a) much smaller than in a single-bit shows the output when the DWA algorithm is disabled by freezing the position of the pointer. A large second and third harmonic distortion component is visible. Fig. 17(b) shows the same measurement with the DWA algorithm switched on and no harmonic distortion components are visible above the white noise floor. Note that no tones were observed during the measurements, thereby confirming the conclusions of the simulations in Section III-C. The converter stays functional for clock-frequencies over 100 MHz, clearly indicating the small delay introduced by the DWA algorithm. The harmonic distortion increases at these frequencies, due to settling problems of the integrators. However, when the oversampling ratio is reduced to 8, a SNR and SNDR of respectively 68 and 67 dB can still be achieved. Turning the DWA algorithm on or off does not change the SNDR, indicating sufficient matching of the unity capacitances for 12-bit accuracies. The converter can thus also be used as a 12-bit ADC with a 12.5 MS/s output rate. The power consumption increases to 380 mW [25]. The most important specifications are summarized in Table II.
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TABLE II PERFORMANCE SUMMARY
Fig. 17. Measurement of the power spectral density of the output with DWA turned off and on.
[28], [16], [26], the converter achieves both the highest resolution, the highest output rate and the best figure of merit, which is a good measure for the power-resolution-bandwidth trade-off [27]. ACKNOWLEDGMENT
VI. CONCLUSION This paper discusses the design of a multibit converter. A DWA algorithm is used to reduce the linearity requirements for the feedback elements. The implementation of the DWA algorithm is optimized for high-speed operations. Clock frequencies over 100 MHz can be achieved, which is much higher than preADCs employing DEM viously reported speeds for similar [16]. Special attention is paid to the combined effect of finite OTA closed loop pole, slew rate and nonzero switch resistance on the settling of the integrators. Behavioral simulations show that the offset specification of the quantizer can become very deconverters. This remanding for high-resolution multibit sults is a large capacitive load on the last integrator and therefore scaling of the integrator, as classically used in single-bit converters, is no longer possible. converter achieves a SNR of 95 dB The third-order 4-bit for an oversampling ratio of only 24. The clock frequency is 60 MHz, resulting in a 2.5 MS/s output rate and a 295 mW power consumption. Compared to state-of-the-art high-speed AD converters [7], [8], [10], [11], high-resolution CMOS
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Yves Geerts (S’96) was born in Geel, Belgium, in 1973. He received the M.Sc. degree from the Katholieke Universiteit Leuven, Belgium, in 1996, where he is currently working toward the Ph.D. degree. Since 1996, he has been a Research Assistant at the ESAT-MICAS Laboratory at the Katholieke Universiteit Leuven. His main research interests are in the area of high-speed analog-to-digital and digital-toanalog data converters.
Michel S. J. Steyaert (S’85–A’89–SM’92) was born in Aalst, Belgium, in 1959. He received the Master’s degree in electical-mechanical engineering and the Ph.D. degree in electronics from the Katholieke Universiteit Leuven (K. U. Leuven), Heverlee, Belgium, in 1983 and 1987, respectively. From 1983 to 1986, he obtained an IWNOL fellowship (Belgium National Foundation for Industrial Research) which allowed him to work as a Research Assistant at the Laboratory ESAT at K. U. Leuven. In 1987, he was responsible for several industrial projects in the field of analog micropower circuits at the Laboratory ESAT as an IWONL Project Researcher. In 1988, he was a Visiting Assistant Professor at the University of California, Los Angeles. In 1989, he was appointed by the National Fund of Scientific Research (Belgium) as Research Associate, in 1992, as a Senior Research Associate, and in 1996, as a Research Director at the Laboratory ESAT, K. U. Leuven. Between 1989 and 1996, he was also a part-time Associate Professor, and since 1997, he has become an Associate Professor at the K. U. Leuven. His current research interests are in high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing. Dr. Steyaert received the 1990 European Solid-State Circuits Conference Best Paper Award, the 1995 and 1997 ISSCC Evening Session Award, and the 1991 NFWO Alcatel-Bell Telephone award for innovative work in integrated circuits for telecommunications.
Willy Sansen received the M.S. degree in electrical engineering from the Katholieke Universiteit Leuven (K. U. Leuven) in 1967 and the Ph.D. degree in electronics from the University of California, Berkeley, in 1972. Since 1981, he has been a full Professor at the ESAT Laboratory of the K. U. Leuven. During 1984 to 1990, he was the Head of the Electrical Engineering Department, K. U. Leuven. He was a Visiting Professor at Stanford University, Stanford, CA, in 1977, the University of Lausanne, Lausanne, Switzerland, in 1981, the University of Philadelphia, Philadelphia, PA, in 1985, and the University of Ulm, Ulm, Germany, in 1994. He has been involved in design automation and in numerous analog integrated-circuit designs for communications, consumer electronics, medical applications, and sensors. He has been supervisor of 41 Ph.D. theses in these fields and has authored and coauthored nine books and more than 500 papers in international journals and conference proceedings.
