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A Low-Jitter 1.9-V CMOS PLL for UltraSPARC Microprocessor Applications Hee-Tae Ahn, Student Member, IEEE, and David J. Allstot, Fellow, IEEE
Abstract—A phase-locked loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of ±25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loop filter, and a feedforward error correction architecture. Loop characteristics are analyzed and verified by measurements. The measured sensitivity of clock period jitter to supply voltage is 2.6 ps/100 mv over an analog supply-voltage range of 1.6–2.1 V; the measured output operating frequency range is 8.5–660 MHz. Fabricated in an area of 310 × 280 µm2 in a 0.25-µm CMOS process, the PLL dissipates 25 mW from a 1.9-V supply. Index Terms—Analog integrated circuits, clocks, frequency synthesizers, phase-locked loops.
I. INTRODUCTION
Fig. 1.
M
ODERN high-speed microprocessors employ deep-submicrometer CMOS devices to achieve gigahertz operating frequencies. As the gate length is shrunk to achieve faster operation, the power-supply voltage is reduced to avoid breakdown and reliability failures [1]. Analog circuit design becomes increasingly more difficult in, for example, a 0.25-µm CMOS process that requires a 1.9-V power-supply voltage. Making matters worse, the allowable clock jitter decreases at higher clock frequencies for a given clock skew tolerance; e.g., a jitter less than ±4% of the clock cycle time is typically needed to avoid functional failures in a microprocessor. Moreover, the high degree of integration leads to the generation of substantial digital switching noise that is coupled through the power-supply network and the substrate into noise-sensitive analog circuits [2]. A charge-pump phase-locked loop (PLL) often employs a series RC loop filter where R is added to form a left-half-plane (LHP) zero that stabilizes the loop [3]. That approach is limited by process, voltage, and temperature (PVT) variations of the resistance. Process variations alone are typically ±30% for an ion-implanted resistor in a digital CMOS process. Since the damping factor is proportional to R [3], [4], loop stability changes dramatically with PVT variations. Excellent PLL performance has been reported using a resistorless architecture at 3.3 V [5]. To stabilize the loop, feedforward current injection was implemented using an auxiliary charge pump; the loop filter capacitors were grounded to the (noisy) substrate. A PLL with its loop filter referenced to a separate quiet supply, rather than the noisy substrate, was recently Manuscript received August 2, 1999; revised October 11, 1999. H.-T. Ahn was with Sun Microsystems, Inc., Palo Alto, CA 94303 USA. He is now with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706 USA (e-mail:
[email protected]). D. J. Allstot is with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195-2500 USA (e-mail:
[email protected]) Publisher Item Identifier S 0018-9200(00)00534-5.
PLL system.
proposed [6]. This brief paper also describes the design of a low-jitter, fully integrated CMOS charge-pump PLL wherein the loop filter is referenced to a quiet analog supply. Measured results are presented for the PLL used in a low-voltage, high-frequency UltraSPARC microprocessor environment. II. SYSTEM ARCHITECTURE A block diagram of the PLL is shown in Fig. 1. It uses a three-state phase/frequency detector (PFD), and its loop filter , is referenced to the separate (quiet) analog supply capacitor, . A PLL that uses a single-capacitor loop filter without a zero-forming resistor is marginally stable. In our design, a stabilizing loop zero is created by a feed-forward path from the PFD output to the voltage-to-current (V–I) converter input of the voltage-controlled oscillator (VCO), which bypasses the loop filter (Fig. 1). The clock distribution network comprises clock drivers and buffers that use the standard digital power supply and ground and is the only block that is directly exposed to digital switching noise. The input, output, and VCO operating frequencies are 180, 360, and 720 MHz, respectively. III. CIRCUIT DESIGN A. PFD/Charge Pump The PLL uses the three-state PFD and charge-pump circuits shown in Fig. 2. The PFD is designed to generate symmetrical charge-up (u) and charge-down (d) pulses. The potential dead zone is eliminated by the propagation delay of the four-input NOR gate, which produces a minimum pulse width at the PFD output even when the phase error is zero. The charge pump comprises complementary current sources, switches, and source followers (Fig. 2). The source followers output; their threshold voltages deare driven by the termine the voltages across the complementary switches when
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Fig. 2. Charge pump and phase/frequency detector.
Fig. 4. Voltage-controlled oscillator.
Fig. 3.
Measured PFD/charge-pump gain characteristic.
they are OFF. This technique reduces the current error between charge up and charge down due to the mismatch of chargesharing effects when the switches are turned ON. Stated another . way, the current mismatch is ideally independent of Fig. 3 shows a measured PFD/charge-pump gain characteristic . The gain mismatch between charge up and charge including down is about 3%, and there is no evidence of a dead zone near the origin. B. Voltage-Controlled Oscillator As shown in Fig. 4, the VCO comprises four subcircuits: a V–I converter, current-controlled ring oscillator (CCO), voltage-level shifter, and damping factor control circuit. – form a PMOS regulated cascode V–I Transistors converter that sources drive current to the CCO; compensation stabilizes the regulated loop and suppresses the capacitor injection of high-frequency supply noise into the CCO. Owing to the regulated cascode, the small-signal output resistance of the CCO driving current source is very high (approximately ). Hence, the driving current is nearly independent of the supply voltage for a given input voltage , and excellent power-supply noise rejection characteristics are achieved [7]. The output jitter also exhibits low sensitivity to power-supply noise over a wide range of frequencies (Fig. 8); the measured output jitter deviation changes by only ±2.6 ps per 100-mV change in supply voltage. The gains of the VCO and the PFD/charge-pump circuits are important factors in determining the loop bandwidth (BW). Since the loop filter output voltage is headroom-limited in a low-voltage design, high VCO gain is needed to achieve a wide
Fig. 5. Measured VCO gain characteristic.
operating frequency range. The VCO gain is chosen based on a tradeoff between operating frequency range and loop bandwidth. The CCO used in the VCO (Fig. 4) is a balanced fiveV, the stage, single-ended ring oscillator. With measured VCO gain (Fig. 5) is 2.5 GHz/V with good linearity over a wide range of operating frequencies from 8.5 to 660 MHz. and in Fig. 4, the CCO Due to the voltage drops across . Hence, a level-shifting buffer ciroperates from about cuit follows the CCO to provide a rail-to-rail output signal. The damping factor control circuit is biased using PMOS (Fig. 4). When all four input branches driven by signals u, ub, d, and db are static (no pulse generated), the left branch current flows to ground through the diode-connected NMOS transistor while the right branch current adds to the main CCO driving current. When pulses are applied to the differential pairs due to a phase error at the PFD inputs, both branch currents flow either to ground or to the CCO, depending on the polarity of the phase error. The amount of current that is subtracted from or added to the CCO driving current is proportional to the magnitude of the phase error and to the static current level, which depends on the operating frequency. The loop stability and the equivalent damping factor increase with the magnitude of the dc bias currents applied to the damping factor control circuit.
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TABLE I PERFORMANCE SUMMARY
Fig. 6.
A continuous-time PLL model.
Fig. 7. A continuous-time PLL model including input and power-supply noise sources.
IV. LOOP RESPONSE Using a continuous-time approximation [3], the PLL architecture of Fig. 1 can be modeled linearly as in Fig. 6. The linear approximation is valid for input frequencies at least ten times higher than the loop bandwidth [4]. Since that ratio is about 72 in this design, the linear model applies and the open-loop transfer function is
with Fig. 8. Measured period jitter versus frequency characteristic for the input noise source.
From the above equations, note that the PLL with feed-forward error correction is equivalent to a PLL with the loop filter and a pole at the origin. is an importhat has a zero at tant parameter that can be varied independently of the natural increases, the zero frequency and open-loop gain. As frequency decreases. If the unity-gain frequency is high compared to the zero frequency, the phase margin of the loop inis reached when the noise creases. The upper limit on gain through the feed-forward path becomes significant; i.e., there is a tradeoff between loop stability and noise gain. The PLL linear model including noise sources is shown in Fig. 7. Generally, there are four major noise sources: input noise, analog and digital power-supply noise, and internally generated noise. The effects of digital supply noise were reduced using separate supply lines. The internal noise was minimized by careful circuit design including, for example,
high-slew-rate charge-pump currents. Several sets of measurements were performed to characterize the loop responses to the input and analog power-supply noise sources. For the loop response to the input noise, the output peak-to-peak period jitter was measured while the input frequency was switched between 179 and 181 MHz at a rate that varied from 1 kHz to 100 MHz. The slightly underdamped measured response (Fig. 8) passes input noise frequencies below the loop BW (about 2.5 MHz). To observe this response explicitly, the output clock period was monitored for both 1-kHz and 10-MHz input modulating frequencies. Fig. 9(a) shows the measured output cycle time distribution for the former case. The output cycle time tends to follow the frequency modulated input signal, so the curve has a bump corresponding to each of the two input cycle times. A peak-to-peak jitter of ±71 ps was measured in this case. When the modulation frequency is 10 MHz [Fig. 9(b)], the output cannot respond to the modulated input. Hence, the curve exhibits a single peak corresponding to an intermediate frequency, and the peak-to-peak jitter decreases to ±25.3 ps. Thus, a low-pass transfer characteristic is observed.
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(a) Fig. 10. Measured period jitter versus power-supply noise frequency at two clock frequencies.
(b) Fig. 9. Output cycle time distribution with the input modulated between 179 and 181 MHz at a rate of (a) 1 kHz and (b) 10 MHz. Both measurement results were taken over 107 cycles. The peak-to-peak period jitter was ±71 ps in (a) and ±25.3 ps in (b).
Measured results also show a power supply voltage dependence of only ±2.6 ps/100 mV. The other major PLL noise source is VCO power-supply noise coupled into the input of the high-gain VCO. Low-frequency noise injected at the VCO input is attenuated by the loop, but high-frequency noise appears directly at the output. ac voltage source representing a noise signal A 400-mV was added to the dc power supply voltage. Peak-to-peak period output jitter was then measured over the supply-noise frequency range, as shown in Fig. 10. As expected, the output jitter response shows a high-pass characteristic with a −3-dB bandwidth of about 2.5 MHz. Phase error generated by the same power-supply noise source measured between the input and output signals is shown in Fig. 11. As expected, it exhibits a bandpass characteristic. This graph clearly shows a phase error peak at 2.7 MHz corresponding to the natural fre. The loop BW calculated with the given damping quency factor is about 2.5 MHz, in good agreement with the simulation result. Fig. 11 also shows the phase error dependence on the power-supply noise magnitude. The VCO has a separate ground metal line and is placed in the middle of the loop filter for spatial isolation from the digital ground noise sources, as shown in Fig. 14. V. MEASUREMENT RESULTS Output peak-to-peak period jitter was measured using an Advantest automatic tester with the UltraSPARC microprocessor
Fig. 11. Measured phase error versus power-supply noise frequency for 200and 400-mV peak-to-peak noise amplitudes.
Fig. 12. Measured period jitter versus PLL output frequency. (V Advantest with vector running).
= 1:9 V,
in a test board while the most power-consuming vector was running. Fig. 12 shows the output jitter dependence on PLL output frequency measured for more than 105 cycles. It shows less than ±60 ps of jitter for operating frequencies greater than 400 MHz. A ±25-ps period jitter was measured at the nominal operating frequency of 360 MHz. Fig. 13 presents the output jitter variation due to supply voltage changes including both analog and
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VI. CONCLUSION
Fig. 13. Measured jitter versus vector running).
V
and
V
A low-voltage and high-frequency charge-pump PLL design has been presented with extensive measured results. A dedicated analog power-supply referenced loop filter and current regulated high-gain VCO enable high power-supply noise rejection. The PLL with a first-order loop filter is stabilized using a feed-forward error correction technique. A wide output operating frequency range, 8.5–660 MHz, was achieved with a nominal 1.9-V power supply using a high-gain VCO. A summary of the measured performance is given in Table I. A field test with the chip used in a complete microprocessor system confirms ±80 ps of total peak-to-peak period jitter monitored for one week while running UNIX. The PLL was fabricated in 310 by 280 m2 in a 0.25- m CMOS process. It dissipates 25 mW. . (400 MHz, Advantest with
ACKNOWLEDGMENT The authors thank S. Selna and K. Ho of Sun Microsystems, Inc., for useful technical discussions and support and W. Baldwin for assistance in testing the PLL. REFERENCES
Fig. 14. Die microphotograph. (0.25 µm, five-metal, single-poly CMOS process).
digital supplies. It shows an output peak-to-peak jitter dependence of −3.6 ps/100 mV. The low supply-voltage limit at 400 MHz is 1.35 V.
[1] The National Technology Roadmap for Semiconductors, Semiconductor Industries Association, 1997. [2] N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Boston, MA: Kluwer Academic, 1995. [3] B. Razavi, “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial,” in Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. New York: IEEE Press, 1996. [4] F. M. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, Nov. 1980. [5] I. I. Novof, J. Austin, R. Kelkar, D. Strayer, and S. Wyatt, “Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter,” IEEE J. Solid-State Circuits, vol. 30, pp. 1259–1266, Nov. 1995. [6] R. Baghwan and A. Rogers , “A 1 GHz dual-loop microprocessor PLL with instant frequency shifting,” in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 336–337. [7] W. C. Black Jr., D. J. Allstot, and R. A. Reed, “A High-performance lowpower CMOS channel filter,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 929–938, Dec. 1980.
