A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology F. Tobajas, R. Esper-Chaín, R. Regidor, O. Santana, R. Sarmiento Instituto Universitario de Microelectrónica Aplicada, IUMA Departamento de Ingeniería Electrónica y Automática, University of Las Palmas de Gran Canaria 35017 Las Palmas de Gran Canaria, Spain
[email protected]
Abstract— In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS techonology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for lowspeed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technology's corner cases. The final IC has an area of 700 µm x 1045 µm and a total power consumption of 300 mW aprox. Index Terms— High-Speed Deserializer, Low Power, SiGe, ECL-CMOS converter.
I. INTRODUCTION
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HE spectacular development experienced by communications technologies in the last years has allowed a huge amount of bandwidth available at a low cost. Nevertheless, switches have not evolved in the same way. For this reason, together with the explosive growth of the Internet users, it is to expect that switches will become the bottlenecks for future communications networks. Due to this increasing demand for high-speed operation, communication between different PCBs of a backplane have evolved from shared parallel buses into serial transmissions requiring the inclusion of SERializer/DESerializer (SERDES) circuits. In the light of the above circumstances, a low power 1:32 2.5 Gbps deserializer in SiGe technology is presented in this paper. In the next section, previous works on deserializers are described. In Section III the chip architecture is outlined and in Section IV the most important circuits are deeply analyzed. In Section V the physical implementation process is described and, finally, simulated results are summarized in Section VI. II. PREVIOUS WORKS A. Technology The development of SONET standard at the end of the
80’s decade was the starting point of a speed race that still continues today. New circuits were required to reach higher transfer rates but the only available technology to achieve it was GaAs [1]. Several years after, first demultiplexers over 1 Gbps fabricated in silicon appeared [2] and later on, first high speed transceivers using CMOS were published [3]. Because the evolution of CMOS wasn’t on a level with the speed requirements, InP started being used in the design of high speed circuits. The first prototypes published in 1996 [4] operated at transfer rates over 40 Gbps and higher speeds were achieved with this technology in a short period time. At the beginning of the 21st century, demultiplexers and deserializers began to be designed using the new IBM SiGe BiCMOS technology, which allowed the combination of MOS devices and HBTs in the same IC in order to achieve high transfer rates with low power consumption and, what is more important, low fabrication cost [5]. In the last few years, SiGe technology has shown an increase of the operation frequency so that nowadays it is possible to design receivers over 40 Gbps [6]. B. Structures Different structures have traditionally been utilized to design multiple outputs demultiplexers. However, the most commonly used architectures in recent devices are based on shift-registers, multiphase clock registers and tree structures. Based on a shift-register it is possible to demultiplex a serial data flow into several outputs. This structure (Fig. 1) is easy to implement because of the low number of circuits required. In addition, all registers work under the same conditions, which means that the same cell can be used for all the components of the circuit. However, a high frequency clock signal is also required, and therefore power consumption increases, as well as complexity. There are other more complex architectures (Fig, 2) also based on shift-registers that allow more control over the data charge and bit rotation. IN
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Fig. 1. 1:4 demultiplexer based on a shift-register architecture. Manuscript received March 16, 2006.
c 1-4244-0185-2/06/$20.00 2006 IEEE
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Fig. 2. 1:4 demultiplexer based on shift-registers with enable signal.
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Multiphase clock based structures represent another way of deserializing data. As the previous structure, this architecture is mostly formed by registers, as shown in Fig. 3. Two different parts can be distinguished. The circuit located at the bottom is a multiphase clock signal generator that provides clock signals for the output registers. In order to generate these signals, a high frequency clock signal is also required. Data are then transmitted to the corresponding output depending on the active phase. IN
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Fig. 4. 1:8 demultiplexer based on a tree structure.
III. CHIP ARCHITECTURE The IC presented in this paper deserializes a 2.5 Gbps serial data flow into a 32-bit parallel data flow at 78.125 Mbps. The main circuits of the deserializer are the 1:32 demultiplexer and the clock distribution network. A block diagram of the deserializer is shown in Fig. 5.
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Fig. 3. 1:4 demultiplexer based on multiphase clock registers.
The tree structure is composed of several 1:2 demultiplexers connected as shown in Fig. 4. Clock signals of different frequencies are required for each stage and consequently a clock distribution network must be included. Even though, this is the main advantage of this structure. For a 2.5 Gbps demultiplexer, the highest frequency required is 1.25 GHz if there is no retimer circuit at the input, whereas for the other structures a 2.5 GHz clock signal is essential. And what is more, there is only one stage working at this frequency which means that power consumption can be easily reduced. In order to generate the required demultiplexer’s selection signals in the tree structure with different frequencies, static or dynamic frequency dividers are commonly used. Static frequency dividers consist of a master-slave flip-flop in a negative feedback, whose slave latch should have a high load drive in order to allow the connection of multiple stages. Dynamic frequency dividers are based on a Miller configuration composed of a mixer and a low-pass filter.
Fig. 5. Architecture of the 1:32 deserializer.
The demultiplexer is based on a tree structure composed of 1:2 demultiplexers, which means that six different clock signals are required: 78.125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz, 1.25 GHz, and 2.5 GHz. These clock signals were generated by static frequency dividers formed by D-flip-flops from a 2.5 GHz external clock. In order to reduce power consumption, two different logic families were used in the proposed design. Low-speed circuits were designed in CMOS (standard cells) whereas high-speed circuits were designed using bipolar ECL structures. In order to adapt the ECL signals to the CMOS circuits, an ECL to CMOS converter was designed. Because the maximum operation frequency of CMOS standard cells is 1 GHz, as specified by the foundry, the demultiplexer was divided into a 8:32 CMOS demultiplexer with a maximum operation frequency of 312.5 MHz, and a 1:8 ECL demultiplexer. IV. CIRCUIT DESIGN The key circuits of the deserializer presented in this paper are the 1:8 ECL demultiplexer, the ECL to CMOS converter
and the ECL clock distribution network because these circuits were implemented full-custom due to the high operation frequency. These circuits are therefore firstly explained in detail in this section. Fig. 6 shows the whole structure of the 1:8 ECL demultiplexer, with the clock distribution network and the ECL to CMOS converters.
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Fig. 8. Schematic view of the 2:1 ECL multiplexer.
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Fig. 6. Structure of the 1:8 ECL demultiplexer with the clock distribution network and the ECL to CMOS converters.
A. 1:8 ECL Demultiplexer The high-speed 1:8 ECL demultiplexer is based on a tree structure composed of three stages of 1:2 ECL demultiplexers, as shown in Fig. 4. Each 1:2 ECL demultiplexer (Fig. 7) was designed using two D-flip-flops and a latch which were designed using a 2:1 ECL multiplexer as main cell. The latch was formed by connecting the output of the 2:1 ECL multiplexer to one of the inputs whereas the D-flip-flop is a master-slave register formed by two latches. D
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Fig. 9. Schematic view of the ECL buffer.
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Fig. 7. Structure of the 1:2 demultiplexer.
In Fig. 8 the schematic of the 2:1 ECL multiplexer is shown. It consists of two differential pairs for the input signals, another differential pair for the selection signal, two class A output stages with two different DC levels and three degenerated current mirrors. This structure has three transistor levels, which was a problem because of the high base-emitter voltage of the bipolar transistors (aprox. 0.9 V) and the low available voltage supply (3.3 V). In order to recover the output signals, two buffers were placed between each stage. The ECL buffer (Fig. 9) is based on a differential amplifier whose emitter resistances were reduced in order to increase DC current and, therefore, minimize fall and rise times of high-frequency clock signals.
B. ECL Clock Distribution Network The different clock signals required for the 1:8 ECL demultiplexer circuit were generated from the 2.5 GHz external clock signal through an ECL clock distribution network, whose structure is composed of static frequency dividers based on D-flip-flops and buffers. The buffers and registers used for the ECL clock distribution network have the same structure as in the 1:8 ECL demultiplexer. C. ECL to CMOS Converter The ECL to CMOS converter must be able to transform a low amplitude differential signal into a 0 V to 3.3 V 50% duty cycle asymmetric signal used for clock generation. Some ECL structures were designed for the ECL to CMOS converter but no one showed a good behaviour, so MOS transistors were used to implement the final version of the ECL to CMOS converter. The ECL to CMOS converter is a BiCMOS circuit formed by a differential amplifier and a CMOS level shifter. In Fig. 10 the structure of the ECL to CMOS circuit is shown. The differential amplifier has a high voltage gain, which was achieved by increasing collector resistances and
by minimizing emitter resistances. The output signal obtained from the differential amplifier is then introduced to the CMOS shifter proposed by Embabi [7] in order to adjust high and low levels to 3.3 V and 0 V respectively. RVCC
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Fig. 10. Structure of the ECL to CMOS converter.
D. 8:32 CMOS Multiplexer and CMOS Clock Distribution Network The 8:32 CMOS multiplexer is also based on a tree structure. The three different clock signals required on this stage were generated by a CMOS clock distribution network formed by static dividers and buffers. These two circuits were designed using different models of standard cells. In particular, low power models of buffers and registers were used for the clock distribution network whereas high load drive models were allocated at the end of lower speed stages because of the high number of driven cells. E. Techniques to reduce power consumption Most of the cells used in the design of the 1:32 deserializer proposed in this paper were previously designed for a 2.5 Gbps serializer [8]. Similar techniques were used in the design of the serializer because high-speed stages were implemented with bipolar transistors whereas standard cells were used in low-speed ones. However, only two stages were designed in ECL while the number of stages based on bipolar transistors in the deserializer is three. Because of this reason, power consumption of the deserializer was extremely high at the beginning and therefore several techniques were applied in order to minimize it. As said before, latches and flip-flops were based on a 2:1 ECL multiplexer which was designed to work at 2.5 GHz. Because the deserializer has a tree structure, most of the cells work at lower frequencies. Consequently, ECL cells were modified in order to work properly at the required frequencies without disregarding functionality. In order to minimize power consumption of the whole ECL circuit, power consumption of each cell was measured. Table I summarizes the results concerning power consumption simulations.
TABLE I POWER CONSUMPTION RESULTS OF THE ECL CIRCUIT Number Power of cells Power consumption per cell Cell consumption in the model per cell unit circuit Latch 3.40 mW 7 23.80 mW 9.28 % Buffer 5.80 mW 19 110.20 mW 42.98 % Register 6.80 mW 18 122.40 mW 47.74 % Total power consumption of the ECL circuit 256.40 mW
The 1:8 ECL demultiplexer and the clock distribution network are formed by 19 buffers, 18 D-flip-flops and 7 latches that have a power consumption of 256.40 mW. Because power consumption of the latches represents only 10 % of the total power consumption, it wasn’t worth to modify them and consequently efforts were concentrated on studying buffers and D-flip-flops. Previous works [8] demonstrated that power consumption is determined by three factors: current value, circuit gain and transistor size. Current is controlled by the reference stage and mirror emitter resistances. If no modification of the reference stage is desired, current can only be reduced by increasing emitter resistances. As far as gain is concerned, collector resistances are responsible for reaching high values. Finally, little transistors dissipate less power than big ones. Once all factors related to power consumption are deeply studied, modifications of the cells can be easily done. Nevertheless, the fact that cells are already physically implemented involves limitations on the possible changes. Fig. 11 shows the physical implementation of the buffer and the D-flip-flop.
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(b)
Fig. 11. Layout of the buffer (a) and the D-flip-flop (b).
It can be clearly observed in the above figure that the buffer allows much more modifications than the D-flip-flop because there is more space available. Regarding to the power reduction techniques previously described, new resistances can be added in the buffer. However, this is not possible in the case of the D-flip-flop unless resistances are placed on both sides. Nonetheless, transistor size reduction can be easily carried out on both circuits. After having done these modifications, power consumption of the circuit decreases to 202 mW which means that approximately 20 % of the power consumption was saved.
V. PHYSICAL IMPLEMENTATION The technology used to implement the designed 1:32 deserializer presented in this paper was 0.35 µm S35D4M5 SiGe BiCMOS technology from Austriamicrosystems, which provides four metal layers and four poly layers. The 1:32 deserializer is a BiCMOS circuit that was designed using standard cells and bipolar transistors. The standard cells’ based 8:32 demultiplexer and clock distribution network were implemented with the automatic synthesis CAD tool Silicon Ensemble whereas ECL circuits and the CMOS shifter were designed full-custom with Cadence Virtuoso. Once both modules were designed and verified, the interconnection of the two circuits was done with Cadence Virtuoso. Fig. 12 shows the layout for the physical implementation of the 1:32 deserializer. It can be seen that the block based on standard cells is located at the right whereas the ECL circuit was arranged at the left. Among the considerations taken into account during the physical implementation process, a guard ring round the ECL block was introduced in order to isolate it from the CMOS circuits. In addition, the CMOS level shifters were located far away from the other full-custom parts in order to minimize noise. However, the most difficult task of the physical implementation was the clock tracks’ routing of the fullcustom layout. In this kind of circuits, it is extremely important that clock signals arrive at the destination at the same time in order to assure that data are transmitted simultaneously. If two tracks of the same signal don’t have the same length, the delay introduced by one of them will be higher than the other one and therefore data will be registered at different time steps. In case of high-speed circuits, the difference between the two delays can be significant. As far as the presented 1:32 deserializer is concerned, the critical point is the 1.25 GHz clock signal routing because it is the highest frequency that has to be distributed to different cells. For that reason, the 1.25 GHz clock tracks must have the same length and the best way to achieve it lies in place the destination cells (REG01 and REG02) at the same distance from the clock generating cell (REG0). Next stages are not so critical because operation frequency is below 1 GHz. Nevertheless, the placement of the 625 MHz destination cells (REG03, REG04, REG05 and REG06) was also thought carefully in order to avoid long distances from the clock origin (REG1). VI. SIMULATION RESULTS Technology’s manufacturer specifies ten different corner cases in which all circuits must be previously simulated before being fabricated. All the different simulations used to verify the functionality of the circuit presented in this paper were run on these ten corners in order to ensure optimal experimental results. Several simulations were run in order to verify, not only functionality, but also tolerance towards variations of the operation conditions. Functionality was verified with random simulations run at 2.5 GHz. Fig. 13 shows the pulse waveforms of the output signal for the ten corner cases. It
can be seen that all signals have accurate amplitude as well as square waveform.
Fig. 12. Final layout of the 1:32 deserializer.
After verifying functionality, different values for voltage supply were used in order to determine the functional supply voltage range of the circuit. It was demonstrated that the 1:32 deserializer can work properly with 3.3 V and 3.4 V supply. Lower voltage values can not be used because of the high base-emitter voltage of the bipolar transistors. By applying higher voltage supplies, it was observed that the amplitude increases and therefore transitions from high logic level to low logic level take a longer period of time. Consequently, some data are not well registered. It was also analyzed the behaviour of the circuit at different operation frequencies with simulations run for the ten corners at higher frequency values: However, due to the power consumption optimization, there were some errors at 2.75 GHz in the two slowest corners. Table II summarizes the most important characteristics of the 1:32 deserializer working under typical conditions at 2.5 GHz with 3.3 V supply. VII. CONCLUSION A low power 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology is presented in this paper. In order to minimize power consumption, slower stages of the proposed deserializer were designed using standard cells. For highspeed circuits ECL structures were used. The combination
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of CMOS circuits and bipolar transistors required the design of an ECL to CMOS converter. TABLE II SIMMULATION RESULTS SUMMARY Technology Supply Voltage Input Transfer Rate Output Transfer Rate ECL Power Consumption CMOS Power Consumption Total Power Consumption Rise Time Fall Time High Pulse Width (50 %) Low Pulse Width (50 %) High Pulse Width (90 %) Low Pulse Width (90 %) Total Area
AMS 0.35 µm SiGe BiCMOS 3.3 V 2.5 Gbps 78.125 Mbps 278.1 mW 27.3 mW 305.4 mW 223.3 ps 140.5 ps 12.800 ns 12.800 ns 12.609 ns 12.635 ns 700 µm x 1045 µm
This design represents the first implementation of a 2.5 Gbps deserializer with 32 outputs in SiGe to the best of author’s knowledge. Because of the low power consumption it can be used for several applications like SONET OC-48, Infiniband, and Fibre Channel.
Canarias, S.A” (UNELCO) under INNOVA Project of the “Fundación Canaria Universitaria de Las Palmas” (FULP). REFERENCES [1]
[2]
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ACKNOWLEDGMENT This work was partially supported by the Spanish Ministry of Education and Science (MEC) under project TEC2005-08138-C02-01/MIC and by “Unión Eléctrica de
[8]
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