A practical EPROM-based extended memory code conversion system

Microelectronics Journal, 26 (1995) 621-626

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A practical EPROMbased extended memory code conversion system G. Bhanumurthy, T.V. Chandrasekhar Sarrna, C. Aneel Kumar and S. Malik Basha Department of Electrical and Electronics Engineering, S. V. University College of Engineering, Tirupati 517 502 (A.P.), India

The design, fabrication and testing of a practical code conversion system is presented. This system is an example of an Algorithmic State Machine or a Finite State Machine: the standard design procedure for such machines is briefly reviewed. Our system facilitates 14 specific types of chosen code conversions, grouped as direct, derived and additional. The system is based on the 16 k bit EPROM 2716 chip: to cover the entire operation envisaged, the system memory is expanded to nearly 28 k bits by including flip-flop, multiplexing and additional ROM units. LEDs are used to indicate the system input and output status. The results of testing of the unit are reported. The design principles and practical implementation of the system described may be applied to similar systems or machines in a wider context.

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Specification o f the problem. Translation o f this specification into an overall flowchart. Development o f a system block diagram, including signal definitions. Implementation o f each block in the diagram.

Specification o f the problem (step 1) demands a code conversion system facilitating conversions involving the following number systems or codes: binary; decimal; hexadecimal; B C D and Gray.

1. Introduction his paper presents a practical alphanumerical code conversion system, constructed on the basis o f the general sequential digital model k n o w n as an Algorithmic State Machine (ASM) [1] or as a Finite State Machine (FSM) [2].

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The design procedure for an A S M consists o f the following steps [1]:

0026-2692/95/$9.50 ,© 1995 Elsevier Science Ltd

A code conversion flowchart (step 2) is presented in A S M chart form in Fig. 1, from which two broad categories o f specific code conversion made available by this system can be distinguished - - direct conversions and derived conversions. The direct conversions are the following: (i) binary to grey; (ii) B C D to decimal; (iii) binary to hex; (iv) binary to B C D ; (v) grey to binary and (vi) B C D to binary. The

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G. Bhanumurthy et al./EPROM-based code conversion system

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derived code conversions are the following: (vii) binary to decimal; (viii) grey to hex; (ix) grey to BCD; (x) BCD to grey; (xi) BCD to hex; and (xii) grey to decimal. The scheme shown in Fig. 1 may be modified according to specific requirements.

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A block schematic of the code conversion system (step 3) developed through the use of R O M , multiplexers and flip-flops is presented in Fig. 2. The E P R O M used in this system is the 2 kB E P R O M 2716. The normal capacity of the E P R O M 2716 (2048 × 8 = 16k bits) is extended to nearly 28 k bits as required by the system. The extension is achieved by the use of flip-flops and the multiplexing units. The additional R O M unit shown in the figure controls the hexadecimal and decimal display, discussed below. The various blocks and interconnections (step 4) shown in Fig. 2 are implemented by the appropriate chips and other necessary discrete components, producing the practical system illustrated in Fig. 3. The system may be broadly divided into the following subsystems: (1) system inputs (A7 to A0 and $2 to SO); (2) E P R O M unit; (3) flip-flops and multiplexer unit; (4) additional R O M and (5) system outputs (07 to O0 and D1, DO). LEDs are used for inputs 'A' and 'S' and for 'O' outputs, whereas 7-segment LEDs are used for 'D' outputs. The power supply required by the system is 5 V 4- 5%, with a maximum current of 1 A. The system logic levels '1' and '0' correspond to +5 V and ground respectively.

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Fig. 1. Code conversion flowchart.

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2.1. System inputs There are two types of system inputs, viz. A7, ..., A0 and $2 to SO, as shown in Fig. 3. A7, ..., A0 constitute an 8-bit (1-byte) code word (binary or grey or BCD ): $2, $1 and SO

Microelectronics Journal, Vol. 26, No. 6

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G. Bhanumurthy et al./EPROM-based code conversion system

comprise the 3-bit select code input. By this arrangement any one of eight sets of code words can be chosen, with each set consisting of 256 one-byte code words. 2.2. EPROM unit The E P R O M 2716 used in this system (U3), as shown in Fig. 3, is a 16 k bit (2048 x 8) ultraviolet-erasable CMOS P R O M and a 24-pin (11 input, 8 output, 2 supply, 1 ground, 1 chip enable, and 1 output enable) DIP. The various modes of operation of this E P R O M are Read, Standby, Program, Program Verify and Program Inhibit: in the present system it is operated in Read mode. For further details reference should be made to the manufacturer's data book [3].

O f the 11 input pins, pins 19, 22 and 23 are connected to $2, $1 and SO respectively, while pins 1 to 8 are used for code word input. The direct code conversions (i) to (vi) listed above are stored manually in the E P R O M using the first six selection combinations of $2, $1 and SO viz. 000 to 101. The remaining two combinations, 110 and 111, are reserved for two other code conversions. In this system, selection 110 is used for Two's complement of input binary sequence, and 111 for certain ASCII characters. The E P R O M program for the eight code conversions mentioned above is written according to the usual procedure [4] and is stored in the E P R O M using a Zeta-85 Micromaster IIA kit [5]. The programming required for this system is voluminous, and debugging is eased considerably by the erasability of EPROM. 2.3. Flip-flop and multiplexing units The flip-flop unit (U4, U5), shown in Fig. 3, comprises two Quad-D flip-flop chips (SN74175). Each of the eight output pins of the E P R O M (9 to 11 and 13 to 17 ) is connected to each data input pin of the eight D flip-flops. The data available at the input pin of each flip-flop is transmitted to the flip-flop output by an exter-

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nal, manually-operated electronic pulser: the activity of the clock pulse is indicated by an LED. The flip-flops can be cleared by connecting the 'Clear' terminal to ground through an SPDT switch as shown; in normal operation the switch is connected to +5 V, which is indicated by the associated LED. The output status of the flip-flops is indicated by LEDs B 7 , . . . , B0. The multiplexing unit (U1, U2) consists of two Quad 2-to-1 multiplexer chips (SN 74157) (Fig. 3). Each multiplexer has two input channels, designated 'A' (pins 2, 5, 11 and 14) and 'B' (pins 3, 6, 10 and 13), and one output line, 'Y' (pins 4, 7, 9 and 12). Connection of the input channels 'A' and 'B' to the output line is governed by the value of the Mux control input, 'M': '0' or '1' respectively. The system inputs A 7 , . . . , A0 are connected to the 'A' channels of the multiplexers, and B7, ..., B0 are connected to the 'B' channels. Bits of like significance in the byte (A7 and B7, ..., A0 and B0) are connected to a single multiplexer. Each of the outputs of the eight multiplexers is connected to pins 1 to 8 of the EPROM. Either of the bytes A 7 , . . . , A0 and B 7 , . . . , B0 is input to the E P R O M depending on the status of 'M', indicated by an LED as shown. The purpose of including this unit in this system, as outlined above, is to realise the six code conversions designated (vii) to (xii) in the Introduction, which are not handled by the E P R O M alone. For example, in conversion (viii) (Gray to BCD), the Gray code is first converted to binary by direct conversion (v). The binary E P R O M output is then stored in the flip-flops. Next, the stored code is transmitted through the SPDT switch, 'M', as input to the E P R O M to obtain BCD code by conversion (iv). Other derived conversions are achieved by a similar procedure. However, the last of the derived conversions, (xii) (Gray to decimal), involves one additional operation (Gray to binary, binary to BCD and finally BCD to decimal).

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2.4. Additional ROM Included in the system is an additional R O M unit (Fig. 3), functioning as a decoder followed by an encoder. The decoder is a 4-to-16 line decoder (SN 74154) (U6). The four-bit decoder input address (at pins 23, 22, 21 and 20) is fed from the upper nibble of the E P R O M input (at pins 1, 2, 3 :and 4 of 2716). Depending upon this input address (0000, 0001,..., 1111), one of the sixteen output lines of the decoder is excited by going logic 'low', while the other, unexcited lines are rcLaintained 'high'. These 16 decoder outputs are inverted by employing three hex inverter chips (SN 7404) (U7, U8, U9) as shown. The sixteen outputs of the inverter form the inputs to a 16-to-7 line rectangular diode (1N4007) matrix encoder. The encoder has been designed so that characters 0, 1,..., 9 andt A, B,..., F are displayed on a 7-segment common-cathode LED display (LTS543R), followir,g standard procedure [6]. The purpose of this R O M unit is to enable the display of 10' place in decimal and 16' place in hexadecimal, whereas 10 ° and 16 ° places are taken care of by the EPROM.

Alternative methods may be devised, but these entail several display devices instead of simply two (as shown in Fig. 3). In one solution avoiding the additional R O M , the hexadecimal display TIL 311 (which is very expensive) can be used; for decimal display, 7-segment LEDs in conjunction with BCD to 7-segment decoders are required. This consideration led to the use of R O M in the present system as a relatively inexpensive option. 2.5. System outputs There are two types of system outputs, viz. LEDs O 7 , . . . , O0 and 7-segment LED displays D1 and DO (Fig. 3). The output codes, which are streams of bits (binary, Gray and BCD), are read from 0 7 . . . . . O0. The character outputs (decimal and hex) are read from D1 and DO. In addition to these five codes (shown in Fig. 1), Two's complement ~nd ASCII available on the

E P R O M are displayed, the former using O 7 , . . . , O0 and the latter using DO. Here O 6 , . . . , O0 are connected to the 7 segments of DO, and 0 7 is connected to the decimal point of DO, in order to double the number of distinct characters that can be displayed in ASCII. 3. Results and c o n c l u s i o n s

All the above units were assembled on a PCB and interconnected as per Fig. 3 with an appropriate and convenient layout. (Technical details of the various constituent chips, other than EPROM, can be obtained from the manufacturer's data book [7].) The inputs 'A' and 'S' are connected to +5 V (logic '1') and ground (logic '0') through SPDT switches. A single power supply energises all chips. The output is read from 'O's and 'D's as described previously. All 14 code conversions (direct, derived, Two's complement and ASCII) were tested in the laboratory after developing and fabricating the system on a PCB. The appropriate 'O's and 'D's were read, depending upon the code conversion under test. The testing successfully covered the entire possible range of the system. On the basis of the practical design ideas presented, future designers of similar systems can upgrade this model by economies of space and cost and by incorporating additional conversions.

Acknowledgement The authors express their grateful thanks to the Editor, Communications in Instrumentation, Central Scientific Instruments Organisation (CSIO), Sector 30, Chandigarh 160 020, India, for originally publishing this article (Vol. 1, No. 4) and for granting permission for its republication in MicroelectronicsJournal. The authors also wish to thank the Director of CSIO for his encouragement and support.

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G. Bhanumurthy et al./EPROM-based code conversion system

References [1] C.A. Wiatrowski and C.H. House, Logic Circuits and Microcomputer Systems, Mc-Graw Hill International Book Company, 1980, pp. 28, 35-36. [2] Z. Kohavi, Switching and Finite Automata Theory, 2nd ed., Tata Mc-Graw Hill Publishing Co. Ltd., New Delhi, 1978, pp. 280-281,291. [3] CMOS Data Book, National Semiconductor Corporation, Santa Clara, California, 1984.

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[4] S.M. Patkar and P.P. Kelkar, Universal digital function generator, Electronics For You, New Delhi, October 1989, pp. 101-107. [5] User's Manual - - Zeta-85 Micromaster IIA, Zeta Micro Systems, Madras-41, India. [6] J. Millman and A. Grabel, Microelectronics, 2rid ed., Mc-Graw Hill, New York, 1987, pp. 286--289, 299301. [7] The TTL Data Book, Vol. 2, Texas Instruments, Dallas, Texas, 1985.