A single-chip 900 mhz spread-spectrum wireless transceiver in 1 |ìm cmos-part i

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

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A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in 1- m CMOS—Part II: Receiver Design Ahmadreza Rofougaran, Glenn Chang, Student Member, IEEE, Jacob J. Rael, Student Member, IEEE, James Y.-C. Chang, Maryam Rofougaran, Member, IEEE, Paul J. Chang, Masoud Djafari, Jonathan Min, Edward W. Roth, Asad A. Abidi, Fellow, IEEE, and Henry Samueli, Member, IEEE

Abstract— A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the data decisions. The received signal is dehopped when it is downconverted. The cascade noise figure is 8.6 dB, and the cascade IIP3 is 08.3 dBm. In active mode, the receiver takes 120 mA from 3 V.

I. INTRODUCTION

AND

SPECIFICATIONS

T

HIS paper deals with the receiver section of an integrated frequency-hopped spread-spectrum transceiver operating in the 902–928 MHz industrial, scientific, and medical (ISM) band (Fig. 1). The transmitter section is described in the preceding companion paper [1]. The receiver is designed for quarternary frequency-shift keying (4-FSK) modulation, communicating a maximum data rate of 160 kb/s at a symbol rate of 80 kHz. The peak signal energy in the modulated baseband spectrum concentrates in the frequency range of 80–160 kHz, while relatively little energy lies at dc (Fig. 2). This enables use of a direct-conversion or zero-IF receiver [2]. This architecture eliminates all IF bandpass filters and therefore is the best candidate to implement a fully integrated single-chip receiver. With reference to Fig. 1, an LNA drives two mixers, which downconvert the received signal with quadrature phases of an LO synchronized to hop in frequency with the same code as the sought user. The agile frequency synthesizer in the transmitter section synthesizes this hopping LO. Thus, this receiver downconverts and dehops the received spread-spectrum signal in one set of mixers. An integrated low-pass filter selects the desired channel, and following that, a limiting amplifier boosts the received signal to drive a correlating digital detector. The receiver detects input signals as low as 1 V.

Fig. 1. Block diagram of receiver section.

Fig. 2. Spectrum of 4-FSK modulation by pseudorandom data.

II. CIRCUIT BLOCKS The various blocks of the receiver are described in depth in the following sections. In those cases where a prior journal publication exists describes a certain block, the text here is brief and summarizes only the salient features. A. Low-Noise Amplifier and Mixers

Manuscript received September 3, 1997; revised January 5, 1998. The authors are with the Integrated Circuits & Systems Laboratory, Electrical Engineering Department, University of California, Los Angeles, CA 90095-1594 USA. Publisher Item Identifier S 0018-9200(98)02398-1.

The fully differential LNA consists of two common-gate FET’s with 30-nH on-chip inductor loads (Fig. 3). It has been shown elsewhere [3] that when a 3-dB LNA noise figure is acceptable, the common-gate topology very conveniently provides a 50- input match without resorting to inductor

0018–9200/98$10.00  1998 IEEE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

Fig. 4. Block diagram of SC channel-select filter in context of receiver front-end.

Fig. 3. Differential LNA, downconversion mixer, and mixer buffer.

degeneration [4]. The ratio of the load inductor impedance at 900 MHz to 50 sets the LNA gain. If the loss in the inductor is modeled by a series resistor and the capacitance defines the tuned circuit at the drain, then it may be shown [3] that the voltage gain is Gain

(1)

is the FET unity current-gain radian frequency. where Thus, using large metal-2 spiral inductors whose nH [3], and with the NMOS biased at of is about 4 GHz [3], a voltage gain of 20 dB 0.35 V where centered at 915 MHz is obtained. This is the voltage gain from the LNA input terminals when it is exactly matched to a 50source,1 to the load inductors driving an on-chip capacitive load. Unlike standalone LNA’s, this circuit finally drives a capacitive load, not 50 A dc feedback loop sets the common-gate bias voltage VG, and VC adjusts the LNA output common-mode level to mixers. Each doubleenable direct coupling to the and balanced mixer consists of a linear transconductor, comprising two common-source FET’s, followed by four commutating switch FET’s driving 1-k polysilicon resistor loads (Fig. 3). The PFET pull-up current sources are of large gate area to lower their input-referred flicker noise, which directly adds to the RF input signal downconverted to zero IF. The voltage conversion gain of the mixer is nominally 0 dB. The cascade double-sideband noise figure2 of the LNA and one mixer is 3 dB referred to the 50- input source. The total input IP3 is about 8 dBm. This LNA drains 11 mA from a 3-V supply, and each mixer drains 2.5 mA. B. Channel-Select Filter The preselect filter after the antenna passes the entire ISM band (Fig. 1), which is amplified in the broadly tuned LNA and downconverted and dehopped in the mixers. A switchedcapacitor (SC) filter [5] then selects the desired user’s channel, which is now centered at 0 Hz (Fig. 4). The specifications on channel-selection require a low-pass filter with a passband 1 In

the case of an imperfect match, the LNA insertion gain is defined as the ratio of the signal voltage on the load inductor to half the voltage of the 50- source driving the LNA input. 2 DSB NF is the appropriate measure here because a direct conversion receiver keeps the images of signal and noise separate in quadrature channels. See [3] for a more detailed justification.

edge at 230 kHz, a stopband edge at 320 kHz, and a stopband loss of 50 dB to suppress the adjacent channel [5]. This is realized in a sixth-order elliptic filter, implemented here as a cascade of three biquadratic sections (Fig. 4). The clock frequency of the elliptic filter is limited to 14.3 MHz so that the spread in values of the filter capacitor does not grow prohibitively. A prefilter clocked at a higher rate must now reject the channels at multiples of 14.3 MHz away from the desired channel, which will fall in the images of the elliptic filter’s passband. A second-order Butterworth low-pass 14.3 MHz) is used as this clocked at 57.2 MHz ( 4 prefilter. In addition, the off-chip RF filter attenuates non-ISM band signals 57 MHz away from the desired channel by at least 15 dB. Therefore, the cascade response of the RF filter, SC prefilter, and SC main filter is to provide a stopband loss of at least 52 dB, typically 65 dB, extending from 320 kHz to well beyond 60 MHz. The active filter very often contributes the largest noise of all the building blocks in an integrated direct-conversion receiver. This filter’s input-referred noise is lowered by strategically distributing gain in the first few biquads. Although gain in the filter compromises its input IP3 (IIP3) because a smaller input signal now saturates the last op amp in the cascade, it does lower noise. With a total voltage gain of 16 (24 dB) distributed as shown in Fig. 4, the filter’s input-referred voltage noise spectral density is 40 nV Hz The balanced filter uses a total capacitance of 200 pF and drains 7 mA from 3 V. For two input tones located 1 MHz in the stopband whose intermodulation product falls in the filter passband, the IIP3 is 7 V (rms). The SC filter samples the output of the mixer buffer (Fig. 3), whose role is discussed in a later section. The on-chip 30-pF capacitor differentially connected at the buffer output limits the noise bandwidth to about 1 MHz. Otherwise, wideband noise at the mixer output will alias into the filter passband after sampling and raise the noise figure of the filter as well as the receiver. C. Limiting Amplifier and RSSI The filter output is directly connected to a limiting amplifier. This circuit also synthesizes a logarithmic measure of the input voltage [6]. The amplifier consists of a direct-coupled cascade of seven differential pairs, each with a voltage gain of 12 dB (Fig. 5). The 84-dB gain is so large that in the absence

ROFOUGARAN et al.: SINGLE-CHIP 900-MHz SPREAD-SPECTRUM WIRELESS TRANSCEIVER IN 1- m CMOS—PART II

Fig. 5. Limiting amplifier and logarithmic received signal-strength indicator (RSSI). Individual circuits shown for input stage, seven core amplifiers in cascade, and rectifier.

Fig. 6. Measured log conformity at RSSI output over 80-dB input signal range and variation in group delay through limiting amplifier.

of an input signal, the amplifier output limits on its own noise. Full-wave rectifiers, each consisting of two unbalanced differential pairs [7] with a unidirectional current output, tap each differential pair, and their outputs are summed in a 10-k on-chip resistor. This architecture implements the successivedetection algorithm [8], and the resulting near-logarithmic output voltage is used to indicate the strength of the received signal (RSSI). Measurements on a standalone prototype verify that over the 80-dB range of input signal, the RSSI output conforms within 1 dB to an ideal logarithm (Fig. 6). In a dc-coupled receiver, offsets, which are typically tens of millivolts, will overwhelm the received signal, which is only fractions of a millivolt in the baseband section, and pin the limiting amplifier output to one extreme or the other. DC feedback is therefore mandatory for proper operation. The feedback loop around this limiting amplifier suppresses offset added by the mixer or filter, or which appears within the stages of the limiting amplifier. A low-pass filter in the feedback loop measures the average value of the differential limited output, and a differencing stage subtracts this off from the differential input (Fig. 5). Although the limiting amplifier is nonlinear, the action of the dc suppressing feedback may

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be roughly understood with a superposition argument. The negative feedback loop gain is 84 dB at dc, and the dominant pole in this loop, set by the off-chip and , is chosen to roll off the loop gain to below 0 dB at the lowest signal frequency, 80 kHz. Suppose first that a small input signal is applied to the limiting amplifier, such that all the limiting amplifier stages operate in the linear region. Then the linear feedback loop suppresses the dc component by 84 dB with respect to the signal, irrespective of dc accompanying the input signal or arising within the limiting amplifier. If the signal is larger, it will drive the later stages of the amplifier into clipping. At first sight it may seem that this lowers the relative suppression of the dc offset, because fewer stages in the cascade contribute linear amplification. However, now the offset manifests itself in the duty cycle of the clipped output signal. In fact, the tendency of the loop to suppress dc offset remains almost unchanged. It is found by simulation that the output duty cycle with feedback remains the same, whether the input is a sinewave of amplitude 100 V with an added offset of 100 mV, or it is 1 V with the same offset. A deviation from 50% in the duty cycle of the limiter output adversely affects the performance of the following data detector. It lowers the correlation output from the detector over a symbol period, as described in greater detail in the next section, and thus the output SNR. One way to counteract this is by using a large clipping level, because now to overcome a given offset, feedback imbalances the output duty cycle less. Clipping levels of 1 V are used here. Feedback does not affect high frequency noise on the input signal, which randomly modulates the zero crossings of the clipped output. The common-source differential differencing stage at the limiting amplifier input (Fig. 5) can handle input offsets of larger than 1 V. If such a large offset cuts off one input FET, the other FET converts the (now single-ended) input signal to a differential swing at the loads plus an offset, the limiting amplifier senses this, and feedback counteracts the offset through the other half of the differencing input stage. The limiting amplifier’s delay changes with input level (Fig. 6). At small inputs, the slope of the small-signal phase versus frequency sets the group delay. At larger inputs, the last stages in the cascade will slew-rate limit and prolong the circuit delay. When a still larger signal drives all stages into slew-rate limiting, the delay is maximum. The group delay changes by 90 ns over the 80-dB logarithmic range of the circuit, with the greatest rate of change at small inputs. The changing multipath interference pattern of a mobile user, or shadowing and fading, all cause the received signal strength to fluctuate. The group delay characteristic will convert these amplitude variations into phase fluctuations (AM-to-PM conversion) and potentially degrade the SNR in the phase-sensitive FSK detector. Simulations show that even in the unlikely event of a sudden drop of 80 dB in the received signal strength, the AM-to-PM conversion in the limiting amplifier is so small that the detector SNR falls by only about 0.2 dB. The limiting amplifier is designed with a relatively wide small-signal bandwidth of 10 MHz. As the preceding channel-

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

Fig. 7. Digital correlating detector for 4-FSK.

select filter has suppressed adjacent channels by more than 52 dB beyond 320 kHz, the limiting amplifier’s own noise and wideband noise at the filter output occupy the excess bandwidth from 320 kHz to 10 MHz. The extra noise is removed by the correlating detector, which is now described. D. Correlating FSK Detector In principle, FSK data may be fully recovered only from information on the sequence of zero-crossings of the modulated carrier. Each limiting amplifier in the quadrature channels of this receiver drives the downconverted signal to binary amplitude levels, but it preserves the information on zero crossings. Following the limiting amplifier, a frequency discriminator or correlating detector can recover the modulation. The latter bases decisions by correlating the received signal with the entire set of modulation frequencies ( here), and in the sense that it minimizes the noise bandwidth, this is the optimal detector [9]. Because it operates on the 1-b representation of the input signal emerging from the limiting amplifier, the correlating detector is naturally implemented here as a digital circuit [10] (Fig. 7). Its main purpose is to accurately locate the zero crossings of the downconverted received waveform, so it clocks at a large multiple (88 ) of the symbol rate (80 kHz). Thus, the received signal is finely quantized in time (88 levels) but only coarsely quantized in amplitude (two levels). At every clock cycle, an accumulator (digital integrator) increments or decrements the correlation between each 1-b limiting amplifier output and each of the two quadrature phases of locally generated noise-free 80 and 160 kHz square waves. The detector estimates the correlation energy from pairwise sums of the absolute values of the four sets of correlations, and at the end of each symbol period it makes a one-of-four decision. Thus, it seeks the closest match between the received signal and the four possible FSK offsets. The oversampling factor locates the zero-crossing instant to within a quantization error of about 1% of a symbol period. Correlation with a noiseless signal of period corresponds, in the frequency domain, to bandpass filtering around the Thus, the four correlators are bandpass filfrequency and ters centered, respectively, at (Fig. 8). Their 3-dB passband is inversely proportional to the correlation interval, here one symbol period. The bandpass

Fig. 8. Measured frequency response of correlating detector at outputs of integrate-and-dump blocks sensing 80 kHz and 160 kHz. Identical responses are obtained at 80 kHz and 160 kHz outputs.

0

+ 0

+

response also has sidelobes, but the largest lies 10 dB below the main lobe, and as far as noise is concerned, the sidelobes may be ignored. However, these sidelobes have a more serious effect on signals. Consider, for example, the case of a conventionally modulated 4-FSK applied to this detector. The frequency offsets in this case are at and chosen in this way because they are all equally spaced apart on the frequency axis and symmetrical around the carrier frequency. However, after limiting, the fifth harmonic will lie in the largest sidelobe of the correlator of, say, This will induce a spurious response in the centered at correlator, when in fact only the correlator should respond. This degrades the decision SNR at the output. The and in our system were offsets of chosen to avoid this problem, because now at the frequency where the response of one correlator is at a peak, the sidelobes of all the others are at a null. This minimizes the undesirable interaction. A standalone prototype of the correlating detector was first implemented. The circuit includes digital phase-locked loops to track symbol timing and frequency hopping. The operation of this digital baseband subsystem is described elsewhere [10]. The total power dissipation of the digital blocks at 3 V is 4 mW. This circuit takes as its input a 1-b estimate of the received signal from the two limiting amplifier outputs, and it constructs 8-b correlation coefficients over each symbol which are used for all the other functions. No A/D converter is required. However, because of the 1-b approximation, there is an “implementation loss” in detection sensitivity of 1.5 dB from ideal [10]. This implementation loss degrades the sensitivity curve of the detector, specified as bit-error rate versus SNR. It does not affect the noise figure of the receiver, which specifies all the blocks up to, but excluding, the detector. In summary, there are three sets of progressively narrower filters in this receiver (Fig. 9). The digital correlating detector implements, in effect, the narrowest bandpass filter, and this determines the overall receiver noise bandwidth.

ROFOUGARAN et al.: SINGLE-CHIP 900-MHz SPREAD-SPECTRUM WIRELESS TRANSCEIVER IN 1- m CMOS—PART II

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Fig. 9. Progressive filtering scheme in receiver.

III. ISSUES OF CASCADING AND MONOLITHIC INTEGRATION Moving up one level higher than the receiver building blocks in the design hierarchy, the optimization of sensitivity and dynamic range in the cascade of these blocks is now considered. Two definitions of dynamic range (Fig. 10) apply to the radio receiver: spurious-free dynamic range (SFDR), the two-tone in-band signal level above noise which creates intermodulation products equal to the accompanying noise [11]; and the blocking dynamic range (BDR), the ratio of the 1-dB gain compression point to the noise [12], [13]. It should be pointed out that SFDR as defined in some texts [14] subtracts off the desired minimum signal-to-noise ratio from the above definition to take into account the demodulator following the receiver; however, this definition does not seem to be widely used in the literature, and it is not used here. BDR is a measure of resilience to a large out-of-band blocking signal which drives a receiver into compression, thereby desensitizing it to a small desired signal [12]. The two are related as follows (Fig. 10): dB Noise Floor SFDR BDR

IIP3

dB dBm/Hz NF IIP3 Noise Floor dB Noise Floor

BW (2)

where dB is the input power (referred to 50 ) which compresses the gain of a block by 1 dB, and BW is the net receiver noise bandwidth. NF is the receiver input noise figure referred to a 50- source resistor, which at 300 K generates a maximum available noise power density of 174 dBm/Hz. It is important to note that the first approximation in the set of equations above, relating dB to IIP3, usually holds in a circuit with a single-point third-order nonlinearity, that is, when the dominant compressive nonlinearity arises only at one node in an otherwise linear circuit. MOSFET’s are attractive in the RF context because they are only weakly nonlinear, but this also means that several nodes in a CMOS circuit may contribute comparable amounts of nonlinearity. Now it is quite possible that distortion at one node sets the (extrapolated) IP3, while clipping at another sets the dB . In this case, the approximate 10-dB relation may not hold. The overall receiver dynamic range derives from the cascade noise figure and intercept point of the individual building blocks. The correct calculation of the noise figure must take

Fig. 10. Definition of spurious-free dynamic range and blocking dynamic range.

into account the greatly different impedance levels in an integrated receiver. Most on-chip building blocks have a high, mainly capacitive, input impedance, while at the off-chip antenna interface, the nominal receiver input impedance is 50 The cascade noise figure is found by referring all circuit in a reference 50noise sources to the noise voltage off-chip source resistor (Fig. 11). Equivalent noise sources at the inputs of downstream blocks must be divided by the directly adds to . On proper gain. The noise source of block the other hand, the equivalent input noise voltage following the LNA contributes a voltage to the noise figure calculation, where is the voltage gain of block measured between its input and output which defines ports, and the is the incident fraction of . This method of calculation holds the LNA insertion gain even when the LNA is imperfectly matched, see footnote 1. The various noise contributions add as the root-mean square, and with reference to Fig. 11, the cascade noise figure is NF

(3) Cascade intercept point is calculated using well-known formulas [15]; again with reference to Fig. 11 IIP3

IIP3

IIP3

IIP3 (4)

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Fig. 11.

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Various noise sources in cascade of integrated receiver blocks.

where IIP3 is the third-order intercept of block referred to this block’s input and measured in terms of the input signal power dissipated in a reference 50- resistor. The relationship between intercept voltage in dBVrms and this power in dBm dBm 13 dB. is dBVrms In practice, when individually designed building blocks are connected together in an integrated receiver, the required total performance is seldom achieved at first. Usually the cascade dynamic range is not good enough. Then, to improve the dynamic range, either the blocks are redesigned or intermediate gain stages are strategically inserted. Take, for example, the SC channel-select filter used in this receiver. When it is preceded only by the 20-dB voltage conversion gain of the LNA and mixer, the filter’s 40 nV Hz input noise alone implies a receiver NF of 17 dB (calculated by (3) above). This is an unacceptably large receiver NF. The filter’s own noise can only be lowered at a disproportionate (quadratic) expense of current drain and chip area. A better way to lower the contribution of filter noise is to insert an intermediate baseband amplifier after the downconversion mixer. The mixer buffer used here (Fig. 3) consists of two common-source PFET’s acting as a linear transconductor and using polysilicon resistor loads to improve linearity and lower flicker noise. It is prudent to allot gain sparingly in any receiver prior to channel-select filtering, otherwise amplified but unfiltered blocking signals may create large in-band intermod products. However, this gain should be large enough to enable the desired minimum signal to overcome noise of downstream blocks.3 These tradeoffs are illustrated in Fig. 12, which plots this receiver’s cascade noise figure, input intercept point, and SFDR versus buffer gain. It is assumed that the buffer’s load resistor sets the gain, and that the buffer’s input noise and output clipping level remain the same at all gains. With too much buffer gain, the receiver noise figure flattens out to a constant value set by the LNA, but the intercept point falls proportionally. Thus, the overall SFDR suffers. If wide dynamic range is a priority, as it is in this spread-spectrum receiver, then with a buffer gain of 14 dB, the SFDR is within 1 dB of the maximum, and the NF is 8 dB. These values are finally used. However, it is interesting to consider other possible tradeoffs with this flexible buffer, whose gain is adjusted simply by choosing the load resistors. For instance, by choosing a buffer gain of 22 dB, the receiver NF may be lowered to 5 dB, now with an IIP3 of 16 dBm. These two 3 Adding gain in active building blocks of a receiver only lowers the noise contributed by blocks subsequent to the LNA to the cascade NF. It does not lower the equivalent input noise of the LNA itself, which is normally set by the LNA input stage and the impedance matching network.

Fig. 12. Receiver NF, IP3, and SFDR versus mixer buffer gain. Gain used in this receiver is highlighted.

Fig. 13. Signal-level diagram in receiver.

figures-of-merit are sufficient to meet the specifications on a GSM receiver. A signal-level diagram (Fig. 13) best illustrates the cascade effect of the various blocks on the entire receiver. Note that as the signal advances up the cascade, it can tolerate blocks with higher input noise, but up to and including the channelselect filter each block must also be capable of handling a progressively larger signal before the onset of clipping. To enable comparison with data reported in other publications on building blocks, this level diagram specifies the input noise voltage of the blocks, as measured on standalone prototypes, as the power spectral density that voltage would dissipate in a hypothetical 50- reference resistor. The input intercept point is specified in dBm under similar conditions. If need be, these numbers may be converted into rms volts by using dBm 13 dB. the equivalence: dBVrms A direct-conversion receiver must represent the downconverted signal in vector format, to distinguish between the positive and negative frequencies in the selected channel spectrum, which is centered on zero-IF [2]. Following RF amplification in the LNA, the downconverted signal bifurcates into two quadrature channels (Fig. 1). The noise of the two mixers and subsequent pairs of blocks in the two baseband channels is uncorrelated, and each channel’s noise adds to the respective quadrature component of the downconverted signal passing through that channel. Now, if the output voltages at the two channels add at the detector, then the rms noise contributed by the mixers and subsequent blocks is 3 dB larger than the

ROFOUGARAN et al.: SINGLE-CHIP 900-MHz SPREAD-SPECTRUM WIRELESS TRANSCEIVER IN 1- m CMOS—PART II

noise in one channel alone. However, the quadrature (vector) components of the signal also sum to a 3-dB larger value than the signal in one channel. Thus, the combined SNR is the same at the detector input as it is at the output of only one channel. For the purposes of calculating cascade noise figure, therefore, the noise contribution of each building block is accounted for only once. The noise of the entire receiver, as referred to a 50- source resistor, may be predicted by using the individual numbers for noise and gain given in Fig. 13, translating them to noise voltage, and then using the formula in (3)

nV

Hz

where the first term arises from the input-referred LNA noise voltage, the second from the mixer and buffer, and the third from the filter. Finally, this induces a DSB noise figure of 8.6 As expected, it is the active filter noise, the third dB in 50 term in the sum above, which dominates: its noise is equal to the combined contribution of the LNA and mixer. Similarly, the cascade IIP3 is calculated for the entire receiver using measured intercept points for the individual blocks and (5). It is found that the mixer with its buffer limits the receiver’s cascade third-order intercept point to 8.5 dBm. Second-order distortion in the baseband circuits of a directconversion receiver, where the signal is largest, detects the envelope of out-of-band amplitude-modulated interferers to create spurious tones in the filter passband [2]. This is specified by the extrapolated second-order intercept point, IIP2. Ideally, the IIP2 is infinite in a fully balanced receiver, but because of element mismatches it is finite in practice. Systematic mismatches arise from asymmetries in layout, and random mismatches from statistical fluctuations in FET’s and passive components. Cumulative dc offsets in circuits with a balanced topology imbalance the differential signal handling. These various effects cannot be easily predicted. The IIP2 is found by measurements on the finished receiver. All calculations of receiver SFDR use a noise bandwidth of 80 kHz, set by the one bandpass lobe in the correlating detector’s frequency response (Fig. 8). The cascade SFDR is about 76 dB, limited by the 73 dB SFDR of the filter (Fig. 13). This is representative of a good receiver. It is 18 dB lower than the LNA SFDR and 13 dB lower than the SFDR of the standalone front-end, comprising the LNA and mixer [3]. This large difference in dynamic range between the front-end building blocks and the complete receiver cautions against simple extrapolation of the latter’s performance from measurements on the former. It also warns the newcomer to wireless receiver design that the apparently mundane baseband building blocks must be designed with great care if they are not to seriously limit the total receiver dynamic range. IV. EXPERIMENTAL RESULTS The predictions of the total receiver performance are now experimentally verified. Strictly speaking, the total performance of any receiver includes all the blocks up to, but

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excluding, the data detector. Whereas specifications such as noise figure and intercept point are a property of the receiver circuits only, and are independent of channel bandwidth or the modulation scheme, the detector or demodulator is specific to both. Accordingly, this receiver is characterized up to the limiting amplifier output. The limiter is not a detector, merely a broadband nonlinear amplifier which replaces the AGC which would be found in a linear receiver. Noise figure and intercept points cannot be directly measured from the nonlinear output of the limiting amplifier, but must be deduced. This is because with multiple input signals, the limiting amplifier limits on the largest, the well-known “capture effect” in FM. The consequences are somewhat unfamiliar. For instance, suppose the input to the limiter is a large signal and small noise. The limiter captures on the signal, which drives its output to the fixed clipping level, and noise randomly modulates the zero crossings of the signal. When the limiter input SNR is 0 dB or less, the output SNR as measured on a spectrum analyzer is the same as at the input [16].4 This means that as the signal amplitude is pegged on the output spectrum—at 9 dBm in this circuit—the noise floor adjusts itself to the correct SNR. If the input signal level rises but the accompanying input noise remains constant, the opposite trend is seen at the limiter output, that is, the signal remains pegged but the noise floor drops to reproduce the input SNR. The same behavior would be seen in an automatic gain control (AGC) system, which automatically adjusts its gain to keep the output signal always at a fixed prescribed level. The receiver noise figure is deduced from the limiter output spectrum by applying a small, known RF input signal. In response to a 1.2- V rms RF input to the receiver offset by 80 kHz from the fixed LO. Fig. 14 shows the measured limiter output spectrum. Also shown superimposed on this plot is the measured frequency response of the 80-kHz bandpass lobe of the correlating detector which follows the limiting amplifier. The limiter output captures on the input signal, downconverted to 80 kHz. In this case, the rms input noise to the limiting amplifier over its 10-MHz bandwidth is almost equal to the dB. Thus, as input signal; that is, the limiter input SNR mentioned above, the limiter input and output SNR are equal, and as the receiver is linear prior to the limiting amplifier, this must also be the net SNR referred to the receiver input. The limiter output noise is almost flat at a level of 51 dBm/Hz across the detector passband centered at 80 kHz, or 60 dBc/Hz relative to the limited signal tone of 9 dBm. Referred to the receiver input where the signal level is 105.4 dBm (1.2 V), this corresponds to a noise spectral density of 165.4 dBm/Hz. Therefore, the receiver noise figure at the RF input frequency, relative to the incident noise density of 174 dBm/Hz from 50 is 8.6 dB. The noise spectrum at the limiter output clearly follows the low-pass characteristic of the channel-select filter. The noticeable peak in the noise spectrum at 230 kHz, slightly past the filter’s passband edge, can only be explained if it originates in the filter’s high- biquad [5], and this independently verifies that the filter is indeed the dominant source of receiver noise.



4 When the input SNR 1; the aforementioned capture effect improves the limiter output SNR by 3 dB [16].

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(a)

Fig. 15. Measured S of input level.

(b) Fig. 14. Limiting amplifier output spectrum measured with (a) single-tone RF input and (b) zero input. The noise spectral density is in dBm/Hz. The 80-kHz bandpass response of the following correlating detector is shown superimposed in both cases. The receiver responds only to the signal and noise lying in the detector passband.

Below 30 kHz, the receiver noise rises because of flicker noise in the baseband circuits. However, the flicker noise corner lies below the lower cutoff of the correlating detector and will be rejected. The dc nulling loop very effectively suppresses static offsets in the receiver. However, it cannot easily suppress dynamic offsets which appear in every direct-conversion receiver and are of practical concern [2]. Due to various parasitic resonances, the offset produced by self-downconversion of the LO inevitably changes with the LO frequency [3]. As the LO frequency hops through a pseudonoise (PN) code in this receiver, the offset also cycles through a sequence of random values creating a fixed-pattern noise at the mixer output. If the frequency spectrum of this pattern noise lies in the receiver passband, it will raise the noise floor and degrade sensitivity. Measurements show just this effect: with the LO hopping, the low frequency spectrum of the noise floor rises (Fig. 14). Fortunately, when the LO hops through a 54-long PN sequence at 20 kHz, the noise spectrum due to the fixedpattern only rises below the lower cutoff of the correlating detector’s bandpass response, and this is again rejected in the detector. Therefore, we conclude that neither flicker noise in the baseband section nor dynamic offsets degrade the sensitivity of this direct-conversion receiver. A curve of S N versus noise at the limiter output measured across 80 dB of RF input level (Fig. 15) summarizes the overall sensitivity and dynamic range.

+ N versus noise at the limiter output, across 80 dB

Three factors set the minimum detectable signal (MDS): the receiver noise figure, the overall system noise bandwidth, and the signal-to-noise ratio (SNR ) required at the detector for a input for an acceptable bit-error rate, usually 10 voiceband system. So far, only the noise figure has been discussed. One bandpass lobe of the detector determines the noise bandwidth of the entire receiver, and this is roughly about 80 kHz wide (the noise bandwidth is somewhat larger than the 3-dB bandwidth shown in Fig. 8). Regarding the minimum SNR, first recall that each detected symbol in 4-FSK carries two data bits. Therefore, the signal energy must be halved or the noise power doubled for the per-bit signal-toratio. In either noise, referred to in textbooks as the case, this adds 3 dB to the MDS. Theoretically, for 10 BER ratio is about 9.5 dB [9]. Thus, taking using 4-FSK, the into account the referred-input noise floor of the receiver, the 3-dB adjustment for 4-FSK, the noise bandwidth, the minimum SNR, and the 1.5-dB implementation loss of the detector, we arrive at MDS

dBm/Hz dB

dB dB

Hz dBm.

This corresponds to a receiver input voltage of 1.7 V rms from a 50- source. One additional source of improvement remains. Convolutional coding of data improves the receiver sensitivity conservatively, say, by 3 dB, and then the MDS drops to 1.2 V rms. The third-order and second-order intercept points for the linear portion of the receiver, that is, up to and including the channel-select filter, are deduced at the limiter output with a three-tone test. A reference RF tone of a fixed small amplitude is applied so that it downconverts to a frequency in the passband of the channel-select filter. Two other RF tones, simulating near-channel interferers, are also applied so that they downconvert into the filter stopband, but their frequency difference is such that they create intermodulation at in the passband. The latter RF inputs are a frequency swept together in amplitude. The limiting amplifier captures on the larger of the two baseband signals appearing at and . The relative levels of these frequencies at the limiter

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Fig. 16. Third-order intermodulation measurement. (a) Three input tone test conditions and (b) components of the limiter output spectrum versus interferer level.

Fig. 17. Second-order intermodulation measurement. (a) Three input tone test conditions and (b) components of the limiter output spectrum versus interferer level.

output are measured on a spectrum analyzer and plotted versus the swept input amplitude. As expected, when the limiter is capturing on the fixed signal at , the output at grows with the third power of amplitude when it is due to third-order intermodulation, and with the second power when secondorder distortion is responsible (Figs. 16 and 17). and The crossover point where the limiter outputs at are equal (Figs. 16 and 17) contains valuable information. Here, the input levels of the interferers and reference tone, respectively, define abscissas with equal ordinates on the two lines comprising the respective intermodulation plot (Fig. 18). Straight lines of the appropriate slope are passed through these coordinates and extrapolated to find the intercept point. Thus, a total receiver IIP3 of 8.3 dBm and an IIP2 of 24 dBm are deduced. As independent verification, the receiver IIP3 is directly measured at a test pad brought out at the filter input (Fig. 18). This IIP3 of 6 dBm, when cascaded using (4) with the 30 dBm IIP3 of the filter, gives the same total receiver IIP3. Similarly, the IIP2 of the standalone active filter was measured to be 60 dBm [5]. When divided by the 34 dB gain preceding this in the receiver, an IIP2 of 26 dBm is expected, which is almost exactly equal to the measured value. Spurious tones in the receiver LO are measured by synthesizing a constant frequency in the direct-digital frequency synthesizer (DDFS) [1], finding the RF input level at the LO frequency which produces a certain SNR at the limiter, and then for various frequency offsets, finding the input level

which produces the same SNR. If there are no spurs in the LO (and zero phase noise), the receiver will respond to an RF input only at the LO frequency but to no other RF input. The plot in Fig. 19 shows the relative RF input signals required at various offset frequencies from the LO which induce the same SNR as an input at the LO frequency assigned a reference level of 0 dB. No RF filter is used in this measurement. The receiver can stand off very large levels everywhere, except those frequencies where the agile frequency synthesizer produces significant spurious tones. Owing to inadequate gain in the frequency synthesizer, the DAC after the DDFS had to be driven at 2 V full-scale, twice the designed value, to fully switch the receiver mixers. As a result, the spurious levels are almost 20 dB higher than at the designed value of 1 V. This problem is discussed at some length in the companion paper [1]. Nevertheless, in the worst case, which is at an offset of 10 MHz, this receiver can stand off an interferer 43 dB larger than the desired signal. At most other frequencies, we have tested standoff of greater than 80 dB. Again, in a redesign we would expect the worst-case standoff level to improve by 20 dB. There are other mitigating conditions here. Although in a narrowband receiver this might be considered a low immunity to the interferer 10 MHz away, the situation is different in a spread-spectrum system. First, it is generally difficult to achieve the low levels of phase noise and spurious tones in an agile frequency synthesizer that are typical in the stationary LO of a narrowband receiver. Second, averaging in a spreadspectrum system improves the immunity to interferers. For

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Fig. 19. Spurious tones at receiver LO, measured by sensitivity to downconversion. The arrows indicates the relative height of a signal at any given frequency offset, which induces an output SNR equal to the tuned channel at the LO frequency, with reference level of 0 dB.

(b)

Fig. 20. Die photo, with building blocks annotated. Note the special RF input and output pads inside the ring of conventional pads.

V. PHYSICAL ASSEMBLY OF TRANSCEIVER IC (c) Fig. 18. Deducing (a) third- and (b) second-order intercept points from the limiter outputs. (c) Measured IP3 at filter input, as independent verification of receiver IP3.

example, if a large LO spur on a certain hop downconverts a strong narrowband signal 10 MHz away, located, say, just outside the ISM band, then at other hops this signal will no longer lie on the same large LO spur. A receiver which deinterleaves blocks of data across many hops in effect averages out the deleterious effect of one bad “hit” across all the hops. The accumulated offset in the direct-coupled baseband sections of the receiver up to the limiter is deduced from the dc voltage which develops in the off-chip feedback loop. This offset is about 80 mV. DC feedback in the limiter responds to this by creating a 4% imbalance in the output duty cycle, with a negligible loss in detector SNR.

Several graduate student circuit designers produced the transceiver building blocks and their respective chip layouts. These were assembled onto a common substrate (Fig. 20) without much effort at overall compaction. The transmitter blocks occupy two-thirds of the horizontal chip dimension, the receiver blocks the remaining one-third. Twelve square spiral inductors, either 30 or 50 nH in value, are seen on the chip, surrounded by the via holes through which the etchant attacks the fabricated wafer. The circuit is implemented in a doublemetal, single-poly 1- m N-well epi-CMOS process offered by MOSIS (CMOS34/AMOSI). 7.3 mm is distributed The active chip area of 10.5 among the various blocks in the following order (Fig. 21). The four largest blocks are the channel-select filter (used only for receive), power amplifier buffer (transmit/receive), two digital/analog converters (DAC’s) (transmit/receive), and LO (transmit/receive). The DAC’s consume a large area because each DAC cell is liberally spaced from its neighbor to lower the fringing capacitance between cells to a few femtofarads

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Fig. 21. Distribution of (a) active area and (b) current consumption among the various building blocks.

(see [1] for details of the DAC design). In all other blocks, the passive components take up the greatest area. In fact, the 12 inductors consume 40% of the total active area, and the 400 pF capacitors in the two channels of balanced filters consume 15%. In total, the passives consume more than half the chip area. The total current distribution is also broken out among the various blocks (Fig. 21). The PA at maximum output consumes the largest current (20 mA), and the digital circuits comprising the DDFS, when clocked at 100 MHz, drain almost the same dynamic current (18 mA). All other blocks take roughly 10 mA each. The baseband buffers after the DAC’s take 20 mA, and the RF buffers after the frequency synthesizer drain 25 mA in transmit mode, 20 mA in receive mode. This means that the buffer currents account for nearly 45% of the total current in transmit mode and 35% during receive mode. The DAC buffers are designed to deliver a large sinusoidal voltage (0.7 V ptp diff) with very low distortion to a heavy load, consisting of the upconversion mixers, the polyphase filters, and the input capacitance of the RF buffers. In turn, these RF buffers must drive 1.7-V ptp voltages at 900 MHz into the PA input and into the receive mixers. This shows that a monolithic transceiver is not (readily) exempt from the large power consumption which is associated with buffers driving discrete components in a board-level transceiver. Cavities are etched under the inductors on the fabricated die (Fig. 22) with a post-process etch in our lab. The silicon surface of each smoothly etched hemisphere is a miniature concave mirror, which reflects light passing through the transparent oxy-nitride dielectric to give the optical illusion of a shiny ball lying on top of the inductor. The cluster of individual cavities under each inductor coalesce into a large pit roughly as deep as half the inductor size. Eight of these pits in the middle of the chip form a sort of trench. This trench may possibly help to isolate the noise generated in the static CMOS digital DDFS circuits on the upper left of the transceiver from contaminating the microvolt-sensitive circuits in the receiver on the lower right. Unfortunately, this hypothesis cannot be verified by measurement because without etching, the large capacitance under the inductors disables all circuits tuned to 900 MHz. The isolation, whether it is due to these trenches, the balanced circuits, or the highly conductive p -substrate under the thin p-type epi is good enough that there is no evidence in the receive spectrum (Fig. 14) of clock feedthrough from the DDFS, which is clocking at full speed

(a)

(b) Fig. 22. (a) Die photo after etching of cavities under inductors and (b) detailed view of pits under inductor and under long RF interconnects.

during all measurements, nor of the SC filter clocks. Neither, in the presence of more than 122 dB of voltage gain in the receiver baseband circuits, is there any tendency to instability. These pits are useful in another way: they lower the substrate capacitance under long interconnects carrying 900-MHz signals. A case in point is the set of four lines, each 3 mm long, which connect the balanced quadrature frequencyhopped signals from the RF buffer in the transmitter section to the downconversion mixer in the receiver. If they are of minimum width, distributed RC effects result in a low cutoff frequency. If they are widened to lower the resistance, the increased capacitance to substrate heavily loads the RF buffer. The solution is to place the same via holes between pairs of these lines as those surrounding the inductors. Thus, when pits are etched under the inductors, they also appear between the lines (Fig. 22). Similarly, long ac metal runs when running alongside an inductor are routed on the area close to the inductor edge, so after etching they are suspended above an outer pit. With the substrate capacitance now gone, the lines are widened to lower the series resistance that otherwise damps the tuned loads of the 900-MHz RF buffers (see [1]). by The LNA input port is nominally matched to 50 absorbing the capacitance of the RF input pad and the package

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Fig. 23. LNA input matching network and measured versus simulated input return loss.

pins into the matching network (Fig. 23). Actually, the LNA to input resistance is deliberately chosen greater than 50 further lower the input noise figure, as a result raising the . This is a well-known tradeoff between input return loss impedance matching against noise figure. The goal is to achieve a return loss of 10 dB. This is good enough in most cases to obtain a satisfactory response from the external RF prefilter and baluns, each of which is designed to be terminated by 50 . The wideband match obtained from 400–1400 MHz (Fig. 23) is better than the sharply parabolic curve of versus frequency seen often [3]. The packaged transceiver chip is mounted on a four-layer printed circuit board for testing (Fig. 24). Each pair of RF input and output lines from the chip is carefully matched in length to preserve signal balance up to the power splitting/combining baluns. Two chip inductors mounted close to the RF input pins match the LNA input impedance. There are another two chip inductors at the RF output and two chokes for biasing. One large off-chip filter capacitor is connected across the balanced lines in the dc feedback loop of each limiting amplifier. No other critical high-frequency components are required, nor is any shielding called for. Compared to the multicomponent transceivers found in many of today’s wireless devices, this highly integrated transceiver clearly simplifies assembly and testing. VI. DISCUSSION

AND

CONCLUSIONS

This set of papers describes a 900-MHz ISM band spreadspectrum wireless communication system, a new transceiver architecture, and numerous CMOS circuit building blocks which are combined on one chip to implement a highly integrated CMOS radio. The design has evolved from tradeoffs at all levels in this hierarchy. The receiver building blocks illustrate a comprehensive allCMOS approach. The LNA and mixer at the front-end show how to obtain low noise and high linearity in balanced openloop circuits. The SC CMOS channel-select filter handles interferers very well and uses a multirate architecture to obtain a very wide stopband. A limiting amplifier is designed to absorb large dc offset without compromising dynamic range, and it also provides RSSI. The digital correlation detector is nearly optimal for 4-FSK, and at negligible power

Fig. 24. Packaged transceiver mounted on a printed circuit board. Only a few support components are required. TABLE I TRANSMITTER CHARACTERISTICS

dissipation, it implements a valuable bandpass response as well as synchronization from a 1-b limiter output. Building blocks must be inserted with care into the receiver to meet stringent specifications on noise and dynamic range. Unlike baseband analog circuits, downstream blocks in the receiver chain significantly affect overall performance. Cascade effects must be carefully calculated, and the individual dynamic range of the various building blocks must also be adjusted to optimize overall performance. As in the transmitter, all circuits are balanced from the antenna onwards, and wherever possible signals are resolved into quadrature components. The low parasitic coupling between blocks and weak pulling effects, both very desirable attributes in a practical transceiver, are mainly thought to result from the rigorous use of a balanced signal path. On the whole, the high level of integration is found to improve, rather than compromise, receiver performance. Tables I and II summarize the key performance features of the transmitter and receiver. It is felt at the conclusion of this work that with a comprehensive and disciplined approach rooted in the CMOS design art, RF-CMOS is now viable to implement, beyond building

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Ahmadreza Rofougaran, for a photograph and biography, see this issue, p. 533.

Glenn Chang (S’92), for a photograph and biography, see this issue, p. 533.

Jacob J. Rael (S’93), for a photograph and biography, see this issue, p. 533.

James Y.-C. Chang, for a photograph and biography, see this issue, p. 534.

blocks, entirely monolithic, mixed analog-digital radios with competitive performance. REFERENCES [1] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M. Djafari, M. K. Ku, E. Roth, A. A. Abidi, and H. Samueli, “A single-chip 900 MHz spread-spectrum wireless transceiver in 1-m CMOS—Part I: Architecture and transmitter design),” this issue, pp. 515–534. [2] A. A. Abidi, “Direct-conversion radio transceivers for digital communication,” IEEE J. of Solid-State Circuits, vol. 30, no. 12, pp. 1399–1410, 1995. [3] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver,” IEEE J. of Solid-State Circuits, vol. 31, no. 7, pp. 880–889, 1996. [4] R. E. Lehmann and D. D. Heston, “X-band monolithic series feedback LNA,” IEEE Trans. on Microwave Theory & Techniques, vol. MTT-33, no. 12, pp. 1560–1566, 1985. [5] P. J. Chang, A. Rofougaran, and A. A. Abidi, “A CMOS channel-select filter for a direct-conversion wireless receiver,” IEEE J. of Solid-State Circuits, vol. 32, no. 5, pp. 722–729, 1997. [6] S. Khorram, A. Rofougaran, and A. A. Abidi, “A CMOS limiting amplifier and signal-strength indicator,” in Symp. on VLSI Circuits, Kyoto, 1995, pp. 95-96. [7] K. Kimura, “A CMOS logarithmic amplifier with unbalanced sourcecoupled pairs,” IEEE J. of Solid State Circuits, vol. 28, no. 1, pp. 78–83, 1993. [8] R. S. Hughes, Logarithmic Amplification with Application to Radar and EW. Dedham, MA: Artech House, 1986. [9] J. G. Proakis, Digital Communications. New York: McGraw-Hill, 1989. [10] H.-C. Liu, J. Min, and H. Samueli, “A low-power baseband receiver IC for frequency-hopped spread spectrum applications,” IEEE J. of Solid-State Circuits, vol. 31, no. 3, pp. 384–394, 1996. [11] U. L. Rohde, J. C. Whitaker, and T. T. N. Bucher, Communications Receivers: Principles & Design, 2nd ed. New York: McGraw-Hill, 1997. [12] R. G. Meyer and A. K. Wong, “Blocking and desensitization in RF amplifiers,” IEEE J. of Solid State Circuits, vol. 30, no. 8, pp. 944–946, 1995. [13] W. B. Kuhn, F. W. Stephenson, and A. Elshabini-Riad, “A 200 MHz CMOS Q-enhanced LC bandpass filter,” IEEE J. of Solid-State Circuits, vol. 31, no. 8, pp. 1112–1122, 1996. [14] J. Smith, Modern Communication Circuits. New York: McGraw-Hill, 1986. [15] W. H. Hayward, Introduction to Radio Frequency Design. Englewood Cliffs, NJ: Prentice-Hall, 1982. [16] W. B. Davenport, Jr., “Signal-to-noise ratios in band-pass limiters,” J. of Applied Physics, vol. 24, no. 6, pp. 720–727, 1953.

Maryam Rofougaran (M’93), for a photograph and biography, see this issue, p. 534.

Paul J. Chang, for a photograph and biography, see this issue, p. 534.

Masoud Djafari, for a photograph and biography, see this issue, p. 534.

Jonathan S. Min received the B.S. and M.S. degrees in electrical engineering and computer science from the University of California, Berkeley in 1987 and 1989 respectively, and the Ph.D. degree in electrical engineering from the University of California, Los Angeles, in 1995. From 1989 to 1991, he was with Rockwell International, Anaheim, CA, where he was involved in the development of space electronic systems such as a multichannel GPS receiver and satellite transceivers. Currently, he is with Broadcom Corporation, Irvine, CA, working on the design and development of high-speed cable modems. His research interests are in the areas of the wireless/wireline communications systems design, spread spectrum transceivers, digital signal processing, and VLSI architectures for realizing advanced digital communications systems.

Edward W. Roth, for a photograph and biography, see this issue, p. 534.

Asad A. Abidi (F’96), for a photograph and biography, see this issue, p. 534.

Henry Samueli (S’75–M’79), for a photograph and biography, see p. 377 of the March 1998 issue of this JOURNAL.