A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

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A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB Christoph Sandner, Member, IEEE, Sven Derksen, Dieter Draxelmayr, Member, IEEE, Staffan Ek, Voicu Filimon, Member, IEEE, Graham Leach, Member, IEEE, Stefano Marsili, Denis Matveev, Koen L. R. Mertens, Florian Michl, Hermann Paule, Manfred Punzenberger, Member, IEEE, Christian Reindl, Raffaele Salerno, Marc Tiebout, Member, IEEE, Andreas Wiesbauer, Member, IEEE, Ian Winter, and Zisan Zhang

Abstract—A WiMedia/MBOA compliant RF transceiver for ultra-wideband data communication in the 3–5-GHz band is presented. The transceiver includes receiver, transmitter and synthesizer is completely integrated in 0.13- m standard CMOS technology. The receiver uses a feedback-based low-noise amplifier (LNA) to obtain an RF gain of 4 to 37 dB and an overall measured noise figure of 3.6 to 4.1 dB over the 3–5-GHz band of interest. The transmitter supports an error vector magnitude (EVM) of 28 dB up to 4 dBm output power and meets the FCC and WiMedia mask specifications. The power consumption from a single supply voltage of 1.5 V is 237 mW for the receiver and 284 mW for the transmitter, both including the synthesizer.

standard will suffer severely from strong blocking RF signals of WLAN sources at 2.4-GHz and 5-GHz bands. Last but not least, the UWB standard newly requires a fast hopping from sub-band to sub-band which requires the synthesizer to hop by 528 MHz within 9 ns. Special care has to be invested into the synthesizer design in order to meet the spectrum mask imposed by [3]. This work presents a pure CMOS zero-IF transceiver optimized for output power, NF, and low-spur LO generation.

Index Terms—CMLOS, direct-conversion, fast-hopping, RF, transceiver, UWB, wide-band, WiMedia.

The block diagram of the direct-conversion transceiver chip is shown in Fig. 1. The fully differential receiver includes an ESD-protected LNA with high and low gain mode, and a programmable gain amplifier (PGA) with four gain steps to enable optimum receive performance for different signal strengths and interferer scenarios [6]. The schematic of the LNA is presented in Fig. 2. It uses a two-stage amplifier with a complex feedback network to obtain a wideband amplifier with low noise figure, high linearity, and input impedance matching to 100 differentially. Although coil networks [7] can provide a convenient ESD protection with small RF deterioration, for this wideband application the ESD protection was implemented using ordinary pn-diodes with an RF-optimized layout [6]. The LNA provides a switchable gain of 6 dB or 15 dB, implemented by a switchable -network as described in [8]. The LNA is followed by a current-steering PGA with a switchable gain of 3, 3, 6 or 9 dB. The amplifiers are followed by a Gilbert-type down-conversion mixer, which generates quadrature (I and Q) outputs. It is based on a class A-B voltage-to-current converter, a Gilbert Quad, and a load which implements both a current-to-voltage converter and a low-noise filter used to suppress large out-of-band interferer signals. The position of the filter poles (around 500 MHz) can be calibrated digitally by tuning filter capacitors, thus achieving good transition-band and stop-band accuracy in the presence of process variations. The analog I/Q chip interface is driven by an output buffer with a bandwidth of 1 GHz to enable characterization of all receive chain impairments.

I. INTRODUCTION

T

HE RECENTLY evolving wireless ultra-wideband (UWB) standard aims at data rates up to 480 Mb/s in the frequency spectrum of 3 to 10 GHz. The data transmission is based on multi-band OFDM [1], requiring a huge digital processing power. An introduction to the UWB standard and typical transceiver requirements can be found in [2]. UWB aims at short-range high-data-rate communications, e.g., between digital camera, mobile, PC, and laptop, or as a general USB-cable replacement, also called wireless USB. This is clearly a consumer market, which puts a tremendous stress on the chip suppliers for a low-cost single-chip CMOS solution, including integrated power amplifier (PA) and low-noise amplifier (LNA). Although realistic external losses of the antenna filter and duplexer must be added, the required output power of 41 dBm/MHz over a bandwidth of 528 MHz combined with external losses of, e.g., 7 to 9 dB in the antenna filter, balun, Tx/Rx-switch, and low-cost antenna requires a chip output power close to 0 dBm, which is feasible with an integrated CMOS PA. The next crucial point for the performance of the UWB receiver is the RF input stage, which has to provide a low noise figure (NF) and a high linearity, as this wideband Manuscript received April 30, 2006; revised August 26, 2006. C. Sandner, S. Derksen, D. Draxelmayr, S. Ek, V. Filimon, S. Marsili, D. Matveev, K. L. R. Mertens, F. Michl, H. Paule, M. Punzenberger, C. Reindl, R. Salerno, M. Tiebout, A. Wiesbauer, and Z. Zhang are with Infineon Technologies AG, Development Center, Villach 9500, Austria (e-mail: [email protected]; [email protected]). G. Leach is with Riverbeck, Swindon, U.K. I. Winter was with Riverbeck, Swindon, U.K., and is now with Innovision Research and Technology, Cirencester, U.K. Digital Object Identifier 10.1109/JSSC.2006.884804

II. RECEIVE CHAIN

III. TRANSMIT CHAIN On the transmitter (TX) side, the baseband I/Q analog input signal is converted to current by a highly linear voltage-to-current converter and fed into Gilbert-type folded up-converting mixers. To reduce the LO leakage caused by DC-offset within the mixer stage, a compensation DAC is added and controlled by a serial interface bus. The differential output signal of the mixer is converted to single ended, followed by a programmable

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Fig. 1. UWB transceiver block diagram.

Fig. 2. LNA schematic. Fig. 3. PA implementation.

gain stage and an integrated three-stage power amplifier (Fig. 3). The three required coils in the PA are realized by stacked inductors. Gain-switching is implemented by a capacitive divider with switchable divider ratio, yielding a variable gain range of 30 dB with a resolution of 1 dB for high gain settings. A power detector followed by an ADC with 6-bit resolution is implemented to measure the output voltage of the PA. Taking into account some back-off due to external losses, antenna, and impedance mismatch, this enables cost-efficient control of the actual output power to fulfill TX emission mask requirements without need for additional external components. IV. LO GENERATION To generate the three required LO frequencies for bandgroup 1 of 3.432, 3.960, and 4.488 GHz for a direct-conversion UWB transceiver, we face specific challenges from the specification point of view that are not required for a classical system like wireless LAN. One is the wide LO frequency range, covering basically the whole frequency band of the UWB

transceiver, and the other is the very fast hopping time that should be in the order of nanoseconds. The first issue—having a wideband loop filter path—poses a challenge to the suppression of spurious falling into the RF output signal band. To solve the latter problem—minimal transition time when hopping—an open-loop topology is required. With classical closed-loop phase-locked loop (PLL) structures, such fast hop-times are impossible to achieve. One option is to simply take dedicated PLLs (three in total) to generate each required LO frequency independently and select one by a multiplexer [2]. In terms of spurious performance, this might be the optimum solution, but could come at the cost of increased area and power consumption. A second solution is described in [1], where the principle idea is to use a direct-upconversion topology with single-sideband (SSB) mixer for combining a fixed frequency of 4.224 GHz with a variable low frequency (LF) of 264 MHz or 792 MHz, respectively. The required LF frequencies are generated by dividing down from

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Fig. 4. LO generation.

Fig. 5. LO generation circuit implementation.

the 4.224 GHz. This works well for the 264 MHz, however, for generating 792 MHz, an additional SSB mixer is required in the LO chain to combine 528 MHz with 264 MHz, with high risk to get additional spurs at the LO output. In addition, the harmonics of the divider outputs need quite stringent filtering, since for an ideal rectangular signal, the third harmonic is at only 9.5 dBc. To avoid this additional SSB mixer, we propose to use direct digital synthesis (DDS) as shown in Fig. 4. The proposed implementation includes a PLL, two SSB mixers (for I and Q channels), and a direct digital synthesizer (DDS) approach for generating the LF frequencies. The advantage of this concept is that there is only one SSB mixer stage within the LO generation chain, which eases control of all unwanted spurious generated in the chip. Due to the DDS approach, the second and third harmonics of the LF signal are completely suppressed in comparison to an LF out of divider chains or logic operations. The remaining dominant fourth harmonics is located at a high frequency and can be suppressed through simple passive filtering as depicted in Fig. 5. The reference clock is fed to a PLL locking an integrated LC-VCO to 8.448 GHz. This frequency is divided by 2 to generate I/Q signals at 4224 MHz. Two current-steering 4-bit DACs

running at a sample rate of 4.224 GHz generate the three LF frequencies of 264 MHz and 792 MHz. The sample rate was chosen identical to the frequency of the I/Q signals to avoid an additional spur. The sinusoidal I/Q waveforms are stored in ROM lookup tables, which can be selected via the hop control commands. The circuit implementation of the LO generation is shown in Fig. 5. To provide a large voltage swing to the receive demodulators and the transmit modulators, the SSB mixer is inductively loaded and followed by a highly linear buffer chain. The inductive load provides further bandpass filtering of unwanted spurs. V. TRANSCEIVER TESTCHIP The transceiver is completed by a bandgap-based biasing and a high-speed control interface. The latter is required for realtime update of gain and hopping settings. It is implemented with low-voltage differential signals running at 264 Mb/s to fulfill the requirements of high control speed and low noise coupling from the interface to the RF part. Fig. 6 shows the photograph of the chip, which is packaged in a low-cost very thin profile quad flatpack no-lead (VQFN) plastic package with 48 pins. Chip area is 6.6 mm and it is fabricated on Infineon’s 0.13- m standard

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Fig. 6. Chip photograph.

Fig. 8. Measured TX spectrum in TFI mode.

Fig. 7. Measured TX constellation @ Pout Pout (right).

07 dBm (left) and EVM versus

digital CMOS technology with one-poly six-layer copper metal stack and MiM capacitors used as the only RF add-on feature. VI. MEASUREMENT RESULTS The transmitter is tested with an OFDM WiMedia/MBOA compliant signal [1]. On the left side of Fig. 7, the constellation diagram at the power amplifier output for band 1 is shown at an output power of 7 dBm. The corresponding measured error vector magnitude (EVM) is 28 dB. For band 2 and band 3, the measured EVM is 27.5 and 27 dB, respectively. On the right side of Fig. 7, the EVM in band 1 is drawn while varying the output power. For large output power levels when the PA is approaching its compression region, the EVM degrades. At a power close to 0 dBm, the transmitter still meets the required EVM of 20 dB [1]. Fig. 8 represents the spectrum at the PA output when operating in time frequency interleaved (TFI) mode [1], hopping between all three bands. The resolution bandwidth set at the spectrum analyzer is 1 MHz as recommended in [3]. The two graphs show the spectrum with power level set close to 41.3 dBm/MHz, and with and without external bandpass filter (TDK DEA453960BT). Using the external filter all spurious are well below 30 dBc.

Fig. 9. Measured conversion gain and noise figure versus baseband frequency over all three bands.

The measured conversion gain and NF of the receiver for all three bands are shown in Fig. 9. The maximum gain and the minimum NF are 37.8 dB and 3.6 dB, respectively. Operating at band 3, the NF increases to 4.1 dB. The gain variations over the entire baseband frequency range and across all UWB mode-1 bands are less than 1 dB. At low (high) gain setting the IIP3 is 2 dBm ( 22 dBm). The phase noise of the LO generation is characterized at the TX output. From 100 Hz to 100 MHz offset, the integrated jitter is below 1.2 ps RMS for all three bands, corresponding to an EVM level of 29.5 dBc for band 3. The hopping time of the LO generation including the receive chain is shown in Fig. 10. It was measured using a fixed RF input frequency of 3.5 GHz, while hopping the LO from 3.96 GHz to 3.432 GHz. With a

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TABLE I UWB TRANSCEIVER PERFORMANCE SUMMARY

TABLE II UWB TRANSCEIVER COMPARISON

hopping time of 2 ns, it is well below the required 9.5 ns described in [1] and mainly limited by the filter pole of the mixer output stage. The performance data of the UWB RF transceiver are summarized in Table I. Table II compares the performance of this work to recently published state-of-the-art UWB transceivers. It shows a 2-dB improvement in NF to previous CMOS and even BiCMOS transceivers, and compares favourably to the previous best-NF BiCMOS transceiver. In TX, the output compression point outperforms all CMOS designs. VII. CONCLUSION

Fig. 10. Synthesizer fast hopping performance.

The presented RF transceiver fulfills or exceeds WiMedia/ MBOA requirements in terms of TX power, TX EVM, settling time, and RX noise figure. With a noise figure around 4 dB and an output power of 4 dBm for an EVM of 28 dB, this work clearly demonstrates the feasibility of a cheap all-CMOS RF solution for UWB applications.

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REFERENCES [1] Multiband OFDM physical layer specification, Release 1.0, Jan. 2005 [Online]. Available: http://www.multibandofdm.org [2] B. Razavi, T. Aytur, C. Lam, F.-R. Yang, K.-Y. Li, R. H. Yan, H.-C. Kang, C.-C. Hsu, and C.-C. Lee, “A UWB CMOS transceiver,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2555–2562, Dec. 2005. [3] Federal Communications Commission, Revision of Part 15 of the Commission’s Rules Regarding Ultra-Wideband Transmission Systems. Feb. 2002 [Online]. Available: http://www.fcc.gov/Bureaus/Engineering_Technology/Orders/2002/fcc02048.pdf [4] J. Bergervoet, K. Harish, G. van der Weide, D. Leenaerts, R. van de Beek, H. Waite, Y. Zhang, C. Razzel, and R. Roovers, “An interference robust receive chain for ultra wide band radio in SiGe BiCMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 200–201. [5] A. Ismail and A. Abidi, “A 3.1 to 8.2 GHz direct conversion receiver for MB-OFDM UWB communications,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 208–209. [6] R. Salerno, M. Tiebout, H. Paule, C. Sandner, and M. Streibl, “ESDprotected CMOS 3–5 GHz wideband LNA+PGA design for UWB,” in Proc. ESSCIRC, Sep. 2005, pp. 219–222. [7] W. Soldner, M. Streibl, U. Hodel, M. Tiebout, H. Gossner, D. SchmittLandsiedel, J. H. Chun, C. Ito, and R. W. Dutton, “RF ESD protection strategies: Codesign vs. low-C protection,” in Proc. EOS/ESD Symp., Anaheim, CA, Sep. 2005, paper 1A.5. [8] M. Tiebout and P. Paparisto, “LNA design for a fully integrated CMOS single chip UMTS transceiver,” in Proc. ESSCIRC, Sep. 2002, pp. 835–838. [9] S. Lo, I. Sever, S. Ma, P. Jang, A. Zou, C. Arnott, K. Ghatak, A. Schwartz, L. Hunynh, and T. Nguyen, “A dual-antenna phased-array UWB transceiver in 0.18 m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 388–397. [10] A. Tanaka, H. Okada, H. Kodma, and H. Ishikawa, “A 1.1V 3.1-to-9. 5GHz MB-OFDM UWB transceiver in 90nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 398–407. [11] T. Aytur, H.-C. Kang, R. Mahadevappa, M. Altintas, S. ten Brink, T. Diep, C.-C. Hsu, F. Shi, F.-R. Yang, C.-C. Lee, R.-H. Yan, and B. Razavi, “A fully integrated UWB PHY in 0.13m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 418–427. [12] B. Shi and M. Y. W. Shia, “A 3.1–10.6 GHz RF front-end for Multiband UWB wireless receivers,” in IEEE RFIC Symp. Dig. Papers, Jun. 2005, pp. 343–346.

Christoph Sandner (S’93–M’95) was born in Munich, Germany, in 1968. He received the Dipl.-Ing. degree in electrical engineering from the Technical University of Graz, Austria, in 1995. Since 1995, he has been with the Microelectronics Development Center of Siemens AG, now Infineon Technologies, in Villach, Austria. His main interest is the design of analog and mixed-signal modules. Since 2004, he has been Project Manager heading the analog/RF front-end UWB development.

Sven Derksen was born in Krefeld, Germany, in 1968. He received the Dipl.-Ing. degree in electrical engineering from the Gerhard Mercator University of Duisburg, Germany, in 1995. In the same year, he joined the Fraunhofer-Institute of Microelectronic Circuits and Systems in Duisburg, Germany, where he was involved in the design of mixed-signal high-temperature SIMOX CMOS ASICs and analog modules. Since 2000, he is with the Microelectronics Development Center of Infineon Technologies, in Villach, Austria, focusing on the design of analog and mixed-signal modules.

Dieter Draxelmayr (M’01) was born in Vienna, Austria, in 1958. He received the M.S. degree in electrical engineering in 1982 and the Ph.D. degree in 1988, from the Technical University Vienna, Austria. He joined Siemens HL, now Infineon Technologies, in 1982. Since 1988, he has worked on analog and mixed-signal circuits, including self-calibrating A/D and D/A converters.

Staffan Ek was born in Jönköping, Sweden, in 1978. He received the M.S. degree in electrical engineering from Lund University, Lund, Sweden, in 2002. He worked for the Swedish research institute Acreo from 2002 to 2004 as a circuit designer. Since 2004, he is with Infineon Austria, Villach, working on the design of frequency synthesizers and mixed-signal circuits.

Voicu Filimon (M’00) received the Dipl.-Ing. and Dr.-Ing. degrees in electrical engineering from the Technical University of Timisoara, Romania, in 1986 and 1994, respectively. In 1995, he was a research associate at Ohio State University, Columbus, focusing on radar system design. In 1997, he joined the DaimlerChrysler Research Institute, Ulm, Germany, working on MMIC and radar sensor design for automotive applications. Since 2001, he has been with Infineon Technology AG, Munich, Germany, and Villach, Austria, working on high-speed and RF integrated circuit design. His research interests include RF system and RF IC design for wireless communication systems.

Graham Leach (M’06) was born on July 12, 1972, in Tunbridge Wells, U.K. He received the B.Eng. degree in electronic engineering in 1994. From 1994 to 1997, he was with Nokia working on DAMPS phone and chipset development. From 1997 to 1999, he was a Research Assistant at Southampton University investigating integrated RF passives and compact modeling of SiGe HBT devices. From 1999 to 2003, he was with Ericsson working on DECT and Bluetooth RF transceivers. Since 2003, he has been a Director at Riverbeck Ltd., Swindon, U.K., working on UWB and CMOS multimedia circuits.

Stefano Marsili received the B.Sc. degree in electrical engineering from the Università degli Studi di Padova, Padova, Italy, in 1996. He is currently with Infineon Technologies Austria, Villach, Austria, working on communication circuits for UWB application. His research interests include digital and analog signal processing and circuit modelling.

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Denis Matveev was born in Dubna, Russia, in 1976. He received the M.Sc. degree in electrical engineering from MEPhI State University, Moscow, Russia, in 1999, and completed his Ph.D. study in the Joint Institute for Nuclear Researches, Dubna, Russia, in 2001. He is currently with Infineon Technologies Austria, Villach. His research interests include RF/microwave, analog and mixed-signal design, testing and measurements of wireless communication systems.

Christian Reindl was born in Vorau, Austria, in 1966. He received the Dipl.-Ing. degree in technical engineering from the Technical University of Graz, Austria, in 1993. Since 1996, he has been with the Microelectronics Development Center of Siemens AG, now Infineon Technologies, in Villach, Austria, where he is engaged in analog and mixed-signal circuit design.

Koen L. R. Mertens was born in Antwerpen, Belgium, in 1971. He received the M.Sc. and Ph.D. degrees in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1998 and 2005, respectively. In 2004 he joined Infineon Technologies Austria, Villach. His research interests include RF IC design for wireless communication systems.

Raffaele Salerno received the Master degree in electrical engineering and the Ph.D. degree in electronics and automation engineering from the University of Catania, Catania, Italy, in 1995 and 1999, respectively. From 1996 to 2000, he was a scientist at STMicroelectronics Research and Development Center of Catania, where his research focused on high-frequency analog integrated circuits for cellular systems. Since 2000, he has been with Infineon Technologies, Villach, Austria, where he has been involved in the design and development of high-performance analog front-ends for telecommunication systems and consumer electronics. His current research interest lies in the design of integrated circuits for wireless communications equipment and analog signal processing.

Florian Michl studied physics in Regensburg, Germany, and Boulder, Colorado, and received the M.Sc. degree from the University of Regensburg in 1993 and the Ph.D. in semiconductor physics from the same institute in 1997. After two years at BCG, a strategy consulting company, he joined Infineon Technologies in 1999, where he held various responsibilities at the company’s headquarters in Munich and in the Design Center Singapore. Since 2002, he has been heading a department for analog and RF IC development in Infineon’s Design Center in Villach, Austria.

Hermann Paule received the degree in telecommunication engineering in Munich, Germany, in 1986. He started his career in the field of television broadband communication via cable and fiber optics in the research and development department of the Kathrein-Werke in Rosenheim, Germany. In 1997, he joined Municom GmbH, where he set up the company’s European RF application department, working with design groups from RF Micro Devices for supporting cordless and ISM applications. Since 1999, he has been working as an RF design and RF modeling engineer for Infineon Technologies AG in Munich and Villach.

Marc Tiebout (S’90–M’93) was born in Asse, Belgium, in 1969. He received the M.S. degree in electrical and mechanical engineering in 1992 from the Katholieke Universiteit Leuven, Belgium, and the Ph.D. degree in electrical engineering from the Technical University of Berlin, Germany, in 2004. In 1993, he joined Siemens AG, Corporate Research and Development, Microelectronics in Munich, Germany, designing analog integrated circuits in CMOS and BiCMOS technologies. In 1997, he started the design of radio frequency devices and building blocks in sub-m CMOS technologies. From 1999 to 2005, he was with Infineon Technologies AG, Munich, Germany, where he worked on RFCMOS circuits and transceivers for cellular wireless communication products and conducted highest frequency RFCMOS research for 17 and 24 GHz applications. Since March 2006, he has been with Infineon Technologies AG Austria, Villach, acting as Concept Engineer for UWB front-end development. He has authored and coauthored more than 30 IEEE publications and holds more than 10 patents. His main interest goes into low-power high-frequency circuits and systems in CMOS. Dr. Tiebout serves as a member of the technical program committee of ISSCC and ESSCIRC.

Manfred Punzenberger (S’97–M’01) received the M.S. (Diplom-Ingenieur) degree in electrical engineering from the Graz University of Technology, Graz, Austria, and the Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, in 1991 and 2000, respectively. In 1991, he joined Siemens EZM (now Infineon Technologies Austria AG), Villach, Austria, working in the field of CMOS, BiCMOS, and Smart Power analog circuit design. From 1994 to 2001, he was a Research Assistant at the EPFL, studying low-voltage low-power analog filter design. Since 2001, he has been with Infineon Technologies Austria AG, Villach, Austria. The main topics of his work include concepts for wireless transceivers and various analog and RF building blocks.

Andreas Wiesbauer (M’98) received the M.S. and Ph.D. degrees in electrical engineering from the Vienna University of Technology, Vienna, Austria, in 1991 and 1994. From 1996 to 1997, he was a research associate at Oregon State University, Corvallis, where his research focused on sigma-delta data converters. In 1997, he joined Infineon Technologies’ Design Center in Villach, Austria. Currently, he is Principal Engineer for analog and mixed signal concepts and circuits. His research interests are in the area of low-voltage CMOS implementations of oversampling, and high-speed data converters and transceiver circuits. He has authored or co-authored more than 40 publications and holds more than 10 patents.

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Ian Winter was born on February 20, 1972, in Reading, U.K. He received the B.Sc. degree in physics from Manchester University, Manchester, U.K., and the M.Sc. degree from Portsmouth University, Portsmouth, U.K., in 1994. From 1994 to 1998, he was with GEC Plessey Semiconductors working in the Wireless Communications Group. From 1998 to 2003, he was working on CDMA, DECT, and WLAN RF transceivers for Ericsson. From 2003 to 2005, he was with Riverbeck Ltd., Swindon, U.K., working on UWB circuits. He currently leads UHF RFID development at Innovision Research and Technology, Cirencester, U.K.

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Zisan Zhang received the B.Sc., M.Sc., and Ph.D degrees in electrical engineering from Jilin University China, Changchun, China, in 1995, 1998, and 2001, respectively. In 2005, he received his second Ph.D. degree in electrical engineering from the University of Duisburg-Essen, Duisburg, Germany. From 2001 to 2004, he worked in Fraunhofer Institute of Microelectronic Circuits and Systems in Duisburg, Germany. Since September 2004, he has been with Infineon Technologies Austria AG, in Villach, Austria. His research interests include CAD for analog and RF circuits, CMOS analog and RF circuit design.