Nuclear Instruments and Methods in Physics Research B 237 (2005) 126–130 www.elsevier.com/locate/nimb
Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping S. Walther a
a,*
, D. Lenoble b, F. Lallement b, A. Grouillet b, Y. Erokhin a, V. Singh a, A. Testoni a
Varian Semiconductor Equipment Associates, Inc. 35 Dory Road, Gloucester, MA 01950, USA b ST Microelectronics, 850 rue J. Monnet, BP 16, 38921, Crolles Cedex, France Available online 17 June 2005
Abstract For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2–5· higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65 nm CMOS devices. Specifically, p+/n ultra-shallow junctions formed with BF3 plasma doping have superior Xj/Rs characteristics to beamline implants and yield up to 30% lower Rs for 20 nm Xj while using standard spike anneal with ramp-up rate of 75 C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65 nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65 nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior Vt roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65 nm devices with PLAD SDE implants while still achieving Vt roll-off and IonIoff performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65 nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity. 2005 Elsevier B.V. All rights reserved.
1. Introduction *
Corresponding author. Tel.: +1 978 282 2490; fax: +1 978 281 1897. E-mail address:
[email protected] (S. Walther).
PLAsma Doping (PLAD) is a technique for implanting ions from a plasma into a substrate that is pulse biased and its performance, including
0168-583X/$ - see front matter 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.nimb.2005.04.087
S. Walther et al. / Nucl. Instr. and Meth. in Phys. Res. B 237 (2005) 126–130
a closed-loop dosimetry system, have been well described by earlier papers [1–6]. Ion energy is set by the wafer bias and the ions are implanted with normal incidence (0 tilt) simultaneously across the entire wafer. It is differentiated from traditional beamline implantation by eliminating mass resolving and beam and/or wafer scanning apparatus, which results in a much simpler and more compact architecture [1]. Ultra-shallow junctions (USJ) are required to suppress short channel effects (SCE) in sub-90 nm devices, and other device electrical characteristics are impacted strongly by implant properties such as lateral abruptness of the implanted dopant distribution, crystal damage, and their impact on the thermal diffusion that occurs during dopant activation. PLAD implant properties are distinctly different from beamline implants and the advantages are well characterized [6,7]. PLAD also offers advantages for device properties, such as threshold voltage roll-off, as illustrated by electrical device characterization results with advanced CMOS architectures [8–11]. Requirements for sub-90 nm devices are driving extension implant energies below 500 eV, and requiring the elimination of high-energy ion beam contaminants. Gate poly doping requirements are similarly stringent, with the thinner poly layers demanding contaminant-free low energy (2–5 keV 11B+) implants with doses near or above 1E16 cm2. This combination of requirements has led to significantly reduced productivity for beamline-based implant tools, due to the inefficiency of transport of low energy high space charge ion beams. Plasma based implants avoid this limitation, as ions are transported across the plasma sheath, a distance of about a centimeter as compared to the meter size scale of beamline ion transport. PLADÕs combination of efficient ion transport and a compact architecture provide a vastly improved throughput/m2 of machine footprint for low energy implants [5]. To implement the demonstrated advantages of the PLAD implant technique for USJ and productivity, the ability to match PLAD to traditional implants is investigated. For gate doping, it is demonstrated that PLAD can be used as a Ôdrop-inÕ replacement for traditional implantation, by matching dose, depth and activation,
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and thus gain the superior productivity of this approach. For the USJ requirements of 65 nm extension implants, device data for both PMOS and NMOS transistors are compared for traditional and PLAD implants, using the novel simplified process flow presented by Lallement at VLSI 2004 [8]. This case illustrates how the improved USJ performance of PLAD can be utilized to achieve a simpler low cost process flow, not feasible with traditional implant, and maintain similar performance. For both of the above implant applications, PLAD productivity is compared with beamline implant, in order to illustrate the economic limitations of traditional implant.
2. Process matching The ability to exploit PLAD as a drop-in process, where no other pre or post-implant processes are modified, is a test of the feasibility of porting existing processes to PLAD rather than designing it in. This is illustrated with the case of high dose gate poly doping, where abruptness at the poly/ dielectric interface and matching activation are critical. Fig. 1 shows the comparison of PLAD and traditional activated boron depth profiles by Spreading Resistance Profiling (SRP), using the ˚ same anneal recipe for wafers having an 800 A
Fig. 1. A comparison of SRP depth profiles of activated carrier concentration between PLAD and traditional implantation into polysilicon after annealing at 950 C for 30 s, showing equal or better activation for the PLAD implant.
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thick poly layer. The two are extremely well matched, especially in the critical region closest to the poly/dielectric interface. Integration of the profiles shows that the activation level for the PLAD implant is equal or better than the traditional implant, and is consistent with sheet resistance measurements. By achieving activated dose matching for otherwise identical process flows, PLAD can be utilized as a Ôdrop-inÕ replacement for traditional implantation, with a dramatic improvement in productivity. In addition, the retained fluorine dose after annealing is 100 WPH 5 kV 1E16 BF3 >100 WPH 9.8 m2 610 kV 0 Good without offset spacer, superior with it 2.8 nA/lm 1.24 fF/lm2
200 eV 1E15 11B+ (decel) 15 WPH (1 mA) 3 keV 1E16 11B+ (decel) 20 WPH (12.5 mA) 20.1 m2 640 80 keV 0 and high tilt Extra process steps needed – good with offset spacer 10 nA/lm 1.35 fF/lm2
items summarize the device electrical data presented and relative performance. 5. Conclusions The trend to lower energies, higher doses, and lower tolerance for energy contamination has led to much higher costs for both USJ and DRAM gate doping applications. In many cases, the requirements for additional tools also runs up against the limits of available cleanroom space for existing fabs. Exploiting PLAD for bottlenecks in high volume manufacturing allows one to circumvent the deficiencies of traditional implant technology. PLAD can be used as either a drop-in substitute, as shown for the DRAM gate doping application, or a designin successor, as for the source drain extension, to replace traditional implant technology. In addition to the direct productivity benefit, the SCE advantages of PLAD USJ have been utilized to fabricate simplified 65 nm NMOS and PMOS transistors with an ultra-low cost process flow. Acknowledgement The authors would like to thank Sandeep Mehta, Kyuha Shim, Jinning Liu and Ed Moore for their assistance in support of this work.
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