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An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic Rod Blaine Foist, Student Member, IEEE, Cristian Sorin Grecu, Student Member, IEEE, André Ivanov, Fellow, IEEE, and Robin F. B. Turner Abstract—This paper presents a reference design and tutorial for an embedded PowerPC subsystem core with user logic in a Xilinx field-programmable gate array (FPGA). The design and tutorial were created to help graduate students who are doing research in complex electronic applications and want to prototype their designs in an FPGA. Specifically, the design provides a starting point for any application that requires an embedded processor plus user logic that is external to the processor block, but must interface to it. In addition, this material is useful as a supplementary laboratory module in advanced FPGA design (for senior- and graduate-level courses). The design project provides a practical introduction to system-on-chip (SOC) design, embedded processor design, hardware–software codesign, and general FPGA development. The authors’ assessment shows that even third-year electrical engineering students can complete the tutorial successfully (within approximately three hours). The design database and tutorial document are publicly available and can be downloaded from a website at The University of British Columbia (UBC), Vancouver, BC, Canada. Index Terms—Embedded PowerPC, field-programmable gate array (FPGA) design project, hardware–software codesign.
I. INTRODUCTION A. Solving a Prototyping Roadblock HEN industry supports university research, they generally prefer to see working prototypes of new research concepts and not just simulations. Recently, a team of graduate students and postdoctoral researchers from The University of British Columbia (UBC), Vancouver, BC, Canada, were at an impasse in implementing their simulated designs into an actual field-programmable gate array (FPGA) hardware platform. They needed to transfer their sophisticated software program into an embedded processor, and they needed tis a hat processor to interface with complex, user-defined on-chip logic that was external to the processor block. However, they were unable to resolve the problem of how to connect user logic to an embedded processor (within Xilinx tools). They called upon UBC’s system-on-chip (SOC) research group for assistance. This led to the development of the reference design that is herein presented, as well as a short training course based on the tutorial document that explains how to recreate the design. The graduate students, for whom this project was created, used the design to
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Manuscript received July 6, 2007; revised September 12, 2007. First published March 21, 2008; last published August 6, 2008 (projected). This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) and by the Canadian Microsystems Corporation (CMC). The authors are with the Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC V6T 1Z4, Canada (e-mail:
[email protected]). Digital Object Identifier 10.1109/TE.2007.912411
resolve their prototyping impasse, and estimated that doing so saved them several weeks of research and development time. The reference design is targeted for the Amirix AP1100 Development Board [1] which contains a Xilinx Virtex II Pro FPGA [2]. With a small amount of effort, the design can be adapted for other development boards that contain any Xilinx device with a PowerPC core (or any device that can implement a MicroBlaze core, if that is the desired processor, since the design steps, presented later, apply to both processors). The design was created using version 7.1i of the Xilinx software (EDK and ISE) [2]. B. Teaching Advanced FPGA/SOC Design Two databases are provided with this project: a fully-functional, finished version of the reference design, and a “starter kit,” baseline design that needs to be completed. The step-by-step tutorial guides the student through the design flow to recreate the finished reference design from the baseline design. In this manner, the tutorial is also useful as a supplementary laboratory module in advanced FPGA/SOC design-to teach and illustrate, by example, the topics of SOC design, embedded processor design, hardware–software codesign, and general FPGA development. C. Pedagogical Issues Addressed FPGA design tools are constantly improving, and becoming more user-friendly. Nevertheless, SoC design is inherently difficult-a designer must manage a whole “system” of complexity, and understand a suite of complicated FPGA software tools as well. This difficulty is intensified when using embedded processors which must interface to user logic. Consequently, FPGA design with embedded processors is not easy to teach. This pedagogical problem is remedied by using a reference design with a step-by-step tutorial as a vehicle for teaching. Such an approach seems to be consistent with the following industry viewpoint. Martin [4] (formerly of Cadence, San Jose, CA, now chief scientist at Tensilica, Santa Clara, CA) gives helpful insights, from industry’s perspective, on what “SOC Design Education” should encompass: “[traditional VLSI and IC Design] education must change to reflect this [SoC] evolution, yet we do not see a complete evidence for this, especially at the undergraduate level. …students need to be exposed to and literate with topics such as embedded software, system-level design, algorithmic design, IP design and IP integration. SoC architectures, HW-SW partitioning and a good understanding of tradeoffs must be added to the curriculum.”
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With regard to the design process, he said: “Students should be exposed to modern electronics-based design flows, and use the most advanced commercially-provided tools…” Similarly, Amaral et al. also recommend the use of “industry-grade” design tools [5]. The unique contribution of this present design project, as a supplementary lab module, is its illustration of the tool flow in designing an embedded PowerPC processor that interacts with user logic. Along the way, the student is introduced, in varying degrees, to every one of the elements mentioned previously by Martin. D. Literature Survey 1) Reference Design (PowerPC Connecting to User Logic): Within the Xilinx toolset, customizing a PowerPC block by adding peripherals to the basic processor core is relatively easy. These peripherals can be intellectual property (IP) blocks from the Xilinx library (such as timers and memory controllers), or they can be user-defined peripherals. Although this customized PowerPC is a type of “embedded processor,” it remains as the top-level of the design. Essentially, the FPGA contains only a PowerPC block (i.e., a processor core plus peripherals). Some designers, however, need to embed the PowerPC as a subsystem that connects to user logic which is not functioning as a peripheral. This custom user logic, whether complex or simple, resides outside the processor block. Using the Xilinx tools to make this type of connection–PowerPC block to user logic–is not easy. In fact, this task requires several nonobvious design steps that are somewhat hard to discover within the vendor documentation, and somewhat difficult to understand at first. The present work simplifies this problem by organizing and clarifying the procedures and placing them into an easy-to-follow, step-by-step tutorial (with accompanying reference design). The design steps presented in the tutorial are partly based upon Norton’s article [6] on how to create an embedded processor subsystem within Xilinx tools. However, his methodology depends on the use of third-party synthesis software, Synplify Pro [7], and he does not provide any reference design. Furthermore, his article is not at all structured to be a tutorial for students, but rather a guide for engineers with much more experience. In contrast, the present paper’s method only requires the Xilinx-provided tools (although some additional manual steps are required by the user). Other PowerPC reference designs do exist, for example [8], [9], and [10]. However, to the best of the authors’ knowledge, none provide (nor explain) the connection from PowerPC to user logic. These other designs connect the processor only to peripherals, and thereby are not utilizing the PowerPC as a subsystem, but rather as a “top-level” design. 2) Supplementary Lab Module in Advanced FPGA/SOC Design: FPGAs have consistently grown in popularity within industry and academia, since their invention by Xilinx cofounder Ross Freeman in 1984 [11]. Rapid prototyping and reconfigurability are two reasons for this popularity. Educational interest in using FPGAs–for teaching system design–goes back at least to 1997. For example, Ochi taught computer architecture by having students implement a 16-bit microprocessor within an FPGA [12].
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Embedded processors, as IP cores, have only come into FPGAs relatively recently. The PowerPC [13], a 32-bit reduced instruction set computer (RISC) processor, was developed in 1991 as a joint venture of IBM, Apple, and Motorola for use in personal computers [14]. The PowerPC was licensed by Xilinx, from IBM, in July 2000 and later placed as a hardwired embedded processor core in the Virtex II Pro family of devices [15]. Various authors have successfully used FPGAs with embedded processors in laboratory design projects for seniorand graduate-level courses. Hall et al. teach digital signal processing (DSP) using FPGAs [16]. In the final capstone lab project, students must use a soft-core processor (unspecified by the authors) as part of their design. Hall and Hamblen [17] use FPGA-based boards, with embedded processors, for senior-level design projects. The embedded processors used were the Nios by Altera [18] and the MicroBlaze [2] by Xilinx. A three-course, comprehensive graduate-level curriculum on SoC design using FPGAs is presented by Lynch et al. [19]. In that curriculum, the final and most complex lab project involves only an 8-bit on-chip processor (but this processor is not an industry-standard block). Wirthlin’s senior-level design project [20] uses a PowerPC processor (in a Xilinx FPGA) to teach system design. But it uses the embedded processor as the top-level design, and not as a subsystem. This paper presented the only educational project found in the literature (to the best of the authors’ knowledge) that uses a PowerPC embedded processor of any kind. In contrast, Xilinx has shipped more than 100 000 PowerPC cores to its customer base [21], which indicates that this processor is widely used in industry. But, apparently, the PowerPC is not so widely used in education. A search within all of IEEE Xplore for “PowerPC” and “education” yielded only 7 documents. In summary, no other papers appear to have introduced a lab module (or design project) that treats this more advanced level of PowerPC embedded processor as a subsystem that connects to user logic (such as was needed by UBC researchers mentioned previously). Thus, the present work aims to contribute in a complementary manner to the solid foundation of other curricula by offering both the reference design and the tutorial for use as a supplementary lab module. II. DESCRIPTION OF REFERENCE DESIGN Fig. 1 is a block diagram of the design to be prototyped. It represents the simplified digital portion of a wireless local area network (WLAN) [22] system implemented within an FPGA. The digital portion of a WLAN system has two major components: the software layer, called “medium-access control” (MAC), running in a processor, and the “physical layer” (PHY), which consists of several cascaded processing blocks (beginning with a “Scrambler”). The simplified design consists of a PowerPC processor block and the user logic (everything external to the processor). Within the user logic are the PHY (Scrambler block only) and interface logic [dual-port RAM, Controller, and a parallel-to-serial converter (PSC)] which connects the PHY to the processor. The mini-MAC is a simple C program, running in the PowerPC, which interacts with the user logic and prints messages, via an RS-232 link, to a hyper terminal running on a personal computer.
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Fig. 1. FPGA prototype of simplified WLAN digital section [PowerPC as a subsystem connects to user logic (shaded boxes)].
A 32-bit word is written to the PHY (Scrambler) as follows. Mini-MAC writes a word to the dual-port RAM (DP-RAM), and then activates the start signal to the Interface Controller (IntCon), a simple state-machine, which in turn controls the read-out of the word and transfer to the PSC. The PSC converts the word to a serial stream of 32 bits, which is captured by the Scrambler (a 32-bit shift-register in this simplified design), under control of IntCon. When the done signal is activated, mini-MAC is triggered to read the value from the 32-bit bus, sreg32_data, and then print the results on a hyper terminal screen. Although the previously shown design was created as a prototype for a WLAN application, the design steps given later can be applied straightforwardly to any application that needs to connect the PowerPC to user logic. Furthermore, these same design steps apply to a system with the MicroBlaze processor and user logic.
Fig. 2. FPGA baseline design.
III. TUTORIAL AND DESIGN STEPS Xilinx’s Embedded Design Kit (EDK) is a suite of tools for processor design (including PowerPC and MicroBlaze). Within EDK, the primary design tool is called Xilinx Platform Studio (XPS). Hardware and software are co-designed within XPS by using two separate graphical user interface (GUI) tabs. ISE is Xilinx’s traditional FPGA design tool for creating the complete design. Project Navigator (PN) is the primary GUI within ISE. The step-by-step tutorial document explains the use of these FPGA design tools for the rather nonintuitive process of connecting an embedded processor-as a subsystem-to user logic. Screen shots of the software GUIs are used extensively to illustrate how to do this. As mentioned previously, a baseline design (see Fig. 2) accompanies the tutorial. Provided by the board vendor, Amirix, this starting-point design contains a standalone PowerPC core which runs a simple C program to print “Hello World” on a hyper terminal. The tutorial guides the student through the steps necessary to recreate the reference design (Fig. 1) from the baseline. It also explains and illustrates general FPGA design concepts along the way. These are indicated with the phrase “design note.” Six major design steps form the outline of the tutorial. 1) Step 1: Design of the Stand-Alone PowerPC Block Using Xilinx’s EDK/XPS Tool: The objectives of Step 1 are to: 1)
Fig. 3. Modified PowerPC design.
verify that the baseline design works by downloading it into the board to see “Hello World” appear on a hyper terminal screen; and 2) modify the design by adding IP cores within the PowerPC block for interfacing input/output (I/O) connections to the user logic. As shown in Fig. 3, four library IP cores (along with ports and interconnections) are added to the PowerPC block. These parameterizable cores-three general purpose I/Os (GPIOs) in
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TABLE I ADDRESSES ADDED TO C PROGRAM
gray, and one external memory controller (EMC) in black-are necessary to interface to the ports of the user logic. These cores are connected to the PowerPC core via the built-in on-chip peripheral bus (OPB), and function as peripherals. In addition, addresses are generated-in order to allocate memory space-for these four peripherals. The base addresses are then manually entered into the user’s C program (via define statements) in order to access these interfaces (see Table I). Accesses to these address spaces will later be simulated. 2) Step 2: Simulation of the Stand-Alone PowerPC Design Using ModelSim [23]: The objective of Step 2 is to simulate the modified PowerPC block in order to verify correct functionality. The “hello-world” C program is replaced with a new C program (for simulation purposes only) that performs accesses to all of the user logic I/O ports. This is not a complete test of the PowerPC block (since the user logic has not yet been added to the overall design) but it does give partial confirmation that the modified design is working (e.g., writing to memory can be verified, and read-addresses can be verified). Hardware and software are simulated simultaneously in this step (a very interesting, and often surprising, realization for the student to grasp). 3) Step 3: Design and Simulation of the User Logic (i.e., Interface Logic Plus Scrambler): The objectives of Step 3 are to: 1) guide the student through the special steps required to design the dual-port RAM (DP-RAM), of Fig. 1, using Xilinx’s CoreGen tool [2]; 2) simulate the DP-RAM in order to verify correct logic functionality; and 3) indicate where to find (within the database), and how to simulate, the remaining blocks of the user logic, which have been predesigned by the authors. For general FPGA design, memory blocks must be prepared (customized) by using one of the ISE tools known as the Core Generator (CoreGen). In this design step, the DP-RAM is designed and then simulated. The other three user logic blocks (Fig. 1) have been predesigned, as hardware description language (HDL) files, by the authors and are placed within the database. Finally, these three user logic blocks-plus the DP-RAM block-are instantiated within an HDL “top-level” file, thus adding one level of hierarchy to the user logic. These five HDL files, which now compose the user logic, can be simulated using author-provided “test bench” files for ModelSim. 4) Step 4: Conversion of the Stand-Alone PowerPC Design (in XPS) to a Subsystem Design, and Exporting to ISE’s Project Navigator Tool: The objectives of Step 4 are to: 1) convert the PowerPC design from being a top-level (stand-alone) block to a subsystem block; 2) load the final C program (which is designed to exercise the circuit shown in Fig. 1); and 3) export the subsystem design from the XPS tool to the PN tool. Within EDK/XPS, a new design is by default a “top-level” design (containing only the processor block). If the design is exported in this manner, a single HDL file will be generated
Fig. 4. Exported design: before editing.
Fig. 5. Exported design: after editing.
that contains the PowerPC block as the top of the hierarchy. In a Verilog design, this file will be named “system.v” (system.vhd for VHDL). When a design is exported as a subsystem, two HDL files are generated: a “system_stub.v” file that now represents the top of the hierarchy, and a “system.v” file that contains only the processor block. Initially, “system_stub.v” contains only an instance of “system.v” and the I/O buffers that go off-chip (see Fig. 4). However, system_stub.v allows designers to instantiate other blocks (i.e., the user logic) and connect them to the PowerPC block as needed. 5) Step 5: Editing of the Design (Within Project Navigator) to Add in the User Logic, to Connect Together the PowerPC Subsystem and User Logic: The objectives of Step 5 are to: 1) perform manual editing of “system_stub.v” both to instantiate the user logic and connect it to the PowerPC subsystem block; and 2) add all remaining design files (that were not auto-exported) into the PN project. Figs. 4 and 5 show the exported design before and after editing, respectively. Note that in both figures, “system_stub.v”
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contains the top-level FPGA design, and “system.v” contains only the PowerPC block. Note also that initially the “User Logic signals” go off-chip (Fig. 4). This was a necessary, but temporary, connection done in Design Step 1 (see tutorial document) in order to make these signals available at the top-level (inside system_stub.v). When exporting a design, the XPS tool auto-assigns I/O buffers to all external signals. Here, in Step 5, within PN, system_stub.v must be manually edited to 1) remove the unwanted I/O buffers connected to the user logic signals, 2) instantiate the top-level user logic block, and 3) reconnect the user logic signals from the PowerPC block to the user logic block, as shown in Fig. 5. As far as the authors know, there is no automated way, within the Xilinx tools alone, to make this instantiation and connection between the two major blocks. 6) Step 6: Implementation and Download Into the Board: The objectives of Step 6 are to: 1) within PN, run all of the processing steps to implement and then download the design into the development board; and 2) verify correct functionality of the final design via hyper terminal messages. Project Navigator will create the final design by performing synthesis and place-and-route steps, then generating the final programming file, and downloading it into the FPGA in the development board. Upon startup, the PowerPC will execute its C program, as described previously, and print hyper terminal messages. IV. ASSESSMENT The design project tutorial was tested on a group of 34 volunteer students, composed as follows: 30 were third-year students enrolled in EECE 353, Digital Systems Design [24], in summer 2007 at UBC; two were second-year Ph.D. students (doing communications research) who were auditing the course, and two were fourth-year students who heard about the tutorial and asked to be included. The lab sessions were conducted with 11 teams of three students, generally. These sessions took about three hours on average. A one-hour introductory lecture, explaining the purpose of this design project and giving an overview of the tutorial, was given to the EECE 353 students before the labs began. At the time of the assessment, the third-year students had some knowledge of FPGA design flow (though not specifically Xilinx FPGAs and software, except for one student who had some prior experience with Xilinx tools), and intermediate expertise in designing digital systems consisting of basic logic blocks: state machines, datapaths, memory blocks, and arithmetic-logic blocks. None of the participants had any prior experience in designing integrated systems using predefined hardware or software cores. During the course of the lab sessions, students worked on the tutorial with virtually no help from the instructor. However, because they expressed an interest in understanding what they were doing, and not just “mindlessly” following a recipe, generous discussion was provided about the concepts, the purpose of each major step, and so on. An interesting fact worth noting is the high interest level of third-year students from a classical computer engineering program for gaining more experience in designing complex SoCs—which is usually the topic of senioror graduate-level courses.
The assessment questionnaire had three sections: A–Assess the Reference Design; B–Assess the content of the tutorial as a Supplementary Laboratory module (see Appendix); C–Qualitative questions (on the overall project). Students completed the questionnaires anonymously, at the end of their respective lab sessions. The findings of the assessment are as follows. A. Section A This section of the questionnaire was focused on evaluating the overall experience and opinions of the participants on the practical laboratory session. Results of questions can be summarized as follows. 1) Successful Recreation of the Reference Design (From the Baseline): Of the 11 teams, nine had a 100% working design, one team had a roughly 95% working design, and one team had a roughly 80% working design. This indicates that the complexity of the initial task-designing a system with a PowerPC block and user logic on an FPGA-was simplified to a level at which the majority of the students could complete the design successfully. 2) Lab Duration: Average time taken by teams to complete the lab was three hours, ranging from just over two hours to four hours. This confirms that the practical part of the tutorial can be included easily in the syllabus of a regular undergraduate course, where lab sessions generally require three hours. 3) General Comments From Participants: The majority of the volunteers indicated that the most interesting aspect of the practical session was the use of, and interaction with, different software tools of the Xilinx suite in order to create a complex, working design on the FPGA. Another aspect that the students appreciated very positively was being able to observe and build a complex digital system that has both software and hardware components. This provides a valuable insight, considering that classic microelectronics courses tend to concentrate on the hardware design aspects, but, on the other hand, embedded systems courses tend to concentrate more on the software side. B. Section B The questions in the second part of the assessment form (see Appendix) concentrated on the technical aspects of the lab session. Students were asked to indicate the functionality of different blocks in the design, and also to identify different aspects related to the interaction between the software program running in the PowerPC core, and the user logic and memory block. The average score for the eight questions of the second part of the assessment form, for the 34 students, was 47.1%, with highest score being 75%, and lowest score 0%. Considering the background and general level of expertise of the participants, this is not entirely surprising. In the third year of electrical/computer engineering programs, the students are able to design fairly complex digital systems software programs. However, there is still a gap in their understanding of the interaction between the software program and the underlying hardware that an embedded system encompasses. The authors believe that the students’ understanding of the content could be much improved if this module were adapted so as to allow them to make design changes and observe the results. For example, an instructor could easily modify/extend the tutorial by having students make simple changes to the C
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TABLE II QUALITATIVE EVALUATION OF THE PROJECT BY STUDENTS (ONLY 33 OF 34 RESPONDED)
program and observe the results after downloading and running the design (via hyper terminal messages, etc.). Similarly, design modifications to the user logic could be instructive as well. C. Section C The set of questions in the last part of the questionnaire were intended to evaluate qualitatively the usefulness of the supplemental lab module. Table II presents a summary of the students’ responses to Section C. The feedback received from students was positive, and the overall agreement was that it improved their knowledge not only on FPGA design, but also on design of embedded systems. The lower score on the third question (and the findings in Section B) seem to confirm the instructor’s observations during the lab sessions: that students were weaker in their understanding of what was happening in the software design versus what was happening in the hardware design. The amount of time spent on the theoretical background of the design (less than one hour) was clearly insufficient to provide a complete understanding of the interaction between the software program and the digital hardware built on the FPGA. In order to include the supplemental lab in the syllabus of an undergraduate or graduate level microelectronics course, the authors believe that the practical lab session should be complemented by adequate theoretical material delivered as a course lecture. The general agreement was that the supplemental lab module was well worth the time and effort invested by the participants. V. INTEGRATION WITH EXISTING COURSES After careful reviews and refining, and using feedback provided by the undergraduate students that volunteered to perform the practical sessions, the authors feel that this material can be successfully used in either third/fourth-year courses, or in graduate-level courses in computer engineering curricula. The sequence in which the laboratory module should be integrated with the course differs in the two previously mentioned situations. When including in an introductory/intermediate-level digital systems design course, the authors believe that the educational impact can be fully achieved by presenting the material in this paper towards the end of the course, when students have a basic understanding of designing fairly complex hardware. The practical lab tutorial would give students new insights on the issues and challenges involved in designing/prototyping complex SoCs on FPGA platforms, using both predesigned cores and user-defined logic. For more advanced courses, the practical tutorial can be scheduled towards the beginning of the course, and also used as a platform on which more complex designs can be built,
by adding custom applications (C programs) on the PowerPC core, and extra cores and/or user-designed blocks. VI. CONCLUSION A design project has been presented that helps to teach, by example, the challenging topic of embedded processor design within an FPGA. It is based upon a real, working design that provides a starting point for many research applications which need to be prototyped. Second, as a supplementary laboratory module, this design project aims to assist educators in teaching complex FPGA/SoC design-with an emphasis on embedded processors-from senior-level through graduate-level, and beyond. In addition, the overall project provides an introductory hands-on experience with hardware–software codesign. The quality of the reference design is based upon an industry-provided baseline design (as mentioned previously from Amirix), as well as the fact that it has been developed using state-of-the-art tools. Furthermore, the quality may be seen in its flexibility for use by a wide range of applications: the C program and the user logic are completely free to be modified to suit a designer’s needs, or to accommodate a diverse set of course practical laboratory sessions and projects. The tutorial and design databases are available for download at this UBC website: http://soc.ece.ubc.ca/soc/ research/fpga_projects. APPENDIX Assessment test (section B-assessing content as a supplementary lab module; correct answers in bold font) . 1) What is the purpose of the UART block RS232 connection? a) They allow programming of the FPGA b) They allow the C program to write messages to the PC’s hyper terminal c) They form part of the Boundary-Scan chain d) They provide for all of the above 2) Which block initiates the flow of data to the Scrambler block? a) Interface Controller b) Parallel-to-Serial Converter (“Par2Ser”) c) PowerPC d) Dual-Port BRAM 3) Data which arrives at the Scrambler originates from where? a) Interface Controller b) Parallel-to-Serial Converter (“Par2Ser”) c) PowerPC’s UART d) PowerPC’s C program
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4) What peripheral must be added to the PowerPC in order to interface to the DP BRAM? a) gpio (General-Purpose I/O) b) uartlite c) PHY d) emc (External Memory Controller) 5) The C program that runs in the PowerPC communicates directly with a) RS232 UART b) Dual-Port BRAM Interface Controller c) Scrambler d) All of the above 6) The PowerPC simulation step simulates the a) PowerPC hardware C program running in it b) PowerPC hardware only c) C program only d) Assembly code 7) The EDK/XPS tool is used to create a) PowerPC hardware C program running in it b) PowerPC hardware only c) C program only d) PowerPC “User Logic” 8) In the ISE tool, the Verilog hand-edit step is necessary to a) add in the C program b) join the PowerPC to the User Logic c) join the Dual-Port BRAM to the PowerPC d) do all of the above ACKNOWLEDGMENT The authors would like to thank the volunteer students of EECE 353 (and others) in the Department of Electrical and Computer Engineering, UBC, for participating in the assessment and J. M. Foist for help in tabulating the assessment data. REFERENCES [1] Amirix Inc., Halifax, NS, Canada [Online]. Available: http://www. amirix.com [2] Xilinx Inc., San Jose, CA [Online]. Available: http://www.xilinx.com [3] “System-on-chip market to hit 1.3 billion units in 2004, 2004, says new report,” Silicon Strategies, EE Times, 2000 [Online]. Available: http://www.eetimes.com/story/OEG20001025S0001 [4] G. Martin, “Industry needs and expectations of soc design education,” in Proc. Int. Conf. Microelectronic Systems Education, Anaheim, CA, Jun. 2003, pp. 146–147. [5] J. N. Amaral, P. Berube, and P. Mehta, “Teaching digital design to computing science students in a single academic term,” IEEE Trans. Educ., vol. 48, no. 1, pp. 127–132, Feb. 2005. [6] A. Norton, “Integrating EDK-created embedded processor subsystems,” Xcell Journal, 2005 [Online]. Available: http://www.xilinx. com/publications/xcellonline/xcell_52/xc_synplify52.htm [7] Synplicity Inc., Sunnyvale, CA [Online]. Available: http://www.synplicity.com/products/synplifypro [8] M. Muggli, M. Ouellette, S. Thammanur, and R. Armstrong, Jr, XAPP434 Xilinx Application Note, 2006. [9] P. Kalra, “UltraController-II: Minimal footprint embedded processing engine,” XAPP575 Xilinx Application Note, 2005. [10] M. J. Shah, “Design of a self-test vehicle for AC coupled interconnect technology,” M.S. thesis, Dept. Elect. and Comp. Eng., North Carolina State Univ., Raleigh, NC, 2006. [11] Xilinx Inc., San Jose, CA [Online]. Available: http://www.xilinx.com/ company/history.htm [12] H. Ochi, “ASAver.1: An FPGA-based education board for computer architecture/system design,” in Proc. Asia and South Pacific Design Automation Conf., Makuhari,, Japan , Jan. 1997, pp. 157–165. [13] IBM Inc., Armonk, NY [Online]. Available: http://www.ibm.com
[14] IBM Inc., Armonk, NY [Online]. Available: http://www03.ibm.com/ servers/eserver/pseries/hardware/whitepapers/power/ppc_arch.html [15] P. Clarke, “Xilinx may license FPGA cores to ASIC suppliers,” EE Times, 2001. [16] T. S. Hall and D. A. Anderson, “A framework for teaching real-time digital signal processing with field-programmable gate arrays,” IEEE Trans. Educ., vol. 48, no. 3, pp. 551–558, Aug. 2005. [17] T. S. Hall and J. O. Hamblen, “System-on-a-programmable-chip development platform in the classroom,” IEEE Trans. Educ., vol. 47, no. 4, pp. 502–507, Nov. 2004. [18] Altera Inc., San Jose, CA [Online]. Available: http://www.altera.com [19] J. D. Lynch, D. Hammerstrom, and R. Kravitz, “A cohesive FPGAbased system-on-chip design curriculum,” in Proc. Int. Conf. Microelectronic Systems Education, Anaheim, CA, 2005, pp. 17–18. [20] M. J. Wirthlin, “Senior-Level embedded system design projects using FPGAs,” in Proc. Int. Conf. Microelectronic Systems Education, Anaheim, CA, 2005, pp. 1–2. [21] T. Snowden, Lucent Technologies Chooses Xilinx Virtex-II Pro With Embedded IBM PowerPC as Solution for Its Optical Translator Unit, Xilinx Press Release 457 [Online]. Available: http://www.xilinx.com/ prs_rls/design_win/0457_lucent.htm [22] IEEE 802.11 LAN/MAN Wireless LANS, IEEE Standard 802.11a-1999, 1999 [Online]. Available: http://standards.ieee.org/getieee802/802.11. html [23] ModelSim Mentor Graphics Inc., Wilsonville, OR [Online]. Available: http://www.model.com [24] EECE 353 Digital Systems Design Course, University of British Columbia, Vancouver, BC, Canada [Online]. Available: http://courses. ece.ubc.ca/353
Rod Blaine Foist (S’07) received the B.S. and M.S. degrees in electrical engineering from the University of Washington, Seattle, in 1982 and 1989, respectively. He is working towards the Ph.D. degree at The University of British Columbia, Vancouver, BC, Canada. He is doing interdisciplinary research in system-on-chip design for biotechnology applications. From 1982 to 1996, he worked as a Test Engineer at John Fluke Manufacuring Company and then as an ASIC Design Engineer at Honeywell Marine Systems, Honeywell Air Transport Systems, and General Instruments. From 1996 to 2003, he worked as a Senior Lecturer in electronics at Singapore Polytechnic.
Cristian Sorin Grecu (S’05) received the B.S. and M.Eng. degrees in electrical engineering from the Technical University of Iasi, Iasi, Romania, and the M.A.Sc. degree from The University of British Columbia (UBC). Vancouver, BC, Canada, in 1996, 1997, and 2003, respectively. He is working towards the Ph.D. degree in the Department of Electrical and Computer Engineering, UBC. His research interests focus on design, test, and fault tolerance of large SoCs, with particular emphasis on their data communication infrastructures.
André Ivanov (S’81–M’85–SM’95–F’06) received the B.Eng. (Hons.) M.Eng., and Ph.D. degrees in electrical engineering from McGill University, Montreal, QC, Canada, in 1983, 1985, and 1989, respectively. He is a Professor of Electrical and Computer Engineering at The University of British Columbia, Vancouver, BC, Canada. In 2001, he cofounded Vector 12, a semiconductor IP company. He is an author and an inventor of several patents, mostly on test and reliability of integrated circuits and systems. Dr. Ivanov formerly chaired the Computer Society Test Technology Council (TTTC).
Robin F. B. Turner received the Ph.D. degree in electrical engineering from the University of Alberta, Edmonton, AB, Canada, in 1990. He is a Professor of Electrical Engineering at The University of British Columbia, Vancouver, BC, Canada, where he also holds appointments in the Michael Smith Laboratories and the Department of Chemistry. His research activities include the development of fiber-optic technology and related signal processing and data analysis methods for biomolecular spectroscopy, as well as applications of this technology to research problems in biochemistry, biotechnology, and biomedical engineering
