B2H6 PLAD Doped PMOS Device Performance

B2H6 PLAD Doped PMOS Device Performance Z. Fang, T. Miller, E. Winder, H. Persing, E. Arevalo, A. Gupta, T. Parrill, and V. Singh Varian Semiconductor Equipment Associates Inc., 35 Dory Road, Gloucester, MA 01930, USA

S. Qin and A. McTeer Micron Technology Inc., 8000 S. Federal Way, Boise, ID 83707, USA Abstract. Plasma doping (PLAD) achieves high wafer throughput by directly extracting ions across the plasma sheath. PLAD profiles are typically surface peaked instead of retrograde as obtained from beamline (BL) implant. It may require optimization of PLAD energy and dose in order to match BL doping results. From device optimization point of view, it is necessary to understand the impact of doping parameters to device characteristics. In this paper we present the PMOS device performance with the poly gate and source drain (SD) implants carried out using B2H6 PLAD. The BL control conditions are 2-5 keV 11B+ 4-6×1015 cm-2. Equivalent device performance for p+ poly gate doping is obtained using PLAD with B2H6 / H2. In SD doping using same gas mixture, nearly 50% reduction in SD contact resistance is observed in the PLAD splits. The reduction in SD contact resistance leads to 10-15% increase in device on-current, hence demonstrating the process advantages of using PLAD in addition to having a high wafer throughput. Keywords: Plasma doping, PMOS, process optimization. PACS: 85.40.Ry, 52.77.Dq, 85.30.De

must be accounted for in the device matching process. Both post-implant cleaning and thermal budgets must usually be included, followed by evaluations at the device level to establish an optimum matching condition. This approach ensures that the resultant PLAD recipe is a complete production solution, producing the desired device characteristics and compatible with the integrated process flow. At the same time, working at the device level also allows one to take advantage of PLAD’s throughput flexibility and unique doping features to significantly improve device performance. In this paper we present the steps taken to match PLAD with BL for an advanced PMOS process. The utility of this procedure is proven by both dopant profiles and PMOS device characteristics.

INTRODUCTION The fabrication of advanced CMOS device calls for production worthy solutions for low-energy high-dose applications. Doping of p+ poly gate and source drain (SD) faces significant throughput challenge. It has been demonstrated [1] that the productivity of a beamline (BL) tool drops quickly at low energies due to beam transportation difficulties. Efforts to improve BL productivity include the use of molecular ion sources (“cluster beams”) [2-3], although these do not ultimately offer the high throughput and species flexibility of plasma doping (PLAD) [4]. PLAD completely eliminates beam transportation limitations so it is able to achieve high throughput regardless of wafer size [4-9]. As a result, it is viewed as an attractive doping solution for device manufacturing. Process matching between different BL tools is a common practice in a manufacturing environment where the goal is simply to achieve a good match in beam species, energy, dose, and incident angle distribution. With PLAD, however, differences in coimplanted species, energy distribution, and damage [7]

EXPERIMENT The experimental procedure to match a doping process starts with tests carried out on blanket wafers. For p+ poly gate doping, the gate stack comprises of 700 Å undoped poly-Si / 60 Å nitride / Si substrate.

CREDIT LINE (BELOW) TO BE INSERTED ON THE FIRST PAGE OF EACH PAPER CP866, Ion Implantation Technology, edited by K. J. Kirkby, R. Gwilliam, A. Smith, and D. Chivers © 2006 American Institute of Physics 978-0-7354-0365-9/06/$23.00

249

shallower and surface peaked. The profile tail cannot be moved deeper by increasing PLAD energy because boron penetration to the gate oxide would cause undesired VT shift. For the same reason, no or very little energy contamination is allowed in the BL implant for this application. One of the goals for poly gate doping is to provide adequate dopant activation at the poly-oxide interface. Under the same thermal budget, the shallower PLAD profile means less B atoms diffused to the poly-oxide interface, causing lower dopant activation or higher poly depletion at the interface. Dopant activation is improved at higher PLAD dose. Electrical tests such as Rs, SRP, and Hall effect (not shown) on blanket wafers suggest that beyond 1×1016/cm2 dose, there is little difference between PLAD and BL doped samples. However these tests are not sufficient to ensure that equivalent poly depletion level is reached. Norm. Poly Gate Depletion

For p+ SD doping, bare n-type wafers are used. PLAD implant parameters are selected from the bare wafer tests to determine suitable conditions for device wafer tests. The device structure is a standard self-aligned poly gate PMOS transistor with a channel W/L of 11.7μm/ 0.078μm, and gate oxide thickness is 50Å. MOS capacitor structures are used for CV test. Standard post-implant strip, clean, and rapid thermal annealing process (RTP) are used to activate the dopants. The RTP condition is 965°C for 20s in N2 ambient. The BL control for poly gate doping is 4.5keV 6x1015/cm2 11B+, and for SD doping it is 2keV 4.5x1015/cm2 11B+, at 0° incident angle for both. All PLAD implants used 15% B2H6 / 85% H2 gas mixture to generate ions that are accelerated into substrates biased at negative potential using a pulsed DC power supply. The SD contact is formed by a Ti/W-base deposition. When the poly gate is doped by PLAD, the SD is doped by BL, and vice versa, to facilitate PLAD doping characterization in each case. There are more parameters other than energy and dose in PLAD that require careful consideration. For example, the DC wafer bias pulse width can affect throughput as well as gate oxide integrity [8]. Dilution ratio of B2H6 in H2 can affect surface deposition as well as implanted boron profile characteristics. A mixture of hydride and fluoride such as B2H6 and BF3 can be used to reduce or even eliminate deposition. Detailed discussion on these parameters is outside the scope of this paper. PLAD parameter optimization was completed prior to blanket wafer test.

B Concentration (atoms/cm3)

1E+19 1E+18 1E+17 600

800

PLAD 03E 6kV 1.5E16

In Fig. 2, we compare poly depletion for two PLAD splits with different doses. Even though Rs is saturated above 1×1016/cm2, it can be seen that PLAD dose increase to 1.5×1016/cm2 reduces poly gate depletion to within 2% of BL control. It demonstrates that device wafer test is the best approach to determine how much PLAD dose is needed to achieve same device performance. Despite the small increase in poly depletion, PLAD reduces the device poly line resistance by 2-3%. It is likely that the PLAD surface-peaked profile accounts for these observations. In Fig. 3 we compare VT and IDS. The overlap and linear fitting of the data indicates that there is no significant performance difference between PLAD and BL poly-doped devices. The selected PLAD conditions also did not induce gate oxide damage due to charging, which agrees with previously published QBD data [7]. Finally, the tested device parameters are summarized in Table 1 with the corresponding PLAD vs. BL comparison results.

1E+20

400

PLAD 02E 6kV 1E16

FIGURE 2. Poly gate depletion effect as measured by CV test for two PLAD doses.

1E+21

200

0.9

BL 01C Control

6kV 1E16 PLAD as-imp 6kV 1E16 PLAD anneal 4.5keV 6E15 B+ BL as-imp 4.5keV 6E15 B+ BL anneal

0

1.0

0.8

1E+23 1E+22

1.1

1000

Depth (A) Depth (Å)

FIGURE 1. Comparison of SIMS profiles in p+ poly gate doping. Peaks around 700 Å mark the poly-oxide interface.

RESULT AND DISCUSSION In Fig. 1 we show the as-implanted and annealed SIMS profiles in poly Si for both BL control and PLAD. It is clear that the 6kV B2H6 PLAD profile is

250

The device parameters tested for PMOS SD doping are also summarized in Table 1. In Fig. 4 we show the as-implanted and annealed SD profiles in c-Si for BL and PLAD doping conditions. Although the asimplanted PLAD profile is slightly deeper than BL control, a very good match is achieved after anneal. This close match is a result of optimization within PLAD bias voltage and dose range 4-8kV and 0.52×1016/cm2 respectively. At first glance, it is surprising that a PLAD voltage of 6kV matched both the SD and poly processes, since the BL control process was 2keV vs. 4.5keV. We suggest that this result is associated with differences in channeling into crystalline Si. In B2H6 PLAD, there are more than one ion species being implanted. Under the same PLAD bias, light ions go deeper but their contribution to profile tail is limited due to their relatively low concentration. The majority ions in plasma are B2Hx+ and they made much less contribution to profile tail even with channeling. Meanwhile, the molecular species B2Hx+ tends to cause more crystal damage [7] and therefore reduces channeling for all ion species. In addition, deposition of surface neutrals during PLAD creates a thin layer that tends to de-channel accelerated dopant species. It is possible that one or more such mechanisms leads to less channeling of the PLAD process that must be compensated by increasing the bias voltage. The origin of the surface peaked profile in PLAD has been explained elsewhere [9]. We shall focus on its impact on device performance when the SD region is doped with such a profile. As indicated in Fig. 4, the close match in annealed profile would suggest similar junction characteristics, which is confirmed by Rs, SRP, and Hall measurements. According to Table 1, the SD series resistance measured on device wafers has only 2-3% increase for PLAD. However, the SD contact resistance has dropped ~50% for PLAD as indicated in Fig. 5. This significant improvement in

FIGURE 3. PMOS drive current IDS against threshold voltage VT after p+ poly gate doping.

TABLE 1. Device Performance Comparison. Doping Device Parameter Compared to BL Step PLAD Is Poly gate depletion less than 2% higher Poly line resistance 2-3% lower Threshold voltage VT statistically equal Sub-threshold slope statistically equal p+ poly gate Drive current IDS less than 2% higher doping SD breakdown statistically equal voltage BVSD Gate oxide VBD statistically equal statistically equal Gate oxide QBD SD contact resistance ~50% lower SD series resistance 2-3% higher Drive current IDS 15-20% higher PMOS SD Threshold voltage VT statistically equal doping Sub-threshold slope statistically equal SD breakdown statistically equal voltage BVSD

B Concentration (atoms/cm3)

1E+23

6kV 2E16 PLAD as-imp 6kV 2E16 PLAD anneal 2keV 4.5E15 B+ BL as-imp 2keV 4.5E15 B+ BL anneal

1E+22

1E+21

1E+20

1E+19

1E+18 0

200

400

600

800

1000

Depth (Å) Depth (A) FIGURE 5. Comparison of SD contact resistance after SD region doped by PLAD and BL control.

FIGURE 4. Comparison of SIMS profiles in c-Si for SD doping conditions by PLAD and BL control.

251

contact resistance is attributed to the surface peaked profile. It is known that contact resistance is sensitive to contact material type as well as to the carrier properties near the contact region. Higher surface B concentration leads to higher carrier concentration for the same anneal, therefore a surface peaked profile is advantageous in contact resistance reduction. The lower contact resistance is translated into more drive current as indicated in Table 1. The SD drive current IDS is increased by 15-20% despite a 2-3% increase in SD series resistance. Although the PLAD bias is 6kV compared to BL control of 2keV, there is no detectable VT and sub-VT slope change. This is a result of successful device parametric tuning with a careful control of lateral dopant profile.

FIGURE 7. Comparison of SD breakdown voltage after SD region doped by PLAD and BL control.

ACKNOWLEDGMENTS The authors would like to take this opportunity to thank the PLAD technical team, Steve Grimmett and Steve Romero for their great support.

REFERENCES 1. A. Renau, D. Downey, “Review of low energy doping and activation technologies", Semi Forum Japan, June 2003. 2. D. Jacobson, T. Horsky, W. Krull and K. Cook, “Cluster Boron™: A New Doping Material for P-Type UltraShallow Junctions,” Int. Conf. on Ion Implant. Tech., 2004, p126. 3. J. Borland et al., Solid State Technology, May 2004, p.53. 4. R. Liebert, S. Walther, S. Felch, Z. Fang, B. Pedersen, O. Pedersen, D. Hacker, “Plasma Doping System for 200 and 300mm Wafers”, Int. Conf. on Ion Implant. Tech., 2000, p.472. 5. S.R. Walther, S. Mehta, U. Jeong, and D. Lenoble, “Formation of extremely shallow junctions for sub-90nm devices,” Surface and Coatings Technology, Vol. 186, No. 1-2, 2 August 2004, p. 68. 6. A. Renau and J. Scheuer, “Comparison of Plasma Doping and Beamline Technologies for Low Energy Ion Implantation”, Int. Conf. on Ion Implant. Tech., 2002. 7. Z. Fang, E. Arevalo, T. Miller, H. Persing, E. Winder, and V. Singh, Ext. Abstr. 5th International Workshop on Junction Technology, June 2005, p. 67. 8. D. Henke, S. Walther, J. Weeman, T. Dirnecker, A. Ruf, A. Beyer, and K. Lee, “Characterization of Charging Damage in Plasma Doping”, Int. Conf. on Ion Implant. Tech., 2002. 9. L. Godet, Z. Fang, S. Radovanov, S. Walther, E. Arevalo, F. Lallement, J.T. Scheuer, T. Miller, D. Lenoble, G. Cartry, and C. Cardinaud, JVST B, to be published.

FIGURE 6. PMOS drive current IDS against threshold voltage VT for SD doping.

The device performance boost with VT aligned can be seen clearly in Fig. 6. The linear fitting to IDS - VT plots suggests that there is 10-15% increase in IDS for PLAD doped devices, primary due to reduction in SD contact resistance. This serves as a good example of taking advantage of new features from alternative doping technology. As pointed earlier, there are other PLAD parameters that can be further optimized for better results. The SD breakdown voltage BVSD is a test of junction quality after forming the SD region. In Fig. 7 we compare BVSD for PLAD and BL doped devices. There is no difference found in BVSD as indicated in Table 1 as well as in Fig. 7. In conclusion, we have demonstrated that PMOS devices with its poly gate doped by PLAD perform equally well as those doped by BL implantation. For devices with SD region doped by PLAD, significant device performance enhancement is observed, which is attributed to the surface peaked profile from PLAD.

252