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Phys. Status Solidi A, 1–6 (2012) / DOI 10.1002/pssa.201200343
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Contact engineering for nano-scale CMOS Muhammad Hussain*, Hossain Fahad, and Ramy Qaisi Integrated Nanotechnology Lab, Electrical Engineering, King Abdullah University of Science and Technology, Thuwal, Saudi Arabia Received 6 June 2012, revised 27 July 2012, accepted 30 July 2012 Published online 12 September 2012 Keywords contact resistance, field effect transistor, nano-devices, nanotube, nanowire * Corresponding
author: e-mail
[email protected], Phone: þ966 544 700 072, Fax: þ1 888 908 5614
High performance computation with longer battery lifetime is an essential component in our today’s digital electronics oriented life. To achieve these goals, field effect transistors based complementary metal oxide semiconductor play the key role. One of the critical requirements of transistor structure and fabrication is efficient contact engineering. To catch up with high performance information processing, transistors are going through continuous scaling process. However, it also imposes new challenges to integrate good contact materials in a small area. This can be counterproductive as smaller area results in
higher contact resistance thus reduced performance for the transistor itself. At the same time, discovery of new one or two-dimensional materials like nanowire, nanotube, or atomic crystal structure materials, introduces new set of challenges and opportunities. In this paper, we are reviewing them in a synchronized fashion: fundamentals of contact engineering, evolution into non-planar field effect transistors, opportunities and challenges with one and two-dimensional materials and a new opportunity of contact engineering from device architecture perspective.
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1 Introduction Today’s world has significant dependency on information technology and computation. With gradual growth of communication technology, we have embarked on a journey where digital logic continuously serves the mankind. Digital logic depends on former microelectronics and today’s nanoelectronics. With sub100 nm gate length, semiconductor industry is on the path of ultimate scaling of its classical planar complementarymetal-oxide-semiconductor (CMOS) devices. Scaling provides a direct benefit of achieving higher drive current, which directly results in reduction of inverter delay. However, it also poses new set of challenge especially in the front of power management. Smaller devices are leaky enough to increase the unwanted power consumption resulting in hotter device surface and reduced battery lifetime. This is one of the critical challenges for today’s portable electronic device oriented human life. At the same time, scaling of the device does not happen only laterally (example: gate length), it also happens vertically (example: gate dielectric). And as a result, we need to scale the source/drain (S/D) junctions also. According to International Technology Roadmap for Semiconductor (ITRS) 2011 report, in near future, some major challenges with bulk planar CMOS transistors are
achieving doping profiles in the source/drain extension regions to form ultra shallow junctions to counter shortchannel effects (10 nm), and at the same time, optimizing the sheet resistance (500 V/&) [1]. It is also equally important to make low-resistance contact to shallow, highly doped source/drain regions. When we look carefully, we can see that while the gate length is being reduced, depth of the source/drain junctions is getting shallower while the contact sheet resistance is increasing (Table 1). With scaling impact on parasitic resistance, it is increasing and it needs to be well addressed. Another major trend is increased impact of source-drain contact resistance. All these trends clearly indicate that good and stable contact engineering is very important for classical CMOS devices. Typically the ratio of channel width to channel length (W/L) of devices remains same with scaling and hence the device resistance remains the same too. However, since the contact hole size is decreasing, contact resistance is increasing proportionately. As per ITRS 2011, nonequilibrium doping levels at the metal/semiconductor appear to be needed by 2010 when an interfacial contact resistivity of 5 108 Vcm2 will be needed to meet device performance objectives [1]. ß 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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M. Hussain et al.: Contact engineering for nano-scale CMOS
Table 1 Scaling trend in modern CMOS devices [1].
areas. Historically salicidation of metal is preferred because of its process compatibility, reduced sheet resistance, and minimal electromigration. Varieties of metals have been used for salicidation (Table 2). Typically a metal is deposited and then it goes through subsequent processes like thermal annealing or such to form alloys (silicide). As-deposited films are often amorphous or micro to nano-crystalline thus their carrier mobility is low. Thermal annealing typically helps increasing the grain sizes and to form a stable phase of poly-crystalline alloys with reduced resistivity. When annealing can be advantageous, we also have to be cautious about the stress effects rise from the annealing as the stress can alter the electrical properties of the junctions and channels. Another important aspect is doping redistribution during salicidation process as diffusivity in silicide is very high. Out diffusion of dopant from source and drain area can reduce the surface doping density and thus results into higher contact resistance. In addition to this, dopant redistribution from poly silicon gate can cause Fermi level change impacting the work function and thus threshold voltage change. If threshold voltage increases, we face the challenge with lower drive current and associated problems to drive the device at higher voltage level than it is designed for. From contact material perspective, not all metals are scalable for contact engineering. As an example, typically sputtering is used for metal deposition used for salicidation. However, previously widely used contact metals like titanium or cobalt consume much larger amount of silicon to form their silicides. On the other hand, nickel is today the metal of choice for contact engineering as it consumes lesser amount of silicon. Another important factor is line width scaling. From that perspective, although TiSi2 had lower silicon consumption ratio than that of cobalt, achieving a stable phase for good contact engineering through TiSi2 is very difficult with reduced line width. To mitigate the higher silicon consumption ratio with cobalt an additional thin barrier layer of titanium is used before cobalt deposition. The most dramatic change happened when the industry moved in favor of nickel silicide. Although nickel silicide has poor stability issue at higher temperature, it was scalable. Interestingly, when the industry also moved towards low-k
critical feature
2011
2012
2013
2014
2015
physical gate length (nm) contact junction depth (nm) contact sheet resistance (V/&)
24 29 9.1
22 26.7 9.9
20 24.7 10.8
18 22 12.1
17 19.8 13.5
Figure 1 (online color at: www.pss-a.com) A classical planar metal-oxide-semiconductor field-effect-transistor device. Various parasitic resistances and capacitances are shown. Increasingly contact resistances (Rc) are dominating the parasitic resistance.
To control the issue of rising contact resistance (a) dopant concentration at the interface needs to be maximized, (b) a lower-barrier-height junction material such as silicon/ germanium is required as the contact junction and/or c) low-barrier-height, dual metal (silicides) needs to be used to contact nþ and pþ junctions. An alternative, yet to be practically demonstrated, is to form Schottky barriers that serve as junctions and contacts. 2 Fundamentals of contact engineering Contact engineering is a fundamental module for CMOS device processing. Figure 1 shows the various parasitic resistances and the presence of contact resistances in the source/drain
Table 2 Various materials used to form silicide [2]. silicide
thin film resistivity
stable on silicon up to (8C)
nm of silicon consumed per nm of metal
nm of resulting silicide per nm of metal
barrier heights to n-Si (eV)
PtSi TiSi2 (C54) CoSi2 NiSi WSi2 MoSi2 TaSi2
28–35 13–16 14–20 14–20 30–70 40–100 35–55
750 900 950 650 1000 1000 1000
1.12 2.27 3.64 1.83 2.53 2.56 2.21
1.97 2.51 3.52 2.34 2.58 2.59 2.41
0.84 0.58 0.65
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0.67 0.64 0.59
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dielectric for interconnect and metallization level the high thermal budget requirements got reduced and nickel silicide made its place as a good contact engineering metal in most of today’s advanced CMOS devices. The conduction mechanism for metal/semiconductor contacts is a function of barrier height and depletion width. Mainly three types of conduction are possible: (i) thermionic; (ii) thermionic-field emission; and (iii) field emission. Typically when a depletion width is large which in turn lowers the barrier height can help in thermionic emission resulting in Schottky contact. On the other hand, when the depletion width is low enough that charges can tunnel through it is generated from field emission and resulting into Ohmic contact. From band alignment perspective in Schottky contact metal, Fermi level energy resides in between semiconductor conduction and valence band. In contrary, if the metal Fermi level is located below the valence band or above the conduction band then it is the sign of Ohmic contact. It is to be noted that Ohmic contact is much preferred as it does not interrupt the charge injection. Since depletion width depends inversely on doping concentration in the semiconductor thus it is a well-known practice to increase the doping concentration in bulk silicon. Thus the specific contact resistivity (the main figure of merit in contact engineering) depends on doping concentration in the semiconductor, the metal semiconductor work function or the barrier height and the effective mass of the carrier. As easily understood, the higher the barrier height, the lower chance of thermionic emission as it requires more external energy typically in the form of thermal energy and voltage, and at the same time the more the effective mass, the heavier the charges and lower their mobility resulting into increased contact resistivity. One point of concern is doping density cannot be scaled below solid solubility. Thus to lower the barrier height low band gap material such as silicon– germanium (SiGe) can be used and thus for nearly 5 years semiconductor industries are using elevated source/drain profile with SiGe materials for p-channel FETs in CMOS devices. In addition to this, SiGe source/drain helps increasing the hole mobility as lattice mismatch between silicon and SiGe compresses the channel area, thus exerting compressive strain along the p-FET channel direction and reducing the series resistance, to let holes transport fast in p-channel MOSFETs. Dual silicide is also another interesting option to meet the fast paced demand of contact engineering scaling. One report shows platinum silicide for a p-channel MOSFET and erbium silicide for n-channel MOSFET (fp, fn ¼ 0.22 eV, 0.3 eV, respectively) [3]. One promising solution comes from the perspective that the interface properties rather than bulk properties in silicon governs the Schottky barrier height (fB). There are two main hypotheses behind this mechanism: (i) dipole formation due to bond polarization at the metal-semiconductor interface and (ii) metal-induced gate states (MIGS). According to the MIGS theory, passivating the gap states of the underlying semiconductor will relieve the Fermi-level pinning effect, and hence recover the unity relation between fB and the www.pss-a.com
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metal work function. Mitigation of Fermi level pinning effect by the insertion of an ultra-thin dielectric has been experimented successfully to achieve low barrier height of 0.2 eV with Mg and Yb contacts to n-Si with interfacial silicon nitride [4]. In another interesting approach, near band edge Schottky barrier height has been achieved by using tantalum nitride (TaN) with aluminium oxide (AlOx) and silicon oxide interfacial layer or lanthanum oxide (LaOx) or silicon oxide (SiO2) interfacial layers [5]. Both of these highk dielectrics are well known for their dipole induced work functioning tuning capability. Their (high-k dielectrics) inclusion both passivates and modulates the Schottky barrier height of tantalum nitride on n-type silicon by more than 0.2 eV, resulting in nearly band-edge modulation with 2 nm of dielectrics. Although thicker dielectric may reduce the barrier height but it can hinder the tunnelling probability. Since atomic layer deposition (ALD) is usable for both of these high-k dielectrics, it is possible to use them for non-planar CMOS devices. 3 Transitioning into non-classical CMOS While scaling is the major catalyst to continue the growth of semiconductor devices and its various applications, it also introduces new challenges like short-channel effects. Nonplanar CMOS devices like multi-gate (MugFET) devices have been introduced to achieve tighter electrostatic control over the channel area [6]. Although theoretically it sounds like a sound solution, implementation of such device architecture is challenging. First the channels (fins) are vertically aligned and formed using reactive ion etching. Patterning sub-lithographic fin dimension (example fin width is 20 nm or below) is a major challenge. Also, fins are patterned in arrays where the distance between adjacent fins are small too (50 nm or below). Fin height is also required to be such so an acceptable aspect ratio is maintained to achieve appreciable amount of current. Now, with the presence of multiple fins in arrays cause shadowing effect hindering uniform doping profile in the channels. Thus to address all these challenges, fins go through the epitaxy process to add more lateral silicon to the existing fins so they touch each other (Fig. 2). Now, typically fins are formed in 40 or more in an array. To have an elevated or raised source
Figure 2 (online color at: www.pss-a.com) Hexagonal shaped epitaxial silicon is formed around the silicon fin (blue). If they are allowed to grow more, they can join with each other. ß 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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Figure 3 (online color at: www.pss-a.com) Nickel silicide formation around a fin, and with increased amount of nickel nearly the whole silicon fin channel area is consumed.
and drain is comparatively easy [7] but the contact landing may take a larger area defeating the purpose of increasing number of devices in a given area to increase functionality in ultimate consumer electronics. Also, contact metal deposition-using sputtering can damage the fin profile and during contact hole etch the fins can be severely damaged. Therefore, individual contact landing has also been considered for contact engineering in MugFET devices. One interesting observation is during formation of metal silicide silicon in the fins can be consumed in such a way that the effective channel area can be severely reduced to have any appreciable amount of current (Fig. 3). Another critical factor to be noted is jointed fins may increase the spreading of resistance from the silicide/silicon interface to the fins through source/drain region and under the spacer [8]. In addition to transitioning to non-planar CMOS devices, semiconductor community is actively thinking about introducing alternate high mobility channel materials to achieve higher drive current. The present trend suggest germanium or a fraction of silicon germanium is preferred for p-channel MOSFETs and III–V materials like indiumgallium-arsenide (InGaAs, InSb, and such) are materials of interest for n-channel MOSFETs. For p-channel MOSFETs, the most metals in contact with p-type germanium have their work function pinned to the valence band of germanium, making it easier to form Ohmic contacts to Ge. However, this at the same time causes Fermi level pinning at the edge of valence band resulting in higher interfacial resistance. For III-V devices with increased doping density, we can lower the barrier height and it also introduces an interfacial dipole, which ultimately reduces the effective Schottky barrier height more. 4 Contact engineering for one and twodimensional nano-devices Over the last decade, exciting discovery in one and two-dimensional nanomaterials has instigated much interest about the vast promise of this genre of science [9, 10]. At the same time, while the contact engineering is getting tougher with bulk planar or non-planar CMOS devices, it brings new set of research opportunities for both one and two-dimensional nanomaterials based devices. There are two ways to form contact in this kind of devices: one is to form a contact with self-assembled nanowire or nanotube structured devices (two dimensional nanomaterials) which ends abruptly generating end bonded ß 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
M. Hussain et al.: Contact engineering for nano-scale CMOS
contact and in the other variation metal pads are landed directly on top of the one and two dimensional nanomaterials [11]. The later is known as side-bonded contacts. One of the important features of these two specific contacts is for an end bonded contact where the nanowire or the nanotube is connected to a metal at the edge has longer area for the band to be bent as that happens across the length of the nanowire or the nanotube. However, this becomes a major challenge for side-bonded contact where there is not enough area within the diameter of the nanowire or nanotube. Typically in bulk semiconductor devices, heavy doping helps in reducing the depletion width. However, in a two dimensional nanowire or nanotube devices doping can take significant amount of area thus to reduce the effective diameter of the device. Also, maintaining uniform doping profile is a significant challenge, which is associated with absence of a definitive metrology method to profile the doping distribution in such materials. For silicon-based nanomaterials oxidation can also play important and derogatory role. One key example of silicon-based nanowire contact formation is with nickel salicidation, which is widely used in bulk CMOS devices [12, 13]. For nanomaterials, the reaction mechanism varies significantly. Crystallographic orientation of the silicon nanowires in conjunction with stress build up due to salicidation can significantly impact the stability of the contact. When a thin nickel film is deposited and annealed, the orthorhombic d-Ni2Si is formed first which is followed by NiSi and finally NiSi2. Although NiSi is the preferred phase, for a Si (112) nanowire, the u-Ni2Si is formed at 300 8C, which does not show up in bulk silicon at such a low temperature. This phase remains stabilized till 600 8C and then at 700 8C the silicide forms whiskas. For a Si (111) nanowire, epitaxial NiSi2 is formed first and remains stable till 700 8C when the low resistivity NiSi is formed temporarily before it turns into NiSi2 at higher temperature. In case of germanium nanowire, nickel contact pads react to form axial nickel-germanide at low temperature (350 8C). At a slightly higher temperature of 450 8C fracture starts to happen due to stress issue. However, by limiting the temperature and increasing the annealing time it is possible to grow long nickel germanide segments [14]. Carbon nanotube, which has excellent mobility suffers from presence of Schottky barrier at the nanotube/metal interface [15]. The low dimensionality of the nanotube is probably the root cause of this. This phenomenon is amplified by non-uniformity in dimensionality. The Schottky barrier between metal contacts and the semiconducting carbon nanotube can be tuned by modifying the electrodes’ work function by hydrogen treatment), vacuum anneal, and post-contact deposition anneal to desorb oxygen; all can help achieve a smaller barrier [16–19]. Interesting possibilities exist with gallium nitride nanowires. Titanium/gold conatct in such nanowire devices show non-linear behavior [20]. However, with UV illumination it shows linear Ohmic conatct type behavior. Probably UV illumination produces excess electroncs to move to a www.pss-a.com
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Table 3 various materials used to form silicide. graphene formation process
contact metal
contact resistivity or resistance
epitaxy on silicon carbide [24] solution processed [25] graphene oxide reduction [26]
Ti/Au
7.5 108 Vcm2
Ti Al
0.1 kVmm2 no contact resistance value, but high output current 7500 Vmm 750 Vmm
chemical vapor deposition-based growth on nickel [27] epitaxy on SiC (4H-SiC) [28] chemical vapor deposition-based growth on copper foil [29]
Ni/AuTi/Pd/Au
Cr/AuTi/Au Au
5 mVcm2 60 mVcm2 340 Vmm
different energy state resulting into narrower depeletion region and higher tunneling probability. For zinc oxidebased nanowires, a titanium/gold conatct forms Ohmic conatct whereas platinum-based conatct forms Schottky conatct [21]. Moving towards two-dimensional atomic crystal structures like graphene, MoS2, etc. – exiciting as well as intriguing properties of these materials make them promising for further exploration in transistors. There remain, however, several challenges in constructing graphene devices with higher performance. One critical challenges of making these materials compatible for transistor applications is to have well control over the metal-material contact resistance. Theoretical studies suggest charge injection from the metal may change the properties of graphene adjacent to the contact and that can result into p–n, p–p, or n–n junction formations [22, 23]. We have tried to capture a synoptic understanding of the research trend in contact engineering for graphene (Table 3). The table suggests that there is no clear winner. A recent study indicates that the electronic structure, electron phonon coupling, and the doping level in gold plated graphene are mostly retained [29]. In some reports, oxygen plasma has been used to enhance adhesion between the metal and the graphene to form good Ohmic contacts to graphene [24, 30]. It is to be noted, upto the best of our knowledge no conatct engineering study is reported on MoS2. 5 Contact engineering from device architecture perspective Recently, we have demonstrated that nanotube architectures with core-shell gate stacks are more advantageous than nanowire architectures for field-effecttransistors applications. With conventional channel materials like silicon and silicon germanium (SiGe), we have shown that a nanotube architecture transistor is capable of generating high drive current resulting into high www.pss-a.com
Figure 4 (online color at: www.pss-a.com) Nanotube field effect transistor with core-shell gate stacks. When the nanotube channel thickness is below 10 nm, full volume inversion takes place and the device generates higher Ion.
performance information processing capability, lower leakage potentially transformative for longer battery lifetime and area efficiency indicates more functionalities per chip [31, 32]. A nanotube field effect transistor operates near the full volume inversion and capable to leverage the presence of all the density of states for higher current generation. Two gates (core–shell: inside–outside) help mitigating short-channel effects in a thin nanotube channel of 15 nm or below. Now, from a contact engineering perspective of a 15 nm node compatible CMOS design and process rule suggests that to match the current generated per silicon nanotube transistor, ten to fifteen nanowire transistors are required. Thus, the corresponding contact area results into 85% more area requirement by nanowire transistors than that of a single nanotube transistor to be competitive from performance perspective. This is an excellent opportunity to look at the contact engineering from a different perspective as contact engineering is not only to scale the material and its electrical properties but to ensure that we are maintaining the area efficiency – a direct benefit of device scaling (Fig. 4). 6 Conclusion In this review on contact engineering for nanoscale transistors, we have described the trend of contact engineering in classical CMOS devices, their roles on performance and area efficiency. We have also extended the discussion to their evolution during the transition of classical planar CMOS devices to non-classical non-planar CMOS architectures. Next, we have portrayed the challenges and opportunities of contact engineering for one and twodimensional materials. And finally, we have reported a new perspective about contact engineering in context of device architecture. All these discussions seriously point out the necessity of scaled and stable contact materials with low contact resistance. Acknowledgements We deeply appreciate the generous research grants provided by King Abdullah University of Science and Technology. ß 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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