Current Mode Sense Amplifiers Design in 0.25um CMOS Technology

Current Mode Sense Amplifiers Design in 0.25um CMOS Technology A. CHRISANTHOPOULOS1, Y. MOISIADIS2, Y. TSIATOUHAS1, G. KAMOULAKOS1 1

ISD S.A. 22 K.Varnali Str., 152 33 Halandri, Athens GREECE 2

University of Athens Department of Informatics, 157 84, Athens GREECE

Abstract: This paper presents a comparison of different current mode sense amplifiers in 0.25um CMOS technology. The sense amplifiers under consideration are suitable for current sensing in SRAM and flash memories. Simulation results are given regarding the delay time for different power supply voltages Vdd and bitline capacitances values. Furthermore comparative results are also given for the energy dissipated per sensing operation, while worst case and high temperature simulations are included, in order to expose limitations of the sensors in various operating conditions.

Key-Words: Sense Amplifiers, Memory periphery circuitry

result severely limit the sensing speed by introducing extra signal delays. Furthermore, the small-signal voltage gain provided by submicron transistors decreases as the channel length becomes smaller, due to channel length modulation. Both of these problems can be overcome when current signals are sensed rather than voltage signals [1]. The current sensing approach seems to be more suitable for realizing high-speed and large-size memories, for low voltage operations, as no large voltage swing on the bit-lines is needed. According to our knowledge this is the first comparative study of modern current mode SA, in the submicron technology area. Five of the most promising SA are compared in terms of the delay time and power dissipation. The effect of the bit-line capacitance in the delay time is also examined. Finally worst case and high temperature simulations are presented.

1. Introduction Semiconductor memories are usually considered as the most vital component of digital logic system design such as computers, microcontrollers, DSPs and other microprocessor-based applications. Recent years there is also an increased tendency of embedding the part of memory (RAM and ROM) in the logic circuit, in order to achieve higher levels of integration and speed. As a result, the performance of the memory array and the limitations of the memory periphery circuitry (decoders, charge pumps, level shifters, sense amplifiers) can seriously affect the overall system performance in terms of power dissipation and speed. One of the most critical circuits in the periphery of a memory, is the sense amplifier (SA). Sense amplifiers are strongly related to the access time of memory, as they used to retrieve the stored memory data, by amplifying small signal variations in the bitlines. Designing fast, low-power and robust sense amplifier circuits is a challenge, especially in the area of submicron CMOS technologies. This is due to the fact that in modern memory designs, bit-lines tend to be larger, exhibiting a significant capacitance. As a

This work has been supported by the PANORAMA ESPRIT-28305 E.U. project 1

2. Circuits description

As a result, the output nodes of the sense amplifier are no longer loaded with the bit-line capacitance and the sense amplifier is able to response very rapidly. Also due to the small impedance at the sensing node, the highly capacitive bit lines change by only a few tenths of a volt during the sensing operation. Transistors M1-M4 form a traditional CMOS cross-coupled latch and have W=1.25um. M5 and M6 are biased in the linear region and provide a low impedance clamp between the bit-line and the reference potential Vref, which is equal to 0.1V. Next, the simple four-transistor (SFT) current mode sense amplifier [4] is shown in Fig.3. This SA presents a virtual short circuit to the bit-lines, thus reducing the sensing delay, and rendering it practically insensitive to the bit-line capacitance. The circuit operates as follows: In the sensing phase the gatesource voltage of M1 will be equal to that of M3, since their currents are equal, their sizes are equal, and both transistors are in saturation. This voltage is presented by V1. The same applies to M2 and M4. Their gatesource voltage is presented by V2. It follows that, since Ysel is grounded, the left bit line (BL2) will have voltage V1+V2, and the right bit-line (BL1) will also have the same voltage.

The operation of the sense amplifiers presents two common phases: Precharge and Sense signal amplification. At the precharge phase the appropriate signals to force the sensing nodes at certain potentials are applied. At the sense operation a comparison is made between the currents of the sensing nodes. The result of this comparison retrieves the contents of the selected memory cell. The conventional current mode sense amplifier (CONV) [2] is illustrated in Fig.1. The design of the sensor is based on classic cross-coupled latch structure (M4-M7) with extra circuitry for sensor activation (M8) and bit-line equalization (M1-M3).

Fig.1: The conventional current mode (CONV) sense amplifier Fig.2 presents the clamped bit-line sense amplifier (CBL) [3]. It exhibits a fast response speed, almost independent of the bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node, within the sense amplifier, that has only a minimal effect on the speed of the circuit.

Fig.3: The simple four transistor (SFT) sense amplifier When the current of the reference cell is bigger than the current of the data cell (Iref>Icell), it follows that the right-hand leg of the sense amplifier pass more current than the left-hand leg. In fact the difference between these currents is I=Iref-Icell. The drain currents of M3 and M4 are passed to the current transporting data lines DL1 and DL2. The differential data lines current is therefore equal to the current I. Thus we obtain current sensing. The sensing delay is unaffected by the bit-line capacitance since the sensing nodes are detached from the bit-lines. This SA has low cost since only four transistors are placed on bit-line pitch (M1-M4). The rest transistors are common to all bit-lines of a block. The pmos bias type (PBT) current mode sense amplifier [5] is shown in Fig.4. At the precharging phase the bit-lines have the same current which is Io.

Fig.2: The clamped bit-line (CBL) sense amplifier 2

During the sensing phase, if for example Iref is bigger than Icell, the current flowing from bit-line BL2 to the amplifier is reduced to Io-ÄI, while the current flowing from bit-line BL1 to the amplifier remains at Io. Consequently, the current that flows through M1 and M3 is reduced to (Io- ÄI)/2, while the current that flows through M2 and M4 remains at Io/2. The current which flows through M5 is Io/2 because the current flowing through M2 and M6 is the same, and the current of M5 is the mirrored current of M6. Therefore, the load capacitance Cload2 is charged up by INV2 since M5 draws more current than M1 provides. In almost the same manner, the load capacitance Cload1 is discharged by INV1 since M4 provides more current than M8 draws. This way, the voltage of terminal OUTL drops while the voltage of terminal OUTR rises.

Fig.5. This SA has also separated inputs and outputs for low voltage operation and for the acceleration of the sensing speed. This aspect is achieved inserting two extra transistors (M6-M7) in the cross-coupled structure of the sensor that each one is driven by a bitline.

3. Simulations results and conclusions All the above mentioned circuits have been simulated using the ELDO simulator, for the 0.25um CMOS technology of ST-Microelectronics. The threshold voltages of the NMOS and PMOS transistors, for the typical case, were 0.557V and 0.546V respectively. All the simulations were carried out keeping the same fan-in and fan-out. Also the transistors involved in the cross coupled part of the SAs and the transistors of the PBT SA which involved in the current mirror topology were of equal size W/L=1.25um/0.25um. Icell and Iref, represent the currents for the memory and the reference (dummy) cell respectively. During the simulations Icell was a value of 10uA for the high state and 1nA for the low state, while Iref was equal to 100nA. A capacitance of 50fF used as a load in the output node Figs. 6a-6c presents the worst sensing delay time, for different capacitance values of the bit line. The CBL and DLT circuits, exhibit a performance independent of the bit-line capacitance (Cbl) value, while the performance of the rest sense amplifier circuits is strongly depended on the Cbl. More specifically Figs. 6b and 6c present the worst case simulation result according to the slow transistors model available in our technology for different temperatures. It results that the CBL and DLT are almost insensitive of technology and temperature variations. Figs. 7a-7c show the worst sensing delay time, for different values of the power supply voltage. The DLT can sufficiently operate with low voltages, even under worst case and high temperature conditions, with no significant speed degradation. The performance of the CBL design is limited down to 1.5V, while for lower Vdd values the delay time significantly increases. The sensing delay time of the PBT is not seriously affected by the Vdd reduction. Simulations results indicate that the CONV, SFT and PBT sensing circuits, are able to operate in a very limited range of Cbl and Vdd values. On the other hand, DLT and CBL appear to be very robust circuits with excellent behavior, under extreme operating conditions. In Figs. 8a-8c, the energy dissipated per sensing operation, is illustrated. As it arises, the SFT and DLT sense amplifiers are applicable for low power operations.

Fig.4: The pmos bias type (PBT) sense amplifier

Fig.5: The differential latch type (DLT) sense amplifier The last SA is a differential latch type sense amplifier (DLT) [6], [2] and it’s schematic is shown in 3

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Fig.7: Simulation sensing delay time versus Vdd (Cbl=1pF)

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References: [1] C. Toumazou, Fj. J. Lidgey, D.G. Haigh. ‘Analoque IC design: The current-mode approach (EII circuits and systems series)’, published 1993. [2] T. Uetake, Y. Maki, T. Nakadai, K. Yoshida, M. Susuki, R. Nanjo. ‘A 1.0ns Access 770MHz 36Kb SRAM Macro’. 1999 Symposium on VLSI Circuits Digest of Technical Papers. pp.109-110 [3] Travis N. Blalock, and Richard C. Jaeger. ‘A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier’. IEEE Journal of Solid-State circuits, vol.26, No.4, April 1991. pp. 542-548 [4] Evert Seevinck, Petrus J. van Beers, and Hans Ontrop. ‘Current-Mode Techniques for HighSpeed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM’s’. IEEE Journal of Solid-State circuits, vol.26, No.4, April 1991. pp. 525-536 [5] Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima and Akihiro Shimizu. ‘A 7-ns 140-mW 1Mb CMOS SRAM with Current Sense Amplifier’. IEEE Journal of Solid-State circuits, vol.27, No.11, November 1992. pp. 1511-1518 [6] T. Seki et al. ‘A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier’, IEEE Journal of SolidState circuits, vol.28, No.4, April 1993. pp. 478483

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