Design philosophy for nanoelectronic systems, from SETs to neural nets

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl. 2000; 28:563–584

Design philosophy for nanoelectronic systems, from SETs to neural nets Arthur van Roermund1 and Jaap Hoekstra2; ∗ 1 Mixed-signal

Microelectronics Group; Faculty of Electrical Engineering; Eindhoven University of Technology; The Netherlands 2 Electronics Research Laboratory; Subfaculty of Electrical Engineering; Delft University of Technology; Delft 2628 CD; The Netherlands

SUMMARY This paper describes an overall policy for the design of nanoelectronic systems, showing how speci c properties of quantum devices can be exploited instead of being counteracted, by introducing unconventional design approaches. Single-electron tunnelling (SET) circuit ideas, as components for neural networks, are described in more detail. It is argued that the orthodox theory of single-electron devices is not appropriate for circuit design and simulation, and needs reconsideration. An overview of SET circuit designs for neural nodes is given. Copyright ? 2000 John Wiley & Sons, Ltd.

1. INTRODUCTION Nanotechnology is a generic term for all kind of emerging and very promising nanoscale technologies, among which are mechanical nanotechnology, with nanoscale mechanical instruments, molecular nanotechnology, with nanoscale supermolecules and nanoelectronics with nanoscale electronic devices. Nanoscale electronics is still at its infancy. The majority of the papers that appear in literature are discussing physical and the device–physical aspects, and focus on the transport phenomena and basic potential device properties. A minority of the papers describe basic electronic circuits. Only few go higher and describe system aspects. The use of nanoelectronics is motivated by several aspects. First of all: the basic devices can be small, extremely small. Second: it has the potency to operate with very low supply power. Third: the quantum properties that appear at nanoscale in principle, represent a huge increase

∗ Correspondence

to: Jaap Hoekstra, Electronics Research Laboratory, Subfaculty of Electrical Engineering, Delft University of Technology, Delft 2628 CD, The Netherlands. Contract/grant sponsor: European Mel-ari/NID ‘ANSWERS’ project Contract/grant sponsor: Delft Inter-faculty Research Center ‘Novel Computational Structures based on Quantum Devices’

Copyright ? 2000 John Wiley & Sons, Ltd.

Received 28 April 2000 Revised 13 June 2000

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Figure 1. Levels in nanoelectronic system design. The sections that describe the various levels are indicated.

in signal-processing power. Together, this promises a gigantic increase in processing power for future ‘chips’ at very low dissipation. We ‘just’ have to be able to manage it; we will have to exploit the new properties. This vision is opposite in that sense to the conventional evolutionary approach, based on the Moore law, which still sticks to the conventional MOS transistor and which tries to counteract the eects that are introduced by the sizing, instead of using them. Both views have in common that they see shrinking down to nanoscale dimensions as inevitable. The physical background of quantum behaviour are the Coulomb energy and the lower dimensionality. The Coulomb energy is responsible for the eect that for very small capacitances, individual electrons aect the transport of other electrons. ‘Lower dimensionality’ implies that in one, two, or even three directions, the dimensions approach the wavelength of the electrons, introducing quantum properties. This way we can talk of two-dimensional gases, one-dimensional nanotubes, and even zero-dimensional quantum puts. Also the mean free path plays an important role in this. Several devices have already been proposed, among which are: single-electron transistors (SETs); resonant tunnelling diodes (RTDs); quantum dots and quantum cellular automata (QCA); buckey balls; nanotubes; and intramolecular nanoelectronic devices. There is still a long way to go to exploit more and more aspects of quantum-level behaviour to come to speci c forms of computing, and to manipulate atoms and molecules to provide desired properties. And there are many problems of course still to be solved. But the challenge is very high, and we are strongly motivated by nature around (and in) us. Nature seems to have solved the ‘problems’ and shows unbelievable processing power. Biological neural networks are unrivalled. But, we begin to learn from nature, and the time is now ripe for research on nanoelectronics up to system level. In this paper, we will try to give a general view (see also Figure 1), of nanoelectronics, from basic technology, via devices and circuits, up to systems. It discusses the challenges and threats of nanoelectronics in general, where individual electrons can be manipulated instead of currents. It shows a design view that tries to exploit the strong points of nanoelectronics, and at the same time to cope with, or even to exploit, the typical properties like inaccuracies and statistical behaviour, that inherently go hand in hand with decreasing dimensions. It further focuses on the interdependencies of the design choices made at dierent levels. Especially, the application of appropriate signal de nition, redundancy, and adaptivity will be elaborated. One speci c form of nanoelectronics, single electron tunnelling technology, with transistors in which the transport of charge takes place on individual electron level, is further explored. Copyright ? 2000 John Wiley & Sons, Ltd.

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2. CHALLENGES FOR RESEARCH IN NANOELECTRONICS The main challenge of nanoelectronics research is to exploit the quantum behaviour and to solve the problems that we face today: the inherent uncertainties and inaccuracies, the interconnection problem, and the problem of how to manage the enormous complexity in the design process.

2.1. Uncertainties and inaccuracies Exploiting quantum eects consequently means: working with devices showing statistic behaviour. This has a great impact on design of nanoelectronics that is mostly overlooked. It also means: extremely low-energy levels. And, if these quantum eects are to be used, we have to assure that the in uence of thermal energy, manifesting itself in thermal vibrations, so in thermal noise, has a negligible eect. This means for the moment: working at extremely low temperatures. The challenge for the future is: decreasing the sizes such that quantum energy levels, like the Coulomb energy of an electron, become larger than the thermal energy levels at room temperature. Low-energy levels also involves high sensitivity to noise which is at the same energy level: every movement of electrons or atoms can be felt; background charge is such a notorious noise source. Others are photons and penetrating EM elds. Also, the problem of crosstalk between signal lines should not be overlooked with these dimensions. Sizing goes hand in hand with increased relative inaccuracies, both for absolute and relative accuracy (matching), which introduces substantial inaccuracies in the electronic functions. This is structural, and we will have to cope with that. Further on, design approaches which address this point are discussed. Manufacturability is coupled to yield a serious problem. The challenge here lies in nding new approaches for the production processes. Self-organizing structures, self-repairing, self-assembling, etc., are interesting new ways.

2.2. The interconnection problem The basic part of the devices, there where the quantum eects take place are small. However, if we aim for huge integration levels, we also have to decrease the interconnection, which in itself is an enormous challenge. One aspect of this is technological, that will not be further addressed here. The other is architectural: if we really want to achieve nanoscale circuits, we will have to look for architectures that need a minimum amount of communication via a minimum amount of interconnections, that are mainly local connections. Also, the interconnection with the outside world, the I=O is still an unsolved problem.

2.3. Managing the enormous complexity in the design process In nanoelectronics, the design levels are not independent. We cannot split o the system level design from circuit design, and circuit design and device properties are also closely related, as will be made clear in this paper. The consequence of this is an enormous challenge: how can we (again) come to manageable design processes? Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 2. Nanoelectronics-design issues.

3. NANOELECTRONICS-DESIGN ISSUES From the foregoing discussion it has become clear that there are three classes of problems the designer of nanoelectronic circuits and systems has to cope with: the relative high level of uncertainties and inaccuracies, the interconnection problem, and the problem of managing the enormous complexity in the design process itself (see Figure 2). Here, we will give some openings how to cope with these problems. 3.1. Coping with uncertainty and inaccuracy The main part of the threats is caused by the uncertainties and inaccuracies, at dierent levels. So the general way to handle that is: reduce it or live with it and try to cope with it. Broadly speaking, the relation between output information and input information of any information-processing system, is the only thing that counts. Every processing system comprises signals, channels, and noise, and the (partial) freedom of the designer is in the de nition of the signals, which in one way or the other carries the information, and the de nition of the hardware that processes these signals. Suppose, like in our case, we want to investigate the feasibility of SET hardware for certain applications (system functions). In that case, the constant factors in the design process are the information to be processed, the technology to be used, and some characteristic properties of the noise sources from the environment. The free factors are: the choice of the signals and the choice of the circuits—and thereby the algorithms—in the SET-hardware. An optimal design means that these choices should be made optimal given the speci c properties of the hardware and the noise sources, the constant factors. Reduction of the uncertainties and inaccuracies looks trivial: rst we always try to make the hardware as accurate enough (as far as that does not increase the cost) and we always try to decrease the noise sources. In fact that is what is called improving technology. Coping with uncertainties and or inaccuracies is less trivial, but in our opinion it is certainly necessary in nanoelectronics. This chapter focuses on that point. We will discuss here three methods: the choice of the optimal signal domain(s) where the information is mapped to, the introduction and application of redundancy, and the introduction and application of adaptivity. 3.1.1. Choosing the optimal signal waveform and the optimal signal domain. The information to be processed is translated in two steps into an electrical signal: rst it is coded in a dimensionless signal, a dependent function versus an independent variable; second this Copyright ? 2000 John Wiley & Sons, Ltd.

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dimensionless signal is given a physical carrier (voltage, current, magnetic ux, number of electrons), resulting in the electrical signal, with values varying in time, that is processed by the hardware. The hardware devices and circuits show strongly dierent properties for the various domains. Some hardware for instance works good in the current domain, some in voltage domain. Or, the properties in the value domain are bad and information can better be put in the time domain. And nally, a combination of these is possible. So, the rst design choice is the carrier domain. This choice also in uences the required biasing of the circuit. Having decided which domain is optimal, the next design issue is how to code the information in an optimal way in the signal. Here we can, e.g. think of all kind of modulation techniques. An example: if the instantaneous value of the output of a SET transistor shows large variations due to background noise, but the amplitude is rather independent of that noise, one might consider putting the information in the amplitude rather than in the instantaneous value. Alternatively, the information could be coded in the number of spikes in a signal that comes out of a SET transistor, or in the periodicity of the spikes, etc. As in nanoelectronics the in uence of the imperfections of the hardware is substantial, a good choice deserves considerable attention and plays an important role in the design process and the choice of circuits to be built. 3.1.2. Applying redundancy. Redundancy literally means: a surplus, an excess of means; sometimes expressed subjectively as super uous or wasted means. So ‘more than strictly seems necessary’. First of all, this can indeed be the case if irrelevant information is processed, which really means wasting; that should be avoided by proper ‘source coding’, so by proper de nition of the signal to be processed. Apart from that, we also can have the situation that relevant information is transported=processed in a redundant way, for instance several times in parallel or several times successively in time. In electronics we can translate this with: more signal contents and=or more hardware than is strictly required for the implementation of a given function, assuming ideal hardware. At rst sight, this also looks a waste of means. However, hardware, including its environment, is never ideal; therefore, redundant hardware is not synonymous with wasted hardware, assuming that it is used in a correct way. On the contrary, it can be applied deliberately and with favour to provide the necessary margin to absorb the errors caused by the imperfections of a physical implementation. We have argued earlier that the designer has the freedom to de ne both signals and hardware, so in principle, redundancy can be applied to both. We also argued that the designer should do this optimally, given the properties of the type of hardware, given the information to be processed, and given the noise from the environment. It is, therefore, of utmost importance to gain insight in what kind of redundancies can be distinguished and how they can be applied, and, on the other hand, to gain insight in the speci c properties of the technology. Here, we will treat the rst point in further detail, as this is still a general issue that can be applied for all kinds of nanoelectronics technologies. Later on, we will look speci cally to SET technology, considering the speci c properties of this technology and the consequences for the design of circuits. 3.1.3. Signal and hardware redundancy. As said above, the designer has freedom in choosing the signals and the hardware. Correspondingly, we can distinguish between two kind of redundancies: signal redundancy and hardware redundancy. Signal redundancy can be explained as follows. After having decided in which electrical domain the processing will take place, Copyright ? 2000 John Wiley & Sons, Ltd.

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the information is mapped on an electrical signal in such a way that there is information redundancy in the signal. This can then be used to absorb the ‘errors’ caused by various kinds of noise and system transfer inaccuracies and uncertainties. That means that there is more contents (‘information’) in the signal than strictly necessary in case of ideal hardware, considering the amount of input information that must be processed. Digital examples are well known, as source coding; the signal is a sequence of discrete-level words, where the number of input information bits is less than the number of bits in the signal. Analog signals too can possess redundancy: the signal, in time and=or in signal value, carries more information than we deliberately put in it, and that extra information will also be processed. In both examples, we have some margin, some surplus, in the signal that grants it extra robustness in the physical implementation, where noise and system-transfer errors are introduced. Depending on the signal domain(s) chosen, the redundancy can be applied in the time or in the value-domain (voltage, current, etc.), or in both. The number of possibilities is, in principle, countless. An example: spreading the information in the time domain followed by processing and subsequently averaging, to obtain a result with more reliability. This can be done continuously or only for discrete events. Another example: discrete information might be coded in the continuous-carrier domain and subsequently processed with a higher resolution than strictly required for the used discretization, enabling signal restoration with a quantizer at the end (a general redundancy used in digital hardware). Instead of coding the information in a single signal, coding into several signals can also be applied (each of them to be represented in the physical system by a separate electrical signal). In case if less information is coded in a signal the redundancy in that signal will increase. Hardware (and algorithmic) redundancy is the second type of redundancy. The physical implementation is now given a surplus of means to make it function more robust in the presence of physical errors caused by noise signals from the environment and imperfections in the hardware. As a result, the functioning of the system will be less vulnerable to inaccuracies in the hardware, so it has an in-built hardware redundancy. This way of introducing redundancy can result in a surplus of hardware and signals, or a surplus in voltage or current range. The surplus of hardware manifests itself in an algorithmic surplus; algorithm and hardware are just dierent abstraction views. Note that at higher abstraction levels the redundancy might be invisible in the system function itself, and only become manifest in its performance. A simple and well-known example of hardware redundancy is used, for instance, in computer systems in critical situations, as like in a space shuttle or nuclear power station: several computers do the same job; the output given by the majority is considered the right one. Another method is averaging the output of several equal paths. Both are simple forms of hardware parallelism. An alternative method is using in the same hardware many times than ‘strictly necessary’, and combining the results. More complex examples with dierent paths are found in, e.g. fuzzy logic and neural networks, like ‘cooperative processing’ and a ‘winner takes all’ processing. Finally, an 8-bit AD conversion function can be implemented as an 8-bit ash AD convertor or as a two-step 4-bit ash approach; the dierence in algorithm and in vulnerability to hardware imperfections however is clear. As the examples already show, hardware redundancy can be applied at various levels of the design: at device level, at basic circuit level, and at higher system levels. In case of restricted operation ranges, however, as in SET transistor circuits, it seems necessary to apply redundancy already at device or basic circuit level. Copyright ? 2000 John Wiley & Sons, Ltd.

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Hardware redundancy might ask for dierent signals for the various channels, and therefore, for coding the input information in a set of dierent signals. However, this is not necessarily the case; the various channels might also use the same signal. Extra signals on the other hand, require extra hardware or hardware operating at higher speed. It is thus clear that there is a relation between signal and hardware redundancy: in both cases we are dealing with redundant processing in an imperfect physical system. 3.1.4. Applying adaptivity. The third way to approach the problem of imperfect hardware is to make your system adapt itself to the desired function, thereby tuning hardware such that the eects of the imperfections are cancelled. Seen from a high-level view, this approach makes use of feedback, which is based on the availability of an accurate reference. This approach, complementary to the approach of introducing redundancy, can be a very fruitful one for nanoelectronics. That is the reason why we have given much attention to neural circuits, as a speci c implementation of it, from the beginning of our work on nanoelectronics. We will discuss this in more detail further on. In principle, this way of tuning can be applied at all levels of the system, so from basic circuit level up to high system level. However, a general remark has to be made here: tuning can only be eective as long as the tuning parameters stay within their maximum operating range. So, the larger the relative noise and errors, the lower the level where adaptivity must be applied. For nanoelectronics, with relatively low signal levels, and consequently high noise and error levels, this means that the tuning should already be applied rather locally. 3.2. Coping with the interconnection problem As said before, the interconnection problem is also a severe problem that can be tackled in the technology domain, but also via architectural design. Technology oers several interconnection methods (metal interconnects, substrate connections, etc.) and improvements in technology can lead to, e.g. smaller lines and less capacitance to substrate. The architecture gives the twodimensional topology of the total circuit and thus de nes among others if the connections are local or global, if they are crossing each other, and the total number of connections. The less global connections and the less crossings, the faster the circuit can operate. A good architecture in that sense is, for instance, a so-called nearest-neighbour architecture, with cells, e.g. in a two-dimensional regular array, or hexagonal honeycomb array, communicating only with their four, resp. six nearest-neighbours; three-dimensional arrays are even better but are dicult, if not impossible, to realize in an IC. The algorithm performed by the cell array can also be chosen such that the communication between the cells is minimum in the sense of communication speed. In principle, almost any architecture can be chosen by the designer, but he has to translate his function into an appropriate algorithm that can easily be mapped on the desired architecture. In fact, regularity in an algorithm maps most easily on the regularity of the architecture, and regular functions on their turn map easily on regular algorithms. So the speci c function that must be performed also has in uence on the nal communication. But even in the de nition of the function the designer normally has in uence: the highlevel system behaviour can be implemented via various combinations of (sub) functions, e.g. a classi cation function that can be performed by dierent types of neural networks. The approach followed here is a bottom–up approach to de ne the architecture, and a top–down approach to map the function via the algorithm on the architecture. In the bottom–up phase, Copyright ? 2000 John Wiley & Sons, Ltd.

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de ning the architecture, the typical primitive cell that will be used is of great importance. For SET-circuit cells, for instance, the fan-out and the fan-in are limited, thereby limiting the number of connections that can be made. The reason for the limited fan in=out is the coupling in the SET cells between in and output and the coupling with the capacitive island. So, fan-in and fan-out can be important properties on the basis of which a speci c primitive circuit is chosen. Finally, the I=O to the outside world also poses a problem due to the capacitive load and the thermal connection with the environment. 3.3. Coping with the design-complexity problem The complexity of some type of nanocircuits, e.g. the SET circuits, is very high due to the nonlinear behaviour: electron transports take place only if certain energy conditions are ful lled and even then the occurrence of such an event follows statistical rules. Between the tunnel events, the state variables are linearly coupled. As the charge on each island corresponds to a state variable, the dimensionality of the circuit is very high. Interpretation of the behaviour of a simple SET circuit, like the three-island ‘inverter’ circuit, therefore already becomes very dicult. A further problem with nanoelectronic circuits is that the levels in the design cannot be considered as independent. For instance, two cells interact with each other via their interconnection. In conventional electronics this is prevented by buering, but in nanoelectronics we try to prevent using buers, as it would counteract high density and the low power we strive at. Also within cells there is often no full decoupling between in and output. In a SET transistor the drain is still coupled with gate and source. Also the presence or absence of reciprocity plays a role. Structuring the design problem, however, is essential for reducing the design problem. It will be a challenge to nd a new and ecient classi cation, a new division into devices, subcircuits, etc. and to de ne dierent models with dierent abstraction levels that are simple but yet accurate enough to be useful for design. Physical models, taking into account the statistical behaviour are accurate but too much time consuming to be useful for analysis of larger circuits, let alone to be of help in designing circuits. Research is going on in this eld. The design problem, discussed in the sequel, is structured in the following way. We rst consider SET-devices, that are: (1) the single-tunnelling junction and (2) the single SET island (both depicted in Figure 3). Using a ‘more-or-less’ classical, or semi-quantum mechanical formulation behaviour of these device is described in the so-called orthodox theory of singleelectronics. Electrical characterization of these devices can be obtained by biasing the devices. Biasing is here de ned as placing the device in such a circuit that voltages over and the currents towards the tunnel junction are speci ed in a precise manner for obtaining a speci c transfer function. Note that the biasing is not limited to small-signal behaviour; in case of the SET devices we could also use the complete signal range. Second, we discuss SETcircuit primitives. These circuit primitives consist of the single SET island device connected to a conventional circuit element, like a capacitance or resistance. The circuit element is connected to the island and modi es the charge on the island. The dierent circuit primitives have qualitatively dierent transfer functions. Then, we discuss some simple SET circuits. The circuits consist of various circuit primitives. We will neglect higher order eects such as co-tunnelling. Finally, we will consider some system aspects. Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 3. Basic SET devices: (a) single-tunnel junction and (b) combination of devices creating an single island.

Figure 4. Equivalent models i the voltage over the tunnel junction is below the threshold voltage and the environment has a high impedance.

4. SET DEVICES The operation of a single-electron tunnelling (SET) device is based on the quantum–mechanical tunnelling phenomena. In such a structure electrons travelling from source to drain encounter a suciently thin potential barrier through which they can tunnel, if the energy during tunnelling is lower than the energy before tunnelling. At very low temperatures, this energy condition gives rise to a charge quantization. SETs may be produced in a number of dierent ways, the most common are metal–insulator–metal junctions or semiconducting quantum dots. Here, we focus on metallic structures. We discuss devices as being the basic building blocks to construct circuit primitives. The device responsible for the tunnelling phenomena is the single tunnel junction (Figure 3(a)). Another device is an island, to which or from which an electron can tunnel. An island is created by combining junctions and=or capacitors. Depending on the energy, an electron can remain on the island and as such create a new barrier. In Figure 3(b) a single-island created by two tunnel junctions is depicted. Other combinations of devices can create an island. For example, a tunnel junction in series with a capacitor creates an island, a structure generally known as ‘electron box’. Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 5. Electrical models: (a) before tunnel event; (b) during tunnelling.

Averin and Likharev [1,2] rst described what is known as the orthodox theory of ‘singleelectronics’: the transport of electrons in an arbitrary single-electron circuit consisting of (metallic) tunnel junctions, capacitors, and ideal voltage sources, as a sequence of jumps of single electrons. For any given charge state of the system one can calculate the tunnel rates for all junctions. The exact moment the tunnelling will occur in a matter of chance with probabilities determined by the corresponding rates. At which junction tunnelling will occur depending on the charges at the junctions. In case of a single junction in a high impedance environment, energy can be lowered during tunnelling if and only if locally the charge in the junction capacitance is greater than e=2; the energy during tunnelling should be smaller than before tunnelling (see also Figure 5): q2 (q − e)2 ¡ 2Ct 2Ct e2 q2 q2 2eq − + ¡ 2Ct 2Ct 2Ct 2Ct −eq −e2 ¡ Ct 2Ct e q¿ 2

(1)

(2)

The orthodox theory makes the following assumptions: the tunnel process is assumed to be instantaneous, the charge redistribution after a tunnel event is also instantaneous, and ohmic resistances only much larger than the quantum resistance RK (≈ 26 K ) are considered. 4.1. Single-tunnel junction The tunnelling rate of an electron through the barrier is proportional to the voltage across the junction, u, if the voltage exceeds a certain threshold voltage, uth , across the barrier. Above the threshold voltage, the ratio between the voltage and the average current is called the tunnelling resistance Rt . In fact the tunnel resistance is not a ‘real’ resistance but a phenomenological quantity. If a single junction is coupled with a current source, a continuous stream of electrons will be fed to the junction, whereas, they will pass the junction discretely by the tunnelling of electrons. The requirement for tunnelling is an amount of energy to remove an electron, or Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 6. Coulomb blockade in a single-tunnel junction in high-impedance environment. Gt is well de ned for large values of u.

more precise a quasi particle, from the conductor (as we consider the system in a semi-classical way). This energy is called the Coulomb-charging energy EC : EC =

e2 2Ct

(3)

This corresponds to an energy level after tunnelling that is lower than the energy level before tunnelling, or to a minimum amount of voltage over the junction, called the threshold voltage, uth , that equals e=2Ct . As long as the threshold voltage is not reached the junction is blocked (see Figure 6). This is called the Coulomb blockade. In order to ensure that the Coulomb charging energy and not the thermal energy governs the transport of charge, a limit on the operating temperature has to be set. The tunnelling capacitance, Ct , must be small such that the Coulomb energy far exceeds the available energy for thermal uctuations (EC kB T ). At this moment practical values for Ct are in the order of 100 aF, thus imposing experiments to be done at a few tens of mK. It is generally assumed that future technology will improve these numbers. As an alternative, architectures, such as neural networks, that can cope with errors due to thermal uctuations should be considered. The amount of charge at a certain point in the circuit is well de ned (‘local case’) only if that point is well separated from the rest of the circuit. The time constant associated with the capacitance between that point and the environment, and the resistance over that capacitance caused by the environment, must, therefore be high enough. This leads to a minimum resistance, equal to the resistance quantum RK , of h=e2 , or 26 K . A voltage source directly coupled to the tunnel junction certainly does not ful l this requirement; the electrons passing the junctions are compensated instantaneously, and cannot be localized; this is also referred to as the ‘global case’. A current source (in combination with an appropriate junction) does ful ll the condition, but is dicult to realize. Extra junctions in series can do the job, if their junction resistances are high enough. Further increase of tunnel resistances only decreases the numbers of electrons and therefore, the signal energy. In terms of circuit design the highimpedance level, or otherwise said: high time constants, will have an immediate consequence for the maximal operation speed. The external impedance causes the voltage over the junction to be a function of the electron transport through the junction. The tunnel current is, therefore, a function of the environment Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 7. Equivalent electrical models for the single tunnel junction, u¿0.

of the junction, like the crossing point between a load line and a transistor characteristic determines the current in conventional circuits. Electrical equivalent models (see Figure 7) can be obtained by placing the junction in a circuit. If the resistance is small we are considering the global case and the necessary energy is delivered immediately. The energy uncertainty now strongly exceeds the Coulomb energy. Consequently, a tunnel current will ow at all values of the external voltage. If the resistance is much larger than the quantum resistance, RRK , and the external voltage much larger than the voltage over the junction, we are considering the local case in which a current source is feeding the junction and we can observe the Coulomb blockade. An ideal current source is obtained if R → ∞. 4.2. Single-island device By placing two tunnel junctions in series we obtain an island between ‘source’ and ‘drain’. In the orthodox theory, in the global case, the single-island device is analyzed by considering charges on the island. Following this theory [1–4] the charges on junction one, junction two, and on the island can be written as Q1 = C1 u1

(4)

Q2 = C2 u2

(5)

Qi = Q2 − Q1 = ne + Q0 ; Copyright ? 2000 John Wiley & Sons, Ltd.

n = n2 − n1

(6)

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respectively, where n is the net number of electrons on the island; n1 is the number of electrons that have tunnelled across junction one entering the island, n2 is the number of electrons that tunnelled across the second junction leaving the island. Q0 is the background charge (including initial charge on the island). In general, the background charge is a noninteger charge oset. If the background charge is assumed zero, the electrostatic energy stored in the double junction is E=

Q2 C1 C2 u2 + (ne)2 Q12 + 2 = 2C1 2C2 2CT

(7)

in which CT is the total capacitance. Tunnelling in the double junction structure is possible if the total free energy of the complete system decreases. For the threshold voltages across the tunnel junctions we obtain (1) = uth

e(1 + 2n) 2C2

and

(2) uth =

e(1 − 2n) 2C1

(8)

In general, if n = 0; tunnelling through the double junction will start as soon as the rst threshold voltage is reached. system = uth

e 2Cmax

(9)

If an electron enters the island via one junction, it is energetically favourable for another electron to tunnel through the second junction out of the central electrode. The electron will, thus, immediately exit the island, this is called space-correlated tunnelling of electrons. A note on background charges is necessary. The background charge Q0 can reduce or even eliminate the Coulomb blockade.

5. SET CIRCUIT PRIMITIVES The popularity of the SET single-island device is based on the fact that the charge on this island can be manipulated or controlled by an external conventional circuit component. In this way we obtain a circuit primitive that looks like a transistor. A common name for the circuit primitives described below is, therefore, SET transistor. According to the components used we will consider brie y the C-SET transistor, the R-SET transistor, and the variable C-SET transistor (see Figure 8). 5.1. C-SET transistor The capacitively coupled C-SET, the coupled capacitance is called the gate capacitance, is the best studied circuit primitive [2], and its periodical transfer function is often used as a description of a circuit building block. Again in the global case, the threshold voltages, u1 and u2 , can be calculated and are a function of voltage at the gate capacitance, the gate capacitance itself, and the capacitances of the tunnel junctions. To obtain a formula we realize that the additional capacitive bias induces an additional charge on the island Qi = ne + Q0 + Cg (ug − u2 ) Copyright ? 2000 John Wiley & Sons, Ltd.

(10)

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Figure 8. SET circuit primitives: (a) C-SET; (b) R-SET; (c) variable C-SET.

in which Cg is the additional gate capacitance, ug the voltage at the gate capacitance, and u2 the voltage over the junction to the referenc. Substituting the new charge in the formulas of the single-island device we immediately obtain u1 =

(C2 + Cg )ub − Cg ug − ne − Q0 CT

(11)

u2 =

C1 ub + Cg ug + ne + Q0 CT

(12)

in which ub is the voltage over the C-SET transistor and CT = C1 + C2 + Cg . The threshold voltages are (again taking Q0 = 0): (1) uth =

e(1 + 2n) + 2Cg ug 2(C2 + Cg )

(13)

(2) = uth

e(1 − 2n) − 2Cg ug 2C1

(14)

Using this orthodox theory well-known SET-simulators, such as SIMON or MOSES [3,5], can simulate the behaviour of this circuit primitive. If we assume the existence of an ideal current source to supply the tunnelling electrons, the voltage at the gate is the input and the voltage over the C-SET the output. The transfer function is periodic with period e=Cg and with amplitude e=CT , where CT is the total capacitance. The C-SET is very sensitive to the random background charges. 5.2. R-SET transistor A resistively coupled R-SET would immediately solve the background charge problem if the resistor is large enough (only a very large resistor will cause the island to be ‘isolated’), but technological problems to realize this resistance, in a relatively small area, in a technology suitable to make the SET single island are not yet solved at this moment. The transfer function will be dierent from that of the C-SET, especially, it will not be periodic. Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 9. RJ-circuit.

5.3. Variable C-SET transistor Recently, an island coupled to a variable capacitance has been suggested to provide a solution to the background charge problem in the C-SET when used in combination with signal redundancy [6]. Information in this case is stored in either the periodicity or the amplitude of the transfer function. The eect of background charges that appear as a shift in the transfer function can be dealt with by integrating the signal over time.

6. SET CIRCUITS The assumptions of the orthodox theory, especially the ideal voltage sources, ideal current sources, and the restrictions on the values of resistors in the circuit, makes the theory only of limited use for real circuit design. To use the basic devices for the design of circuit primitives we must consider, as we discussed in the section on the basic devices, the environment of the junction. The tunnel rate is a function of the energy and so is the average current through the junction. There are, however, two dierent energy dierences associated with the tunnelling process, namely qV (directly supplied by an external voltage source) and EC , the Coulomb energy. These two dierent cases were viewed as the global and local case of the single-tunnel junction coupled to an external circuit Now, the question arises which of the cases, if any, is correct when we consider real circuits. 6.1. RJ-circuits Quantum–mechanical calculations [7] show that a tunnel junction coupled to an ideal voltage source will always behave according to the global view since after the tunnel process the charge is reestablished immediately. This is not the case if the voltage source is attached to the junction with a very large resistor in series; then the behaviour will be like that of an ideal current source and will always behave according to the local view. For intermediate values of resistances there is hardly any good rule of thumb to give, the correct current–voltage characteristic has to be calculated for speci c environments. The necessary restrictions can be obtained by considering circuits in with a single junction is connected to a resistor (see Figure 9). The total current through the junction is given by the transported charge e times the dierence of the forward and backward tunnelling rates i(u) = e( (u) − (u)) Copyright ? 2000 John Wiley & Sons, Ltd.

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Tunnelling is a quantum–mechanical eect. The tunnelling rate, (u), is the number of tunnel events per second. The tunnelling rate for a single metal–insulator–metal tunnel junction can be derived assuming the following two assumptions: (1) the states with speci c energies on the two electrodes only mix very weakly, and (2) charge equilibrium is established before a tunnel event occurs. The rst assumption assures that the tunnelling rate can be calculated with the so-called Golden Rule approximation, the second assumption assures that the states are equilibrium states. The time between two tunnelling events should, thus, be larger than the charge relaxation time. The golden rule i→f

=

2 |hf|Ht |ii|2 (Ei − Ef ) ~

(16)

states the transition rate between the initial state of the system |ii and the nal state of the system |fi. Ht describes the exchange of electrons via tunnelling and the  function enforces the conservation of energy in the tunnelling process. The tunnelling is non-dissipative. Using quantum–mechanical calculations [7] the tunnelling rate can be expressed as a function of the voltage u necessary to create an energy dierence eu between the two Fermi-levels of the metal electrodes Z +∞ E 1 P(eu − E) dE (17) (u) = 2 e Rt −∞ 1 − exp(−ÿE) In this equation ÿ = 1=kT , all constant terms are collected in the term: e2 Rt . Rt has the dimension of resistance, and is called ‘tunnelling resistance’. P(E) may be interpreted as the probability to emit the energy E to the external circuitry; for negative energies P(E) describes the absorption of energy by the tunnelling electron. For the calculation of the current (Equation (15)) the backward tunnelling rate can be obtained from the forward tunnelling rate (u) = (−u)

(18)

Important, for the description of the current, is the function P(E) in Equation (17), the probability to absorb from, or to excite energy to the environment. For P(E) holds the socalled detailed balanced symmetry relation P(−E) = e−ÿeu P(E)

(19)

which means that the probability to excite energy to the environment compared to the probability to absorb energy from the environment is larger by the Boltzmann factor. Another consequence is that at zero temperature no energy can be absorbed from the environment. P(E) then vanishes for negative energies. Using properties of P(E), not mentioned explicitly here, one can obtain the equation for total current through the junction Z +∞ E 1 P(eu − E) (1 − e−ÿeu ) dE (20) i(u) = eRt 1 − exp( −ÿE) −∞ The average current as a function of an external voltage source in series with a resistor can be calculated [7] in some special cases (R¡RK ; RRK , and R = RK when T = 0 K). We will give the results in the rst two cases. Copyright ? 2000 John Wiley & Sons, Ltd.

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In case of a low impedance the global description leads to a correct description. The external voltage source keeps the voltage across the junction xed at any time. At a consequence we do not nd a Coulomb gap. The current will be proportional to the applied voltage. i(u) =

u Rt

(21)

In case of a very high impedance at very low temperature the local description leads to a correct description. The average current is determined by an ohmic characteristic with resistance Rt shifted in voltage by e=2Ct . i(u) =

(u − e=2Ct ) Rt

(22)

It is important to note that the value of the resistor has to be compared with the quantum resistance instead of the tunnel resistance, as one might expect. 6.2. Multiple-junction circuits Devices with n junction in series, creating n − 1 islands can be analysed by considering the charges on each island. In general, this is a rather elaborated job. Device simulators, based on the orthodox theory like SIMON [3] and MOSES [5], can simulate these devices as long as n is not too large. The simulators can be used to obtain stability diagrams that shows stable states between tunnel events. A circuit consisting of two islands is called an electron pump, if the islands are connected to suitable capacitors and are controlled in such a way that electrons are ‘pumped’ through the structure. The structure can be used as a very sensitive electrometer. Another very interesting circuit is the three island structure often called SET inverter, named by Tucker [4] who used this structure as an inverter (see Figure 10). However, the structure is much more ‘rich’ in terms of interesting and distinguishable functional behaviour. The functions that can also be obtained in this structure include [8]: NAND, NOR, XOR, Schmitt-trigger, or a stochastic signal generator. A thorough analysis of this structure with and without taking into account the presence of background charges is very important, but time consuming. 6.3. Neural circuits Although not all circuit design ins and outs are known yet, various research groups suggested neural network nodes based on SET circuit primitives and SET devices. We will brie y present some of those proposals. The rst circuit ideas date from the end of 1995. Goossens et al. [9] suggested a neural node consisting of a multiplication function, adding function, and activation function. Central in the design is the C-SET transistor in series with a current source (see Figure 11, lower part). A multiplication like function is obtained using this C-SET transistor coupled to two gates, representing the input and the weight. The adder is obtained by capacitive coupling, and the activation function by cascading two C-SET transistors. The power-consuming current source is replaced by another C-SET, obtaining a three-island structure, by Kirihara et al. [10] and Akazawa et al. [11], who used a three-island structure to design a neural node. The structure is depicted in Figure 11 the upper part without the dashed junction. Kihiraha et al. described a multiplier based on the inverter property of the structure to obtain an multiplicator. The weight is represented as a voltage at the drain of the Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 10. Three-island structure often called SET inverter.

three-island structure. They also describe a weight storage and in=decrementing device based on a charge pump. Akazawa et al. described a neuron suitable for implementing a Boltzmann machine neural network. They use the stochastic signal generation property of the three-island circuit to design the output of a stochastic neuron. The stochastic property is a result of the instable operating mode of the structure at a certain bias. The probability is controlled by the voltage at the input. Recently, Gerousis et al. [12] suggested a node for a cellular neural network based on the three-island structure extended with an extra junction (see Figure 11, upper part with dashed junction). The node switches non-linearly between two stable operating points. The extra junction at the output should provide a current proportional to the output voltage. 6.4. Device-imposed constraints for circuit and system design The nanodevices discussed earlier show certain speci c properties. Some of these can be used favourably, but some impose constraints for the circuits and systems that have to be designed with them. Consequently, this entails restrictions to the mapping. In this chapter, a number of constraints will be discussed shortly. 6.4.1. Directionality. The SET transistor is dierent from the normal MOS transistor. The output voltage at the drain in the SET transistor shows a strong in uence (feedback) on the electron transport, in contradiction with the conventional transistor. There the output is almost completely determined by the gate–source voltage and the output-voltage feedback is just a secondary eect. In the logic circuits built up with quantum-dots, as proposed in Reference [13], the circuits are in principle reciprocal: the device can be seen to operate both in forward Copyright ? 2000 John Wiley & Sons, Ltd.

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Figure 11. Proposed SET-based neural circuitry; (a) three-island based and (b) C-SET based.

as well as in backward direction. Therefore, extra measures have to ensure that the direction is xed. For instance, by forcing the input voltage to the input of the rst dot, the output of it will change, giving rise to a change at the input of the second quantum dot, etc; the total directional eect is that of a sequence of dominoes. 6.4.2. Fan-in and fan-out. In all electronic circuits the driving capability (‘fan-out’) is in principle limited, as the total load will in uence the behaviour of the circuit in a negative sense. Similarly, the number of devices coupled to the input (‘fan-in’) is limited. Due to the extremely small dimensions of nanodevices, the relative in uences of external devices and interconnection (impedance levels) on the behaviour of the nanodevices will, in general, be rather strong and the fan-in and fan-out correspondingly more limited. In the case of a SET Copyright ? 2000 John Wiley & Sons, Ltd.

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transistor, the number of inputs increases the capacitance seen by the island. This in uences the operation of the transistor, especially the maximum slope in its transfer characteristic, which is related to the maximum gain that can be achieved. A similar argument holds for the capacitance of long interconnection lines. The low fan-in, therefore, asks for short local interconnections and puts a constraint on the number of inputs of a SET transistor (e.g. just four) and consequently to the topologies that are allowed. The number of outputs is limited too, due to the feedback discussed above and due to the negative in uence of capacitive load on the bandwidth, especially with the high impedance levels we are dealing with in these types of networks. Both limited fan-in and fan-out ask for sparsely connected networks and make regular-array type of cellular networks the logical choice [14]. 6.4.3. Gain. The gain of SET-devices is rather limited, again due to the feedback eect, and to practical limits on capacitance ratios. The maximum slope in the (periodic) transfer characteristic from a given input to the output is equal to the capacitance of the speci c control gate divided by the total capacitance seen by the island (so the combined capacitance of all inputs). This means that functional gain, gain to improve SNR, and gain necessary for accurate feedback operation is dicult to realize, which restricts the freedoms for the designer. 6.4.4. Accuracy. A well-known problem with very small devices is the decrease in accuracy that accompanies the shrink in sizes. Finally, a function requires some accuracy. There are several ways to achieve this. One is the use of redundant hardware, as discussed earlier in this paper. Another, more conventional way, is to introduce feedback. However, the lack of available gain and the lack of accurate components for the feedback loop makes this method problematic to implement. On a higher level it can be done: a learning neural network in fact can obtain its accuracy via a global feedback with the learning vectors (e.g. images) as accurate references. An accurate network is not required then; the accuracy is obtained from externally applied vectors. 6.4.5. Integration with other devices. Combining nanodevices with MOSFETs, bipolar transistors, JFETs, etc., can be desired to add locally properties that the nanodevices miss, like gain, directionality and accuracy. However, this is troublesome for several reasons. First, the technology is normally not compatible. Second, as long as the nanocircuits require ultra-low temperatures, problems are encountered with the other devices. Third, the signal levels are not always compatible: the levels in nanocircuits normally are far lower.

7. SET SYSTEMS For building nanoelectronics systems it is essential to consider all levels of the design, and to decide where and how we should cope with the various speci c properties of the nanoelectronic circuits. Fuzzy logic is a good example of how fuzziness can be used instead of counteracted. Fuzzy logic accepts that information often is only available in a fuzzy way. Based on this recognition, it makes ecient use of the signal domain: only relevant information is coded in the signals. Based on this a complete new type of logic reasoning, called fuzzy logic, has Copyright ? 2000 John Wiley & Sons, Ltd.

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been built, comprising fuzzy algorithms with non-linear functions like maximum or minimum, and several kinds of redundancy via e.g. co-operative processing. Although, here the speci c coding and the speci c logic is based on the ‘fuzzy’ availability of data, it might also be applied in systems where originally correct data becomes fuzzy due to unpredictable errors, so in systems where the system parameters are fuzzy. So, to our opinion this is a good starting point for building nanoelectronic systems. Arti cial neural nets imitate the brain, which comprises an unlikely amount of very small and basically inaccurate neurons, co-operating in a non-linear way, together performing rather accurately an incredible amount of unbelievably complex functions. Obviously, nature has found a very ecient way of exploiting hardware, diering strongly from the way computers operate. Biology, therefore, inspires us to follow this unconventional approach. Several properties make sense to consider for nanoelectronics. The architecture, comprising clustered and locally more or less regularly arrays. The primitive function executed by a neuron, performing analog and inaccurate non-linear processing. The information coding, and the redundancy is applied both in signal and hardware. Self-learning and self-organization, providing accuracy and reliability despite inaccurate components.

8. CONCLUSIONS Nanoelectronics will evolve the coming years. Quantum-device sizes are very small, and they have the potency to operate with very low power, as only a few electrons can be enough to represent the information. In addition, quantum properties that appear in nanoscale devices in principle represent an increase in signal-processing power that might be utilized favorably. It has been argued that, for nanoelectronic systems to become feasible, it will be necessary to follow unconventional design approaches. An overall design philosophy for circuit and system design has been introduced to utilize the unconventional quantum properties of the devices and to cope with the supplementary problems. These are mainly: the uncertainties and inaccuracies, due to the small sizes and the very low signal levels; the interconnection problems; and the design complexity. As main ingredients of the design philosophy, we proposed mutually complementary measures: a coding of information into appropriate waveforms, the use of redundancy at all levels of the system design; and the introduction of adaptivity. Appropriate waveforms are those waveforms that are optimal with respect to the speci c properties of the hardware. Redundancy can be applied both in signals and in hardware to increase the robustness to the relatively high noise levels and to inaccuracies in the hardware. Adaptivity is a way to introduce accuracy by means of feedback. These measures can be applied at all levels of the system. It is explained that fuzzy logic and neural network concepts combine several of these measures and are therefore recommended. Quantum-devices have to be supplemented with conventional devices, such as capacitors, resistors, or diodes, to obtain useful circuit that, combined in a proper way, provide the desired functionality. We showed that the commonly used orthodox theory of single-electron tunnelling is not powerful enough to describe the behaviour of the circuits; this depends on the impedance levels, as locality is only preserved under high isolation conditions. To investigate the viability of nanoelectronic systems, neural-network nodes, implemented with single-electron tunnelling technology have been explored. Equivalent electrical models Copyright ? 2000 John Wiley & Sons, Ltd.

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are presented to describe the circuits. It makes sense to investigate other circuit primitives than the common C-SET, as they might deal better with the background-charge problem. ACKNOWLEDGEMENTS

We gratefully acknowledge the nancial support of the European Mel-ari=NID ‘ANSWERS’ project, and the Delft Inter-faculty Research Center ‘Novel Computational Structures based on Quantum Devices’. REFERENCES 1. Averin DV, Likharev KK. In Mesoscopic Phenomena in Solids, Altshuler BL, Lee PA, Webb RA (eds). Elsevier: Amsterdam, 1991; 173. 2. Likharev KK. IBM Journal of Research and Development 1988; 144–158. 3. Wasshuber C, Kosina H, Selberherr S. SIMON—a simulator for single-electron tunnel devices and circuits. IEEE Trans Computer Aided Design of Integrated Circuits and Systems 1997; 16:937–944. 4. Tucker JR. Complementary digital logic based on the Coulomb blockade. Journal of Applied Physics 1992; 72:4399–4413. 5. Chen RH, Korotkov AN, Likharev KK. Single-electron transistor logic. Applied Physics Letters 1996; 1954– 1956. 6. Klunder RH, Hoekstra J, van Roermund AHM. Variable capacitively coupled single-electron tunnelling transistor. In Innovative Circuits and Systems for Nano Electronics, Schmitt-Landsiedel D (ed.) 1998; B41–B49. 7. Ingold G, Nazarov YV. Charge Tunneling rates in ultrasmall junctions, In Single Charge Tunnelling, Grabert H, Devoret MH (eds). NATO ASI series 1992; 21–108. 8. Akazawa M, Amemiya Y. Elicting the potential functions of single-electron circuits. IEICE Transactions on Electron 1997; E80-C:849–858. 9. Goossens MJ, Verhoeven CJM, van Roermund AHM. Concepts for ultra-low-power and very-high-density singleelectron neural networks. NOLTA’95 1995; 7B–7. 10. Kirihara M, Taniguchi K. A single neuron device. Japan Journal of Applied Physics 1997; 36:4172–4175. 11. Akazawa M, Amemiya Y. Boltzmann machine neuron circuit using single-electron tunnelling. Applied Physics Letters 1997; 70:670–672. 12. Gerousis C, Goodnick SM, Wang X, Porod W, Csurgay AI, Toth G, Lent CS. Modeling nanoelectronic CNN cells: CMOS, SETs and QCAs. ECCTD’99 1999; 835–838. 13. Tougaw PD, Lent CS, Porod W. Journal of Applied Physics 1993; 74:3558. 14. Goossens MJ. Analog neural networks in single-electron tunnelling technology, PhD thesis, 1998. University of Technology Delft.

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