Digitally enhanced analog circuits: System aspects

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Digitally Enhanced Analog Circuits: System Aspects Boris Murmann

Christian Vogel

Heinz Koeppl

Stanford University Department of Electrical Engineering Stanford, CA, USA [email protected]

Graz University of Technology Signal Processing and Speech Communication Laboratory Graz, Austria [email protected]

EPFL School of Communication and Computer Sciences Lausanne, Switzerland [email protected]

Abstract— An overview of digital enhancement techniques for analog circuits is presented. Recent research suggests that the high density and low energy of digital circuits can be leveraged to enable a new generation of interface electronics that is based on minimal precision, low complexity analog blocks. Today, examples of enhancement schemes can be found in diverse applications and include nonlinearity compensation of ADCs, predistortion of power amplifiers and mismatch calibration in radio receivers. Since it is often difficult to identify commonalities among these different, but conceptually related schemes, this tutorial paper aims to provide a unified and system-oriented perspective of the field.



The continuing downscaling of feature sizes in integrated circuits has enabled the realization of ever more complex electronic devices. In addition to purely digital functions such as microprocessors, we have seen an extraordinary growth in wireless and wireline communications. Since most communication channels are “analog” in nature, such applications are typically partitioned into an analog front-end and a digital back-end processing unit. Since the analog and digital system elements usually obey different limits and technology trends, proper partitioning is an important challenge. This is particularly so in cases where the analog interface constitutes the system’s bottleneck. In recent years, we have seen growing efforts to push the digital processing functions “closer to the antenna,” aiming for a reduction in the complexity of performance-limiting analog elements. In addition to minimizing analog content, there has been a clear trend toward digitally enhanced analog design, aiming to leverage digital correction and calibration techniques to improve the analog performance. Historically, digital enhancements to analog circuits have evolved at the block level of specific functions, as for example linearity calibration in A/D converters. In this classical scenario, digital correction is more or less applied as an afterthought and without considering the overall system. With the growing complexity in today’s applications, there exists an opportunity to explore a more holistic view of digital

correction; one that looks at block interplay, and specific system and signal attributes. Figure 1 shows a general block diagram of a digitally enhanced electronic system in which additional digital resources are allocated either to assist individual blocks or to facilitate the system-wide interaction of previously isolated blocks. Digital Enhancement Signal Conditioning Analog Media and Transducers

A/D Digital Signal Processing

CLK Signal Conditioning


Digital Enhancement

Figure 1. Block diagram of a generic electronic system with digital enhancement.

The purpose of this paper is to provide an overview of the state-of-the-art in digital enhancement techniques, highlighting challenges and opportunities from a system-level perspective. We begin our discussion by outlining the tradeoffs and scaling trends of analog and digital circuits in Section II. Section III identifies the different hierarchical levels at which digital enhancement can be used. Section IV provides additional examples and insight into specific applications. II.


A. Digital Logic Over the past decades, integrated circuit technology has been scaled according to Moore’s law, aiming to double the number of transistors per die every two years. A direct result of this scaling trajectory has been the tremendous improvement in the performance of digital circuits. For instance, lead microprocessors have shown a doubling in their computing power roughly every 15 months. Alongside with these improvements in speed comes a significant reduction in

energy per logic operation. As explained in [1] the typical 0.7x scaling of features along with aggressive reductions in supply voltage have led to a 65% reduction in energy per logic transition for each technology generation. The survey data presented in [2] suggests that a 2-input NAND gate dissipates roughly 1.3pJ per logic operation in a 0.5-µm CMOS process. The same gate dissipates only 4.5fJ in a more recent 90-nm process; this amounts to a ~300x improvement in only 10 years. B. Analog Circuits Unlike their digital counterparts, most analog circuits are constrained by electronic noise, linearity and matching requirements; factors that at best conditionally benefit from technology scaling. Generally, the achievable performance and power dissipation of an analog circuit is a complex function of specifications, technology, implementation and architecture. However, several basic trends can be identified as a function of the “signal fidelity” that an analog circuit must deliver. Circuits that operate at low resolutions, e.g., 6-bit A/D converters, are usually not impaired by thermal noise. A significant limitation in this class of circuits stems from matching. With appropriate mismatch calibration techniques in place, low resolution circuits do reasonably well at extracting a scaling benefit that is close to that of digital logic. In recent high-speed flash ADCs we have seen conversion rates on the order of 5GS/s, approaching speeds seen in lead microprocessors. At the high end of signal fidelity, say at 16-bit resolution for audio, thermal noise is the main culprit. Much of the energy dissipated in such analog circuits is spent driving large capacitances and/or low resistances that facilitate low noise operation. Additional constraints arise in such circuits due to the need for high linearity. For instance, using large gain in analog feedback loops amounts to additional power that is spent to achieve highly linear operation. Between the two outlined extremes of “low” and “high” fidelity circuits exists a space that obeys a complex mix of the described tradeoffs. Due to the large variety in analog circuits and the complexity of the involved dependencies, it is hard to identify clear and universal trends in performance. In [3] it was suggested that the throughput of A/D converters, measured through their speed-resolution product, doubles every 5 years; an improvement rate much slower than that of microprocessors. In recent years, analog speed improvements have become hard to identify. This is primarily so for two reasons. First, a large fraction of analog circuits is designed for “fixed bandwidth” standards, i.e. no attempt is made to optimize the circuit speed beyond a given spec. Second, power dissipation has become a hard limiter for realizable throughput levels; the achievable speed of a circuit may be larger than the power-limited bound. Especially since power dissipation has become one of the most dominant system limitations, it is more interesting to compare the two domains – analog versus digital – in terms of their relative energy per operation. Such a comparison was carried out in [2] for typical A/D converter realizations and

logic gates (see Table 1). These data suggest that at low signal fidelity, e.g. SNDR=30dB, a single A/D conversion consumes as much energy as toggling 4,679 logic gates. On the other hand, at 90dB SNDR, more than two million logic gates would need to transition to consume the energy of an A/D conversion. The data of [2] also states a progress rate for the energy used in A/D converters. According to published results from ISSCC 1997-2007, the average energy across all resolutions has decreased by a factor of 35. Relative to the previously stated 300x improvement in logic gates, this means that the relative “cost” of digital computation has reduced roughly by a factor of ten over the past decade. TABLE I. ENERGY/CONVERSION IN A/D CONVERTERS (EADC) RELATIVE TO LOGIC GATE ENERGY (ENAND=4.5FJ) IN 90NM CMOS. SNDR [dB]




21 nJ



168 nJ



1.35 µJ



10.8 µJ


While the numbers in Table 1 present no hard bounds or fundamental limits, they provide a general feel for how many logic gates can be used today for digital enhancement. For instance, in a system with fairly low SNR, it is unlikely that tens of thousand of gates can be used for digital enhancement without exceeding reasonable energy or power limits. A large number of gates may be affordable only if the involved gates operate at a low activity factor or if they can be shared within the system. Conversely, in very high fidelity circuits, each analog operation is very energy consuming and even a large amount of digital processing can typically be accommodated in the overall power budget. A well-known example that reflects this case is a high-resolution sigma-delta A/D converter. Even in fairly old technologies, it was reasonable to justify high gate counts in the converter’s decimation filter; simply because the overall energy per sample in the analog portion of the circuit is very high. In light of the above analysis it becomes clear that a key task in energy and power-limited mixed-signal systems is the careful allocation of signal processing in either domain. A widely accepted strategy in circuits with moderate to high signal fidelity (e.g., SNDR>50dB) is to either minimize analog content or to relax the precision requirements on analog functions, e.g., using digital enhancements. The resulting approaches can be classified as discussed in the following section. III.


As outlined above, optimum usage and synergistic interplay of analog and digital functions is a must for meeting the requirements of next generation devices. Instead of

designing a collection of individual blocks, future devices are likely to employ a holistic approach in which the functionality of a traditionally isolated block is provided through the support of other blocks and superposed protocols [4]. Holistic Enhancement Approach System Level Enhancement

Block Level Enhancement

Digital signal processing

Block Level Enhancement

Block Level Enhancement

Mixed signal processing

Analog signal processing

Efficient digital enhancement of analog circuits is only possible if their analog behavior is sufficiently well characterized. We have to identify an appropriate model as well as its corresponding parameters. The model is often based on a priori knowledge about the system. The key parameters that influence the system and their time behavior are typical examples. However, in principle, we can also derive and modify the model itself adaptively, which is the central topic of adaptive control theory. The parameters of the model are tuned during the fabrication of the chip or during its operation. Since fabrication-based calibration methods are limited, we have to employ algorithms that adapt to a non-stationary environment during operation. However, specifying and implementing robust adaptation algorithms that guarantee a certain performance levels is a challenging task. Furthermore, the design of, e.g., an A/D converter cannot be separated from the system design anymore, since the calibration algorithms rely on particular properties of the system. Therefore, a holistic approach to system and block design becomes essential.

Figure 2. Holistic approach to digital enhancement of mixed-signal and analog circuits.

As illustrated in Figure 2, a typical electronic system can be divided into analog, digital and mixed-signal blocks. The mixed-signal blocks are essentially the data converter in the system, where due to additional digital post- or pre-processing the boundaries between analog signal processing and digital signal processing become blurred. Because of the increasing analog/digital performance gap and the flexibility of digital circuits, performance supporting digital circuits will become an intrinsic part of mixed-signal and analog circuits. Digital enhancements of analog and mixed signal functions can be classified into system-level and block-level schemes. Block level enhancement refers to the improvement of the overall performance of a particular block in the system, e.g., the A/D converter. System level enhancement uses system knowledge to improve or simplify block level enhancement tasks. Typical examples are crest factor optimization in multicarrier systems [5], I/Q channel calibration in communication systems, and ADC calibration in OFDM systems [6]. Digital enhancement at the block level can be loosely categorized into digitally enhanced, digitally guided, and digitally emulated circuits. Digitally enhanced circuits use digital signal processing to overcome shortcomings of the analog design and intentionally exploit the advantages of a minimalistic analog design [7]. Therefore, the digital signal processing is not necessary for the functionality of the overall block but significantly enhances its performance. Digital calibration of A/D converters is an example [8-10]. Digital guided circuits need the digital signal processing as an intrinsic part for the functionality of the overall system. Deltasigma converters are examples of digital guided devices. The final group is the digital emulated analog circuits. Here, the digital signal processing is mainly responsible for the functionality. Digitally switched power amplifiers and alldigital PLLs can be assigned to this category [11].



A. Digitally Enhanced A/D Converter A specific example of a system-synergistic enhancement concept was reported in [6]. The scheme of Figure 3 uses the pilot tones of an OFDM system to measure and cancel offsets in a time-interleaved ADC array. With a proper ratio between the number of channels and FFT size, the error signal due to offsets is spread across the entire FFT spectrum. Since the pilot bins of the FFT are modulated with a known pseudorandom sequence, errors due to the offsets can be extracted via a correlation-based measurement. The measured errors feed into a gradient descend algorithm, which applies offset corrections until optimum performance is achieved. ADC7

+ -

baseband processor pilot estim.




+ pilots




calibration logic +


pilot errors

ADC1 offset adjustments

Figure 3. Block diagram of a digitally enhanced, time-interleaved A/D converter using a system-synergistic approach. Specific system resources (FFT block, pilot tones) are used to facilitate background calibration.

An advantage of this holistic enhancement is that costly resources, such as the system’s FFT block, are efficiently reused for background calibration. While the specific goal of [6] was to calibrate offsets, many other possibilities exist for “training” the ADC and other system hardware using pilot tones. Furthermore, future systems could incorporate special calibration signals that are different from existing pilot tones and show superior properties for the purpose of hardware selfcalibration.

B. Digitally Enhanced Power Amplifiers Due to their pervasiveness in today’s RF systems, power amplifiers represent a very promising field of application for digital enhancement techniques. In particular, a digital improvement of their linearity can yield a large gain in power efficiency of a system. Digital compensation of nonlinear distortions in power amplifiers can be realized by serial as well as parallel structures such as predistorters and cancellers, respectively. A typical example of digital predistortion in conjunction with crest factor reduction [12] is depicted in Figure 4.

analog and mixed-signal circuits is a multi-disciplinary research field with many open questions and opportunities. REFERENCES [1] [2] [3] [4] [5] [6] [7]

Figure 4. Block diagram of a digitally enhanced power amplifier with crest factor reduction and predistortion. The predistorter can be adjusted adaptively through the sensing feedback path.

Conceptually, predistortion is a block level enhancement approach, whereas crest factor reduction can be assigned to system level enhancement schemes. Mathematical models for the nonlinear distortions of power amplifiers range from computationally cheap memoryless nonlinearities to doubly truncated Volterra series [13] that are computationally very demanding. Models of intermediate complexity include variants of Hammerstein models [14] (memory polynomials), Wiener models [15] and LNL (linear-nonlinear-linear) models [16]. The exact inversion of models for the purpose of predistortion is often not feasible for implementation and various structures that give approximate inverses have been proposed [17, 18]. However, if the current trends in analog and digital circuits continue, more complex and therefore more efficient predistortion schemes will become feasible. Due to the dependence of the nonlinear characteristics of a power amplifier on its operating conditions, such as temperature, most linearization schemes incorporate a feedback path that is used to adjust the model parameters during operation in order to meet a predetermined distortion metric [19]. This metric normally applies to the signal level as for block level enhancement schemes but can also be based on the symbol level as for system level enhancement schemes [20]. V.

[8] [9] [10] [11]

[12] [13] [14]

[15] [16]



In order to deploy digital enhancement of analog circuits successfully, knowledge from circuit design, signal processing, and information theory must be combined. Analog, RF and digital circuit designers must work together to model, optimize and implement digitally enhanced circuits. Knowledge in signal processing and system theory is essential for developing and applying advanced algorithms. Applying information theoretical considerations – as it has been done for communications channels – can help in finding the ultimate limits on digital enhancement. Thus, digital enhancement of

[18] [19]


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