Embedded Mechanical Stress Sensors for Advanced Process Control Moustafa Kasbari1, Romain Delamare1, Sylvain Blayac1, Christian Rivero3, Ola Bostrom 3, Roland Fortunier2 1
Ecole des Mines de Saint-Etienne, Centre de Microélectronique de Provence, 13541 Gardanne, France 2 Ecole des Mines de Saint-Etienne, SMS, 158 cours Fauriel, F-42023 ST-Etienne cedex 02, France 3 STMicroelectronics, Zone Industrielle de Rousset, 13106 Rousset cedex, France E-mail: [email protected]
Keywords: Advanced Process Control, Polysilicon, Sensor, Mechanical stress, Piezoresistive effect.
curvature measurement does not allow measuring the stress because of the both wafer sides deposition of this material. The second reason is that monitoring of strain induced by polysilicon takes a particular importance as strained silicon devices come into production. The aim of this paper is thus to report the results obtained with the new test structure and demonstrate its relevance in an APC scheme. Section II introduces the principles of this piezoresistive sensor and section III details the structure design. Section IV details the results obtained on an individual sensor as well on full wafer mapping. We identify some variability in the response of the structures throughout the wafer. The aim of the discussion in section V is therefore to assess the sensitivity of the structure, analyze the origins of variability and demonstrate the usefulness of the sensor.
II. GUIDELINES FOR SENSOR DESIGN
It is well known that mechanical stress is developed during manufacturing process of CMOS microelectronic circuits . This residual stress plays an important role in the devices reliability and often generates fabrication yield loss . This phenomenon becomes of increasing importance as the complexity (integration density, number of metal levels, thermal cycling, packaging effects…) is growing. It is therefore of major importance to put parameters in correlation with mechanical stress under systematic control along process flow, as close as real time as possible. This should be done in order to minimize yield losses. This Advanced Process Control (APC) approach  dedicated to stress minimization requires convenient stress monitoring methods. Conventional local strain measuring techniques, like Xray diffraction  or Raman microcopy , are not easy to implement in a standard process flow or are destructive. It is more convenient to control the global wafer shape in order to reduce the global mechanical stress impact, but the local information is lost. Thus, in response to industrial environment, data collection has to be non destructive, fast, easy to perform, low cost and process compatible. For these reasons, it was chosen to develop embedded stress microsensors with electrical monitoring to be performed during the standard electrical test stages. We developed a first test structure dedicated to polysilicon stress monitoring. The first reason for this choice is that wafer
Using standard CMOS process steps was the main guideline for the design of this polysilicon stress sensor structure. To have total process compatibility, it was convenient to use the piezoresistivity effect of silicon and monitor the resistivity change induced by the presence of polysilicon. A large literature exists on piezoresistive stress sensors which concerns mainly the monitoring of externally imposed mechanical stress (for monitoring of packaging stress for example) . Usually, resistor rosettes are used, or more complex structures based on MOSFET devices . In the present application, the source of stress is internal to the circuit stack. In this case, the main drawback is that the effective resistivity change may be due not only to stress but also to process variations. As was stated in , piezoresistive effect induces variations in the order of a few percents, as cumulated process variations, wafer to wafer or within wafer, may induce overall resistance changes in the order of 2%. For this reason, single sensors cannot be used here. The solution to circumvent this problem is to make a differential measurement, in other words to measure the resistivity change between two closely matched resistors: one standard, and the other with polysilicon strain. The test structure is therefore based on a Wheatstone bridge including four resistors with two strained and two unstrained resistors (Figure 1).
Abstract - For state of the art microelectronic technologies, reliability is a major challenge. Mechanical stress induced by the process steps is often at the origin of yield losses. Degradations of electronic devices are usually correlated to the presence of defects such as dislocations, cracks or delaminations. Usual methods for mechanical stress measurement generally require off-line measurements and are not compatible with fast correction of process parameters. We propose here embedded stress microsensors to allow fast monitoring of mechanical stress and enable real time correction of the process parameters. The test vehicle presented here is dedicated to polysilicon stress monitoring. Its feasibility, sensitivity and relevance in an Advanced Process Control objective are particularly investigated.
Figure 1: Schematic representation of a stressed Wheatstone bridge.
The stressed resistors are represented with a crossed arrow. We suppose that the four resistors have the same nominal value R, the resistance variation induced by the stress is noted δR. Only the offset voltage ∆V is measured as the current is swept. The resistance variation δR can be expressed versus the current and the offset voltage (i.e. the offset resistance ∆R) regarding the following equations:
R 2 − (R + δR ) ∆V = ∆R = 4 R + 2δR I
According to the piezoresistive effect, δR / R is in order of a few percent and can be neglected. This expression is reduced to:
δR = − 2 ∆ R
The use of a Wheatstone bridge allows contact errors free measurements and gives a response proportional to the resistivity difference between strained and unstrained resistor. This measurement technique allows solving the problem of across wafer and wafer to wafer variability since the compared resistors are in close matching. The remaining variability is thus related to the ultimate resistor matching, in the order of 0.2%, well under the 2% overall resistor variability. To investigate separately the resistor matching, a second structure with no stress modification will also be investigated. III SENSOR STRUCTURE AND FABRICATION Figure 2 shows the layout of the embedded test structure. Two sensors are placed in a standard 1x9 contact pad module. The first one (on the left) which is located between the pads 2 and 3 is composed of four boron implanted p+ resistors connected in a Wheatstone bridge configuration: named “Ref”. The second one (on the right) located between pads 7 and 8 is composed of the same resistors with the same Wheatstone bridge configuration excepted that two opposite resistors are stressed (named “poly”) by two polysilicon lines. Polysilicon lines are not electrically connected. The resistor dimensions are chosen with high aspect ratio: Length/Width = 20. Their main axis is oriented along the  silicon crystal orientation. All the resistors are rounded by Shallow Trench Isolation and special care was taken to ensure that each one has the same environment.
Metal1 SiO2 Figure 2: Layout of the structures. Above, the standard 1x9 contact pad module. On the left bottom, the reference bridge (Ref). On the right, the stressed bridge (Poly) with polysilicon lines.
The polysilicon is deposited by Low Pressure Chemical Vapor Deposition (LPCVD) at 620°C and lines are then etched. The line etching is performed by a 193nm photolithography process compatible tool. The obtained lines present a polycrystalline structure and are placed on the Shallow Trench Isolation (STI) silicon oxide and oriented along the main resistor axis (Figure 3).
Figure 3: SEM cross sectional view of a stressed resistor with polysislicon lines. The lines are on the STI and their long axis is perpendicular to the cross section plane in the  direction.
A study of the two different structures (unstressed and stressed) has been performed by Scanning Electron Microscopy (SEM). Figure 3 is a SEM cross sectional view of a half stressed resistor by polysilicon lines. On the picture only the right half resistor is represented. The cross section is made in the 110 plane perpendicular to the resistor main axis. Polysilicon lines are above the STI and oriented along the  silicon crystal orientation i.e. parallel to the main axis of the resistor. The silicon active area the STI and the poly lines are covered with a thin nitride layer and by an oxide layer covering the stack. The two polysilicon lines, regarding to their ratio L/W = 20, can impact only the environmental stress of the active silicon in the long resistor direction. The reference bridge (Ref.) presents the same characteristics excepted that the polysilicon lines are missing.
IV. ELECTRICAL RESULTS All electrical measurements are performed on a dedicated high precision measurement system, consisting of a Keithley 4200 precision semiconductor parameter analyzer and a Suss Microtec PA200 semi-automatic probe station. Figure 4 compares I-V characteristics between an unstressed reference (Ref.) bridge and a stressed one (Poly.) performed on a golden wafer site.
From this sketch, the median value can be extracted. This value corresponds to the x value at y=50%. The standard deviation of each population can also be estimated from the slope at the median value according to the following formula:
σbridge is standard deviation of the population.
As expected, the reference bridge has a median value very close to zero. Its distribution shows some variability which can be associated with the ultimate matching between the reference resistors. The Ref. and Poly. populations are clearly separated. This indicates a stress-induced resistance change δR / R = 0.38% Moreover, the Poly. population shows a higher standard deviation compared to the Ref. population The results are reported in Table I. The reference value for R is 2507 Ω. Table 1: Experimental statistical data extracted from distributions
Figure 4: I-V characteristic of Ref. and Poly. bridges on one site.
The linearity of experimental data allows to extract the slope with a high accuracy and then to estimate accurate values of the offset resistor ∆R. As expected, the unstressed bridge presents a very low offset voltage. A significant increase of ∆R is observed in the case of the stressed structure, and this demonstrates the mechanical coupling between the polysilicon lines and the resistor . An individual structure thus shows, with respect to a reference structure, a clear deviation, that can be attributed to the additional polysilicon stress. To further investigate the accuracy of the structure, a full eight inches wafer mapping was carried out on 31 sites. The results of the ∆R measurements for the test structures Ref and Poly are shown in cumulative frequency form in Figure 5.
Experimental statistical data: Median of Ref. Median of Poly. σRef σPoly
δR / R (%) 0.048 0.38
Further discussion of these results is made in next part.
V. ASSESSMENT OF THE STRUCTURE AND VARIABILITY ANALYSIS
To assess the relevance of the sensor, the results presented above may be discussed regarding three key points: - First, the shift of median value represents the average resistance deviation due to stress. This value should be in good agreement with the known stress modification induced by the polysilicon. The polysilicon lines disturb the mechanical stress generated by the STI surrounding the resistors. In our case, the stress modification is uniaxial along the main resistor axis. We can estimate the effective stress level at the resistor according to : ∆σ =
Figure 5: Comparison of the offset resistor ∆R distribution between Ref. and Poly.
(ohm) 0.6 4.8 1.5 2.4
1 δR × ΠL R
Where πL, in this case, is the silicon piezoresistive coefficient in the  direction. Considering our previously extracted πL according to , the additional stress induced at the resistor by the polysilicon lines is compressive and can be estimated to 13.6 MPa. This value is in good agreement with our mechanical simulations. The extracted stress value represents
the perturbation of the resistors by the stress in polysilicon. Obviously, this is not the effective value of the stress in polysilicon lines. The correlation between these two stress values are made through coupled process-mechanical simulation (not detailed here). - The second key point is that the reference structure presents a median value close to zero, showing that the bridge is balanced, as expected. This structure shows however some variability. This variability represents the ultimate matching of the resistors. The active layer indeed undergoes a level of stress imposed by the STI oxide [9,10] that might be responsible for this scattering. To evaluate the standard deviation of the resistors, equation (1) can be written taking into account the resistor mismatches:
δ r2 + δ r3 − δ r1 − δ r4 4
Where δri terms represent the ultimate mismatch on each resistor (2,3 and 1,4 opposite diagonally) and δR the stress variation. Considering that the standard deviation of each resistor due to mismatch is the same for all the resistors, the standard deviation of ∆R can be written as:
σ bridge =
2 2 σ poly −line + σ mismatch
VI. CONCLUSION Mechanical stress is a major issue for up to date microelectronic technologies. We demonstrated embedded sensors aimed at polysilicon stress monitoring in an Advanced Process Control scheme. Unlike other stress measurement techniques, they allow fast electrical stress monitoring without any additional process cost. We were able to track very small resistor variations due to polysilicon and easily extract the average polysilicon induced stress level as well as the polysilicon-induced standard deviation across the wafer. Those extracted values are in good agreement with our coupled process-mechanical simulation and assess the relevance of this structure. It is ready for its integration in Run to Run loop and will be of special interest for strain engineered silicon technologies control. ACKNOWLEDGMENTS This research was financially supported by: the “Communauté du Pays d’Aix”, the “Conseil Général des Bouches du Rhône” and the “Conseil Régional Provence Alpes Côte d’Azur”, through the focused research program called "Rousset 20032008" in partnership with STMicroelectronics. Special thanks to Valérie Serradeil-Luton and Jean-Luc Liotard STMicroelectronics Rousset teams managers for their help and interesting discussions. REFERENCES
This formula allows calculating the standard deviations of the resistor as a function the measured one. For the reference structure, σpoly-line is zero. Then;
σ mismatch = 2 σ ref = 3Ω ≡ 0.12% This value is in good agreement with the known mismatch value from the technology Design Rule Manual - The third key point is that the Poly structure shows additional scattering compared to the reference structure. If this additional scattering is entirely due to the fluctuation of stress level in polysilicon lines, the standard deviation of effective stress at the resistor is then:
σ stress = σ poly−line = 3.8Ω ≡ 0.15% This corresponds to an across wafer stress variation of 5.4 MPa. One can see that the Wheatstone bridge configuration allows tracking very small resistance variation and give the sensor very high electrical sensitivity. The ultimate mismatch scattering is the main limitation, preventing a true local stress characterization. To overcome this limitation, the mechanical coupling between polysilicon and the resistor should be increased by an upgraded layout of the structure
 Hu, S.M., “Stress-related problems in silicon technology”, J. Appl. Phys., vol. 70 (6), pp R53-R80, 1991.  Flinn P.A., Gardner D.S. and Nix W.D, “Analysis technology for VLSI fabrication”, IEEE Trans. On Elec. Dev., Vol 34(3), pp 689-699, 1987.  Moyne J., Kim J., Beachy M.and Parikh T. “Determining RTR control deployment strategies from process run data”, 2nd European Advanced Equipment Control / Advanced Process Control (AEC/APC) Conference, Dresden, 2001.
 Noyan. I, Cohen. J, Residual Stress, (Springer Verlag, Stuttgart) 1987.  O. Slattery, « Sources of variation in piezoresistive stress sensor measurement », IEEE transactions on components and packaging technologies, 2004, pp 1-5  R. C. Jaeger et al, « CMOS stress sensors on (100) silicon », IEEE journal of solid-state circuits, vol. 35, NO1, january 2000  Manic D., Igic P. M., Mawby P. A., Haddab Y.and Popovic R. S., “Mechanical stress related instabilities in silicon under metal coverage”, IEEE Trans. On Elec. Dev., vol 47, n° 12, pp 2429-2437, Dec. 2000.  Smith C.S., « Piezoresistance effect in germanium and silicon », Phys. Rev., vol. 94, n°1, pp 42-49, 1954.  Hu S. M., “Film-edge-induced stress in silicon substrates”, Appl. Phys. Lett. Vol. 32, issue 1, pp5-7, 1978.  Moroz V., Strecker N., Xu X., Smith L. and Bork I., “Modeling the impact of stress on silicon processes and devices”, Materials Science in Semiconductor Processing VI, pp 27–36, 2003.