ESD: a pervasive reliability concern for IC technologies

ESD: A Pervasive Reliability Concern for IC Technologies CHARVAKA DUVVURY,

MEMBER, IEEE, AND

AJITH AMERASEKERA, MEMBER, IEEE

Invited Paper

Electrostatic discharge (ESD) is considered a mujor reliability threat to integrated circuit (IC) technologies. A review of the ESD phenomena along with the test methods, the appropriate onchip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits, are presented. The presenr status of understanding the ESD failure physics and the current approaches f o r modeling are also discussed. This overview paper deals with several aspects of ESD from the point of view of the test, design, product, and reliability engineers.

I. INTRODUCTION In the present advanced stage of integrated circuit (IC) technologies, almost everyone is aware of the electrostatic discharge phenomena, commonly known as “ESD,” and its potential destructive effects on VLSI chips. The major impact comes from the Human Body ESD events. In a typical work environment of shoes and carpets, a charge of about 0.6 pC can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4 kV or greater. Any contact by the charged Human Body with a grounded object such as an IC pin can result in a discharge for about a 100 ns with peak currents in the amperes range. The high energy associated with this discharge could mean failure to electronic devices and components. Typically, the damage could be oxide rupture and device or interconnect burn out. The latter form of damage requires a large amount of energy. Many semiconductor devices can be damaged even at a few hundred volts, but the damage is too weak to be detected easily, resulting in what is known as “walking wounded” or “latency effects.” A device can be exposed to undetected jolts of ESD starting from the fabrication area during process all the way to the board level in the system end-user. Thus precautions to suppress ESD become important through all phases of an IC device’s life. A broad overview of this will be presented in this paper. The paper Manuscript received September 3, 1992; revised November 9, 1992. The authors are with the Semiconductor Process and Design Center, Texas Instruments Inc., Dallas, TX 75265. IEEE Log Number 920925 I .

will more specifically address the understanding of the ESD phenomena and the required protection for IC chips. As an outline, the basic concepts of ESD and the appropriate protection techniques are reviewed in Section 11. The representation of ESD threat comes in various stress models including the Human Body Model (HBM). These are reviewed in Section 111. The on-chip protection techniques depend on the process technology and the IC pin application. Some examples of these are presented in Section IV where NMOS, CMOS, and BiCMOS technologies are considered. Section V will deal with the typical failure modes caused by ESD in MOS technologies and the influence of the process technologies. In recent years modeling techniques to understand and solve ESD reliability have been going through interesting developments but are still at early stages. These techniques and their limitations are discussed briefly in Section VI. A controversial topic in ESD is the latency phenomenon where low level damage due to ESD is suspected but not conclusively proven. Some examples of latency are discussed in Section VII. Since ESD is important from chip level to board level, some issues associated with board level phenomenon and the protection methods are outlined in Section VI11 . Finally, even with all the protection concepts available today, there are still some unresolved issues involved with the ESD phenomena. These, along with the important future issues for ESD, will be reviewed in Section IX. 11.

ESD BACKGROUND

ESD is actually a subset of a broad spectrum of electrical stress that is known as electrical overstress, or EOS, where the EOS family includes lightning and electromagnetic pulses (EMP’s). The main concem for the microelectronic chips is ESD, which is in the time scale of the 100 ns range. EOS, on the other hand, commonly refers to events other than ESD that encompass time scales in the microsecond and millisecond ranges. These events can occur due to electrical transients at the board level or the system level. They can also occur during device product engineering

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characterization or during the bum-in test. Although much of the reliability focus has been on ESD, EOS is now considered to be a major issue and an increased attention to this is expected within the next few years. In this paper, only the ESD related phenomena will be reported. Fundamental electrostatics tells us that when two materials are brought together and then separated, they acquire charge through electron exchange. The main ESD problem in a FAB is static charge generation which should be suppressed. The prevention methods could be the use of antistatic coatings to the materials or the use of air ionizers to neutralize charges. The damage due to human handling can be reduced by the proper use of wrist straps for grounding the accumulated charges and shielded bags for carrying the individual wafers. Static control and awareness are two important programs to combat ESD in the semiconductor manufacturing environment [ 11, [2]. As a second step to reduce ESD effects, proper design of protection circuits are implemented within the IC chip. With effective protection circuits in place, the packaged device can be handled safely from device characterization to device application. However, the packaging procedure itself can cause serious damage and thus antistatic precautions are also needed during wire bonding. Even with good protection circuits, the devices are not immune to ESD once they are in the circuit boards. Other forms of ESD from the charged boards is possible. Thus ESD precautions are important during system assembly as well. The implementation of effective on-chip protection is a challenging task and requires several design iterations to optimize. This is mainly because no reliable modeling programs are available to date and the designer thus has to rely on empirical studies on test structures in silicon. However, there has been considerable progress in recent years in electrothermal modeling.

111. STRESSMODELS ESD stress models are based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standard models have been developed, known as the Human Body Model (HBM), Machine Model (MM), and the Charged Device Model (CDM). The names are derived from the origin of the ESD pulses. Details of the three models are given in this section. A. Human Body Model ( H B M ) The HBM is the principle ESD test method used in industry today, and is specified in the MIL-STD 883C method 3015.7. The test method attempts to reproduce an ESD waveform generated by the discharge of a human being through a low impedance path. A typical waveform is shown in Fig. 1, and is defined as having a risetime of < 10 ns, and a decay time of about 150 ns. The pulse is generated by the discharge of a 100-pF capacitor through a 1.5-kR resistor (C, and RI in Fig. 2 ) into the device under

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test. The discharge circuit was based on the requirements for generating the double exponential pulse shown in Fig. 1, which was determined to be typical of that generated by a charged human body. The rise time of the pulse translates into an effective inductance, and the equivalent LCR circuit is shown in Fig. 2 [3]. C, is the discharge capacitor which is initially charged to the ESD stress voltage V I .RI is the discharge resistor, and L1 is the parasitic inductance introduced by the wires. In addition, the capacitance of the resistor is modeled by C,, and the capacitance of the test socket is modeled by C,. These parasitics influence the rise time and overshoot of the ESD pulse, as shown in Fig. 1. Typical values of L1, C, and Ct are 7.5 p H , 1 and 10 pF, respectively. Testing specifications usually require circuits to be able to have a minimum pass threshold of +/- 2000 V HBM ESD stress on all pins, with respect to the supply pins, V,, and V,, individually, and with respect to each other. However, ESD pass thresholds of 1000 V are still acceptable for more complex circuits, such as microprocessors and microcontrollers as well as large (> 1Mb) SRAM’s and DRAM’S. More aggressive manufacturers have developed 4000-V ESD resistant circuits, even for advanced circuits and technologies, creating a target level which other manufacturers are urged to achieve. There is a good reason for this - the U.S. military requires that all products with less than 4-kV ESD robustness be labeled ESD sensitive and be subject to special handling procedures.

DUVVURY AND AMERASEKERA: ESD: A RELIABILITY CONCERN FOR IC TECHNOLOGIES

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The choice of 2 and 4 kV as threshold levels for ESD qualification have no specific meaning in themselves. However, there is evidence that products with ESD thresholds 4 kV, no significant decrease in the fallout rate has been observed, and the additional cost required to achieve even higher ESD threshold levels is not considered to be worthwhile. The automotive industry, on the other hand, does require even higher ESD levels, ranging up to 10 kV, and in some instances 20 kV, because of the hostile environment in which these parts operate. These levels are not, however, typically required for state-of-the-art IC’s.

B. Machine Model ( M M ) The MM originated in Japan, as an equivalent to the HBM, but based more on the type of stress which may occur in automated assembly areas. The circuit model for the MM is the same as that for the HBM shown in Fig. 2. The discharge capacitor C, is increased to 200 pF and, ideally, the model requires that R I = 0 f2, but for practical purposes, there will always be a finite resistance. In addition, the low impedance system will mean that the parasitic inductance, L1, and the stray capacitance, C+,will have a significant influence on the dynamic impedance, and therefore, on the amplitude and frequency of the discharge current waveform. Since there is no established specification for the MM test method, the definition of the series inductance will play a major role in defining the ESD failure threshold. L1 is influenced by the socket and package leads, and for values < 1 p H it is difficult to obtain reproducibility between pins on the same package. This has caused some problems in comparing MM testers; however, present testers use an inductance of between 0.5 p H and 2.5 p H with R I being around 10 0, achieving some form of compatibility. The MM waveform is stable for values of RL between 0 R and 10 R. As R L is increased, the oscillating frequency is changed, and for R L > 100R, or L1 > 10 p H . the MM ceases to oscillate and the waveform will be similar to that of the HBM. Because of its higher current levels for a given discharge voltage when compared to the HBM, the pass thresholds for the MM required for commercial IC’s are typically 200 V. However, as in the case for the HBM, a target specification is 400 V for more aggressive manufacturers, while state-of-the-art IC’s are usually passed at 100 V levels. C. Charged Device Model

Failure modes with the HBM and MM test methods have been found to be similar, and usually result in damage in the diffusion area of the protection circuits. As protection circuits improved, and devices became more capable of withstanding 2-kV HBM and 200-V MM stress levels, a failure mode was observed which could not be reproduced 692

by these two tests. These failures were usually observed to be due to breakdown of the gate oxide of the MOS transistors in large IC’s, either at the input or in the internal circuitry [4] The CDM test method is intended to reproduce the effects of mechanical handling in the manufacturing and assembly areas. Here, packaged IC’s themselves get charged up to high potentials, and the stored energy is discharged when one of the pins is grounded. Charging may take place when the device is being transported along conveyor belts during assembly or in the final test area, for example. The discharge occurs when one of the pins is contacted by a metal handler or inserted into socket. CDM pulses have very fast durations, < 1 ns, and current levels may reach several amperes for a single event. The damage in the gate oxides is caused by the voltage drops which occur in the metal interconnect due to the self inductance and the fast rise time of the pulse. Standard input/output protection circuits do not provide adequate protection against these pulses because they are limited by the response times of the transistors (of the order of I ns). Typical CDM pass levels are 1 kV. However, the absence of either an industry standard or a fixed test method, coupled with a very limited understanding of the test method itself, has resulted in a very arbitrary setting of the pass thresholds. It is expected that the CDM will become an important ESD test method, especially with the trend towards thinner gate oxides and big chips with complex metal routing. However, there is still a lot of work that needs to be completed before the test method will be sufficiently mature to be an industry standard. One of the biggest problems is the very high frequencies (> 1 GHz) involved, which together with the high current levels, make monitoring and calibration of the stress pulse a nightmare for the test engineer. IV. ON-CHIPPROTECTION The traditional on-chip protection techniques have undergone a significant evolution during the last ten years with more innovative protection circuits being recently reported. With the advances in both process technology and circuit complexity the protection circuits of the previous generation could not always be used. These new protection concepts extended from NMOS to CMOS and now to BiCMOS. In this section the protection techniques for each of these technologies are reviewed. In each case the impact of process changes on the design are also discussed. A . NMOS Protection

In an NMOSFET protection scheme, either the thin oxide nMOSFET (with the gate tied to ground) or the n-channel thick field oxide transistor (with the gate connected to the drain pad) is generally used as a protection device. For the conventional abrupt junction processes, when the drain junction is stressed common to the source and substrate, the breakdown will occur at the cylindrical portion of the junction causing maximum heat generation at this P R 0 C t t l ) l N C S OF THP, IEEE. VOL. X I . NO. 5 . MAY 1993

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location. The heat dissipated at the junction then leads to thermal breakdown and damage at the drain junction. Further heating results in a metal melt filament formation or result in a polysilicon melt filament by spreading heat to the gate directly above the thin oxide, in the case of a MOSFET. For both thin oxide and thick oxide devices, moving the contact farther way from the junction improves the ESD performance [SI. This parameter is indicated in the case of a thick oxide device in Fig. 3. A typical maximum practical value for this is about 6 pm. Another critical parameter that is effective is the width of the device, which, when maximized, will reduce the local heat generation and improve the ESD level. Commonly, for the NMOS technologies of 2.0 to 1.5 pm, the thick oxide device was used for input protection and the thin oxide device for output protection. Both of these devices operate as parasitic bipolar n p n devices during the ESD event, with the drain as the collector, the substrate as the base, and the source as the emitter. See Fig. 3, for example. Consider the I-V breakdown characteristics of an nMOSFET with the gate and source at 0 V as shown in Fig. 4. As the input current is increased from zero, the transistor goes into avalanche followed by snapback due to parasitic bipolar action between the n-drain (collector), the p-substrate (base), and the n-source (emitter). Snapback takes place at a trigger voltage of Vtl and a current Itl. The snapback holding voltage is given by V., in the figure, and most of this voltage is across the depletion region of the reverse-biased drain-substrate junction. As the current is increased further, the low on-resistance of the npn results in a relatively small voltage increase, until at &2 and It2 a second “snapback’ is observed. This has been termed second breakdown in bipolar transistors and is the source of one of the major operating limits in bipolar devices [6]. During the ESD event the device operates mostly in the snapback mode with V., as the clamping voltage. At higher stress levels the device could go into this second breakdown mode where filament formation is encouraged and the device failure eventually occurs. This V,, value, which is dependent on the process and the channel length, plays a limited role in improving the ESD [7]. The essential difference between the thin and thick oxide devices is the T I , ~ T I . trigger voltage, which occurs at the

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Fig. 4. I-V characteristics of an NMOST showing the bipolar snapback and second breakdown.

drain avalanche voltage in the former and at the thick field device turn-on (25-30 V) [8] in the latter. For this reason, the thick field device cannot be used for output protection since the output buffer device itself will turn on first. Therefore, for output pins the n-channel buffer device should form the protection. With advanced process technologies including LDD transistors and silicided diffusions, both of these devices become ineffective and restoring their protection performance needs an understanding of the protection phenomena. As mentioned earlier, an effective on-chip protection circuit must provide immunity to minimum stress levels of 2 kV caused by human handling. During ESD stress, failures can be prevented if the protection scheme can maintain uniform current density within its area. For the conventional abrupt junction processes a field oxide device, when properly optimized, can yield 6 kV of protection for only a 150 pm wide device. Since the current density is dependent on the perimeter, the junction depth of the process has some positive impact [8]. Other process parameters such as oxide isolation techniques, multilayer metal systems, and contact sizes do not have a known clear impact. To implement this device at the input, the buffer gate must be protected. This is simply achieved by placing a diffused isolation resistor and a thin oxide grounded gate device in series as shown in Fig. 5 . The thin oxide device breaks down into the npn mode first and builds up the pad voltage through the resistor to subsequently trigger the thick field protection circuit, which dissipates the bulk of the ESD energy. The ESD performance of the thin oxide output device is much less effective, usually resulting in about 8-10 V ESD protection per micrometer of device width for the conventional processes. Even this is critically dependent on the layout. The ladder structure shown in Fig. 6 is most often used to provide uniform current density and maximize the protection level. Here the parasitic resistance RF is composed of the metal finger resistance, contact resistance, and diffusion sheet resistance; and the parasitic resistance

DUVVURY AYD AMFRASEKERA ESD A RELIABILITY CONCERN FOR IC TECHNOLOGIES

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Rs is that of the ground bus that connects the fingers of the device. Maintaining a minimum ratio for RsIRF is important for best possible performance from this devicc. Note that while maximum RF is desirable, contact resistance itself should not be high since damage could result from excessive contact heating. For the output protection also, a deeper junction is best for high performance. Besides this, a minimum channel length is preferred for smaller V,,, and reduced power dissipation during ESD. B. Process Impact on ESD Protection Design During the last decade, the LDD devices as well as graded junction devices have become popular for CMOS. In these structures the peak electric field near the drain pinch off region is reduced, resulting in improved hot carrier reliability. The consequently expected improvement in ESD due to the reduced electric field was not only not realized, but the ESD performance actually degraded in these structures [9]-[ 121. It was first shown in [lo] that for thick oxide devices the graded junction process degraded the failure threshold to about 65% of the value with a conventional abrupt junction process. However, the work of [ 1 11 indicated that for graded junction thick oxide devices, ESD performance can be optimized by a careful balance between the source/drain implant species, dose, and drive time. However, neither a clear correlation to the process nor an understanding of the ESD degradation was obtained. More investigations with thin oxide nMOSFET devices have led to further insight as discussed in the following. Both the LDD and graded drain processes use a relatively higher level of substrate doping to reduce the short channel effects. This, of course, increases the drain avalanche as 694

well as the bipolar snapback voltage [13]. Therefore, the increased V,, (in Fig. 4) has been suspected to be reason for the drop in ESD for these process options [7]. This was more thoroughly studied in [12]. From this later work, the ESD failure voltage is plotted as a function of device width for various graded junction process options in Fig. 7. Two important points are to be noted. First, the failure threshold slope increases with an increase in the sourceJdrain phosphorus dose. This is because the junction becomes less graded in nature, and subsequently, the bipolar snapback voltage also decreases. Secondly, for the lower phosphorus case the addition of surface arsenic has a significant impact in improving the ESD level. This improvement is attributed to the surface arsenic modifying the junction profile near the surface, making it more abrupt in nature and decreasing the snapback voltage as the depletion region exposes the abrupt arsenic junction. Although these results partially explain the ESD phenomena in graded junction devices, a full consistent explanation has not been established. Such understandings require transient thermal analysis programs that can clearly correlate to the process variations. These are briefly addressed in Section VI. It was reported in [7] that the LDD process degrades the thin oxide ESD performance more than that for graded junction process. The reasons are again: 1) the snapback voltage for the LDD is higher than for the graded junction, and 2) the effective junction depth is shallower. It is suspected at this time that for the LDD device compared to the graded junction devices, the drain breakdown area is smaller thus resulting in increased current density (J) or higher power density J.E for a lower failure threshold. This has not yet been clearly established with experiments or with any detailed transient thermal simulations. As originally reported in [lo], clad silicides reduce the thick oxide ESD performance to less than 35% of the level with the nonsilicided abrupt junction process. Also, from the work on thick oxide device in [l 11, when silicide is included, the use of graded drain process variations had almost no appreciable impact. This leads one to conclude that silicide is clearly the weak link. The weakness with clad silicide was later established for thin oxide devices also in [14] and [15]. PROCEEDINGS OF THE IEEE. VOL. 81, NO. 5 , MAY 1993

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(h) Fig. 8. ( a ) Cro\\ wction of :I \ilicided LDD trnn\i\tor \houInp curreiit density a1 the silicide and silicon iii[erlxc. from [ 171. chi ESD dainage in a silicided NMOS thick tirld de\icc. \howiiig

symmetrical inelt filaments at both drain and \ource.

The clad diffusions modify the device .;ource/drain resistance due to the effect of silicide/silicon interface [ 161. As reported in [ 17). this results in nonuniform current density with the peak occurring at both the drain and source sidewall edges. This is illustrated i n Fig, 8 (a). With the current peak at these points, the J.E product is naturally highest, leading to a premature ESD failure at a relatiLely low stress level. Also, not only that. it leads to syninietric failure models as shown in Fig. 8 (b). As pointed out in [ 171. the key parameter to improve the ESD perforniance is to make the current density as uniform as possible. This can be done by increasing the contact transfer length I., . which defines the region of nonuniform current density [ 161. The longer L, \ d u e can thux have an improved effect. The process variables that can affect this are the silicide anneal temperature [ 161 and the silicide thickness. Previously it was shown in references [7].[ I X ] that thinner silicide improved the ESD of thin oxide de\ ice