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Nuclear Instruments and Methods in Physics Research A 510 (2003) 122–125
FPGA-based data acquisition system for a Compton camera$ K. Nurdana,b,*, T. C¸onka-Nurdana,c, H.J. Beschc, B. Freislebenb, N.A. Pavelc, A.H. Walentac a
CAESAR (Center of Advanced European Studies and Research), Friedensplatz 16, Bonn D-53111, Germany b Uni-Siegen, FB Elektrotechnik und Informatik, Ho¨lderlinstrr. 3, Siegen D-57068, Germany c Uni-Siegen, FB Physik, Emmy-Noether Campus, Walter Flex Str. 3, Siegen D-57068, Germany
Abstract A data acquisition (DAQ) system with custom back-plane and custom readout boards has been developed for a Compton camera prototype. The DAQ system consists of two layers. The first layer has units for parallel high-speed analog-to-digital conversion and online data pre-processing. The second layer has a central board to form a general event trigger and to build the data structure for the event. This modularity and the use of field programmable gate arrays make the whole DAQ system highly flexible and adaptable to modified experimental setups. The design specifications, the general architecture of the Trigger and DAQ system and the implemented readout protocols are presented in this paper. r 2003 Elsevier B.V. All rights reserved. PACS: 07.05.Hd; 87.59. e Keywords: Compton camera; Data acquisition systems (DAQ); Field programmable gate arrays (FPGA)
1. Introduction A Compton camera (CC) is a gamma-ray imaging system, which consists of two radiation detectors a scatter detector and an absorption detector. A gamma-ray incident on the camera can be imaged when it Compton scatters in the scatter detector producing recoil electron and the scat-
tered photon is detected in time coincidence at the absorption detector. A monolithic array of 19 silicon drift detectors [1] as the scatter detector and an Anger Camera without lead collimator as the absorption detector are used in the prototype system [2,3].
2. System hardware $
Work Supported by CAESAR (Center of Advanced European Studies and Research). *Corresponding author. Address for correspondence: University of Siegen, ENC FB7, Walter Flex Str. 3, Siegen D-57068, Germany. Tel.: +49-271-740-3534; fax: +49-271740-3533. E-mail address:
[email protected] (K. Nurdan).
The data acquisition system (DAQ) presented in this paper covers the electronics between the frontend analog electronics (FE) and the image reconstruction computer (Fig. 1). The DAQ performs the reconstruction of Compton event data and its system hardware is based on two types of
0168-9002/03/$ - see front matter r 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0168-9002(03)01688-7
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Fig. 2. Single channel architecture.
Fig. 1. Overall system architecture.
modules connected by a custom-designed active back plane. The first module is a channel processor module (CPM). The CPM is responsible for the digitization of analog input signals and the extraction of desired features (like peak, integral, etc.). The extracted features are time stamped and buffered for further processing in an event builder module (EBM). The EBM collects extracted features with their time stamps, channel numbers from CPMs and applies Compton coincidence logic to reconstruct the event fulfilling the requirements. 2.1. Channel processor module The CPM hardware consists of four 12-bit analog/digital converters running with a system clock of 66 MHz with differential filtered analog inputs, a Xilinx Spartan IIE Field Programmable Gate Array (FPGA) which is responsible for collecting data and communicating with the bus, an FGPA configuration ROM and a voltage regulator. Special care is taken to avoid cross-talk between the analog channels and the digital bus logic. The control logic of an FPGA is implemented slightly different for two types of detectors. Flexible and reprogrammable FPGAs enable the application of different control tasks without changing the hardware. 2.1.1. Implemented FPGA logic for scatter detectors The architecture of the data flow implemented for the scatter detector channel is presented in Fig. 2. The data flow starts with a programmable
digital delay where data can be delayed up to 256 clock cycles (approximately 4 ms). FE delays can be compensated and even reordering events in time relative to their appearance can be arranged. Delayed data are then fed into a trigger unit and a second small delay, where it is possible to capture the rising or falling edge of signal. The trigger unit is programmable with a threshold word and has selectable modes of rising edge, falling edge, higher-level and lower-level triggering. The triggering decision is transferred to a local channel controller (LCC). The LCC decides, according to its configuration, which causal operators (peak finding, integration, etc.) should be applied to incoming data within a programmed processing time window. The following four operators are implemented: peak finding, integral, raw data, time stamp, and the operators may be enabled inclusively. The processed data are then transferred to a derandomization FIFO buffer. The transfer of data from derandomization buffers to the EBM is achieved by slave bus controller (SBC) logic (Fig. 3). There may be only one master but many slaves on the bus. As there are four physical channels per CPM card, a single SBC is implemented and it serializes data to be sent over a bus to the EBM which is coordinated by a bus master (BM) implemented in the EBM. 2.1.2. Implemented FPGA logic for absorption detector The absorption detector FE electronics produces already shaped signals with a proper trigger. The signals are X ; Y coordinates, energy and a digital trigger. We used the same structure as defined above with the following changes: The first three channels on the CPM are assigned as X ; Y and E signals. The fourth channel is assigned as
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K. Nurdan et al. / Nuclear Instruments and Methods in Physics Research A 510 (2003) 122–125
Fig. 4. BM and EBM.
Fig. 3. Bus slave.
the trigger signal and the internal trigger decision of this channel is hardwired to others, so that they start at the same time. The SLB is also modified to utilize a single bigger derandomization buffer. This modified CPM can signal its status to the EBM through a priority signal. 2.2. Event builder module The EBM hardware is implemented with a 1M 18bit NtRAM from Samsung, a Xilinx SpartanIIe and an LVX161284 physical level parallel port interface from National Semiconductors. 2.2.1. Implemented FPGA logic The schematic of the EBM with the integrated BM logic can be seen in Fig. 4. All CPMs have dedicated request lines to the BM. With the help of a priority signal, the BM also identifies the CPM dedicated to the absorption detector. The BM controls two queues where the received data are pushed in. The data received from the absorption detector are pushed in one queue (ABS-REG) and all others to the other queue (SCAT-REG). Due to the nature of the Compton events the ABS-REG queue length is set to 1. If new data arrive to the ABS-REG, the SCAT-REG queue is cleared and made ready for the next possible Compton event. The coincidence logic checks time stamps from
both queues and if the time stamps fall within a defined relative time window they are accepted as coincidence candidates and the programmable system controller (PSC) is informed about this decision. The PSC itself is some sort of a stripped microprocessor core with limited programmability. It continuously checks the coincidence decision and if a true decision arrives, it starts an internal timer and waits for a timeout. After timeout, it checks the status of the SCAT-REG queue. If there is still one event in this queue (and no new absorption detector events), it accepts this candidate as Compton event and transfers all data from the queues to the SRAM with a known data structure. The PSC is also responsible for establishing a PC connection and proper protocol to transfer data from the SRAM to the PC. The burst performance of the system can reach up to 8 M events per second with a three-cycle protocol delay and five cycles of data transfer with a system clock of 66 MHz. The dead time per channel is 2 clock cycles. Maximum achievable sustained data rate is 200 k events per channel per second while 32 channels are fully utilized. The Compton coincidence logic manages 500 k Compton events per second and the expected event rate is 10 k Compton events per second for the prototype system. The parallel port PC interface with a raw data transfer rate of 800 kB/s, is capable of carrying two times more information than required for the whole system.
3. Conclusion This paper described the architecture of a DAQ system for a CC. The system has been designed by
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using Xilinx SpartanII devices, 12 bit 65 MHz ADCs. The whole DAQ system is composed of a channel processor, a back-plane and an event builder. A CPM consisting of four channels and a back-plane hosting nine such modules has been designed. Peak detection, 24-bit time stamps, and integration operations are performed on each channel with the additional functionality of a programmable time window and a threshold for self-triggering. Up to 85 pre-processed events can be buffered for further processing in the FBM. The EBM provides an interface to a PC and handles the triggering logic. VHDL language has been used for programming the FPGA modules and simulations were performed by using ModelSim
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software. Tests with an input signal from a signal generator confirmed the performance of a 66 MS/s rate and a 10.5 bit resolution.
References [1] C. Fiorini, A. Longoni, F. Perotti, C. Labanti, E. Rossi, P. Lechner, H. Soltau, L. Stru¨der, IEEE Trans. Nucl. Sci. NS-49 (3) (2002) 995. [2] T. C¸onka-Nurdan, K. Nurdan, F. Constantinescu, B. Freisleben, N.A. Pavel, A.H. Walenta, IEEE Trans Nucl. Sci. NS-49 (3) (2002) 817. [3] T. C¸onka-Nurdan, et al., Proceedings of the IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyon, France, 2000.
