Future technology for advanced MOS devices

Nuclear Instruments and Methods in Physics Research B 186 (2002) 380±391 www.elsevier.com/locate/nimb

Future technology for advanced MOS devices C. Wyon

*

CEA/LETI, D epartement des Technologies Silicum/Section de Caract erisation Physico-Chimique, 17 Rue des Martyrs, 38054 Grenoble cedex 9, France

Abstract This paper describes some of the future technologies for next generation metal±oxide-semiconductor (MOS) devices, focusing on development of new materials. After a brief presentation of the future evolution of lithography tools, results on the development of high j thin ®lms, metal gates for the gate stack, low j materials for Cu interconnects and on the new technologies currently investigated to fabricate ultra-shallow junctions, will be presented. Ó 2002 Elsevier Science B.V. All rights reserved. Keywords: CMOS; Technology; High j; Gate stack; Ultra-shallow junctions; Low j; Cu interconnect

1. Introduction System on a chip (SoC) is the main technology theme of the semiconductor industry for providing superior multimedia products for the 21st century. SoC integration will require integration of (1) high performance, high density digital complementary metal±oxide-semiconductor (CMOS) logic having low active power, and in portable applications, low standby power, (2) embedded RAM: SRAM or DRAM, (3) ¯ash EEPROM or non-volatile memory replacement such as FeRAM, (4) analog CMOS for analog base band functions, (5) RF BiCMOS or CMOS for radio or tuner functions, (6) extended drain CMOS capable of withstanding

*

Corresponding author: Tel.: +33-4-38-78-31-18; fax: +33-438-78-94-85. E-mail address: [email protected] (C. Wyon).

5±10 V surges and (7) technologies to enable passive integration: capacitors, inductors. Since cost reduction is the goal, the challenge is to accomplish the integration of these technologies in low cost, deep sub-micron CMOS with minimal additions. For higher integration density and higher performance, scaling down the size and operation voltage of CMOS is inevitable. The SIAs International Technology Roadmap for Semiconductor (ITRS), published in 1999 [1], prospect the requirements for CMOS device scaling beyond 100 nm. Based on this prospect, the gate length is reduced by approximately 11% every year and the same drive current density is maintained with reduced operation voltage [2]. Gate and junction capacitances of a transistor are reduced due to the lateral size reduction even though thinner gate dielectrics are employed, therefore, the gate delay is expected to be reduced by 10% every year. The power dissipation of a chip is also maintained low

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C. Wyon / Nucl. Instr. and Meth. in Phys. Res. B 186 (2002) 380±391

because of reduced operation voltage even if the number of transistors in a chip increases. However scaling CMOS transistor beyond 100 nm with satisfactory performance is not so easy and many issues should be solved. To overcome these issues, virtually all parts of the transistor should be carefully modi®ed and optimised, which includes modi®cations of process conditions, physical structures and materials. This paper will review some proposals of new technologies to solve these issues. After a brief review of lithography solutions in order to pattern such smaller and smaller dimensions, materials issues concerning the gate stack, ultra-shallow junctions and interconnects will be presented. 2. Patterning Lithography has always kept apace of integrated circuits (IC) development, providing solutions for shrinking geometries and improved performance. The semiconductor industry has a strong interest in extending optical lithography as far as it can go because its reliability has been outstanding. Nevertheless semiconductor industry is trying to determine what will happen after optical lithography: next generation lithography (NGL) options are being currently narrowed.

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2.1. Optical lithography Currently main semiconductor industry uses 248 nm exposure wavelength delivered by a KrF laser to perform patterning of ICs. Reticle enhancement technology (RET) like optical proximity correction, phase shifting masks, extreme o€ axis illumination, sub-resolution assist features, etc. will extend 248 nm KrF technology down to sub-180 nm design rules. The most promising work has been presented by Chau et al. [3] who succeeded in producing a high performance CMOS transistor by patterning a 30  5 nm long poly-silicon line using 248 nm two-mask phase shift mask lithography. Nevertheless this RET will considerably drive up the mask writing and inspection cost, and so will strongly increase the chip cost. Another signi®cant challenge resides in low contrast targets resulting from extensive CMP use. The fundamental limits of optical lithography are captured by the Rayleigh scaling equations, Wmin ˆ k1 …k=NA†

…1†

and DOF ˆ k2 …k=NA2 †;

…2†

where Wmin is the minimum linewidth, DOF is the Rayleigh depth of focus, k is the exposure

Table 1 A comparison of optical and non-optical lithography techniques Parameter

193 nm

157 nm

126 nm

EBDW

SCALPEL

X-ray

EUV

k

193 nm ArF laser

157 nm F2 laser

126 nm Ar2 lamp

4 pm cathode guns

4 pm cathode guns

1 nm synchrotron

Exposure mechanisms Optics

Photons

Photons

Photons

Electrons

Electrons

Photons

11±14 nm laser plasma discharge Photons

Transmission SiO2 or CaF2 P 0:75 4 Transmissive

Re¯ective

Electrom.

Electrom.

Re¯ective

Re¯ective

NAs Reduction Mask type

Transmission SiO2 or CaF2 P 0:75 4 Transmissive

0.5 4 Re¯ective

± N/A None

Wmin (nm) DOF (lm) Throughput (wafer h 1 )

150±100a 0.4a > 100 (/: 200 mm)

125±80a 0.28a 50±80 (/: 300 mm)

150±100a 0.5a ?

22 N/A Depends on die

0.001 4 Membrane transmissive 0.24±0.16a 400a 20±30 (/: 300 mm)

N/A 1 Membrane transmissive 30 N/A ?

0.1 4 Re¯ective (multilayer) 70±45a 1.1a 50±80 (/: 300 mm)

a

Wmin and DOF are theoretically calculated using Eqs. (1) and (2) with k1 ˆ 0:6 and 0.4 (Source: Sematech).

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wavelength, NA is the numerical aperture of the projection optics and k1 and k2 are the Rayleigh factors. There is a strong motivation to shrink exposure wavelength since minimum linewidth scales proportionally. Table 1 lists several wavelengths of interest to optical lithography. 193 nm lithography is progressing although it has not yet reached production levels. With considerable challenges in lens material (SiO2 or CaF2 ) stability, pellicle lifetime, resist processing and laser source stability 193 nm lithography will be adopted in 2002 for 130 nm technology node and later for 100 nm technology node, and perhaps a little beyond. The F2 laser at 157 nm would seem to o€er another incremental advance for optical lithography and would probably allow to postpone the use of NGL tools. Several problems remain, however, before the industry can implement this technology to an industrial level. Fused SiO2 , the well understood mainstay for 248 and 193 nm optics, has unacceptable transmission at 157 nm. CaF2 is the most promising material for refractive elements, but large pieces (larger than 150 mm in diameter) with the required quality are not industrially available. Progress in 193 nm optics will drive learning to improve CaF2 single crystal quality and polishing techniques. Production-level 157 nm lithography will also require high power and linenarrowed F2 laser sources, super high NA optics,

etc. Furthermore high absorption in air at 157 nm forces the use of dry nitrogen or inert gas atmospheres in order to remove any oxygen content out of the optical path by purging. The prospects of 126 nm lithography are more remote. The Ar2 sources are too weak and not reliable for a practical system. Fig. 1 describes the expected roadmap for optical lithography in the next few years [4]. The evolution of the Rayleigh k1 factor is also presented. The k1 factor is a useful measurement of the diculty of printing a particular feature. When k1 > 0:8, the printing process is relatively easy. As k1 shrinks, the imaging process becomes less tolerant to any imperfections and process windows decay. When k1 < 0:5, it becomes necessary to use RET approaches. When k1 6 0:25 printing pattern is nearly impossible. 2.2. Next generation lithography Electron beam direct write (EBDW) uses a Gaussian electron beam to directly write patterns in a chip. EBDW is a mask-less approach and is attractive for industry whose business depends on a lot of mask usage. As EBDW exhibits a very high resolution, it is frequently used to pattern ultrasmall CMOS transistor in order to study their ultimate performance. Nevertheless its throughput is very low which considerably limits its production capability. To overcome this issue EBDW can

Fig. 1. Lithography roadmap [4] (courtesy of ASML).

C. Wyon / Nucl. Instr. and Meth. in Phys. Res. B 186 (2002) 380±391

be mixed and matched with conventional DUV lithography. Scattering with angular limited projection e-beam lithography (SCALPEL) is also an electron-based lithography. It uses electron beam projection through a metal (W, Au, Cr, TaSiN, etc.) scattering mask, and so requires the use of very high speed, high accuracy vacuum stages. The key problems to be solved are ®eld stitching (multiple masks are needed to cover a single chip), mask integrity and cost. Proximity X-ray lithography system requires a synchrotron X-ray source and uses the X-ray beam through a 1 mask. The main barriers stand with the quality of the mask and the availability of compact and reliable synchrotron source. EUV lithography uses high energetic photons (11±13 nm) generated by a laser producing plasma discharge. It uses re¯ective optics with a 4 reTable 2 Front end processes ITRS roadmap (selected data [1])

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duction scheme. This system requires concave re¯ective lenses composed of a superlattice of approximately 40 layers of 2±3 nm ®lms (Mo±Si) with a local and global uniformity of atomic dimensions. Due to its best ®t with the current optical lithography technology base and due to its throughput (Table 1), EUV should be the NGL of choice even if EUV is not mature at this time (Fig. 1). 3. Gate stack The most stringent requirements for high performance, sub-100 nm CMOS technology are dictated by the PMOS transistor. High performance sub-100 nm transistors require both ultra thin gate dielectrics, i.e. tox < 2:5 nm, and ultra shallow, i.e. xj < 50 nm, junctions (Table 2) to

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Fig. 2. (a) Measured and simulated oxide tunnelling current versus gate voltage [5]. (b) Calculated gate voltage dependence of median time to breakdown [6] for various oxide thickness.

achieve a high saturation current with a low power supply voltage and to control short channel e€ects. The motivation for reducing the oxide thickness is an increase in capacitance which translates into increased drive current capability. Ultra thin gate oxides make a low voltage power supply practical and minimize active power dissipation. Concomitant with an increase in the gate capacitance are (1) a detrimental exponential increase in leakage current due to direct tunnelling of electrons (Fig. 2(a)), (2) a limitation of processing issues like poor wafer uniformity and oxide growth control, (3) boron di€usion from the p‡ -gate to the substrate which causes excessive and uncontrollable threshold voltage shifts and (4) insucient reliability (Fig. 2(b)). Although recent results pointed out that the apparent robust nature of SiO2 ultra thin ®lms can be achieved for thickness as low as 0.8 nm [7], the maximum tolerable gate leakage current …1±10 A cm 2 † induced by direct electron tunnelling will occur for gate silicon oxides in the range 1.3±1.5 nm (Fig. 2(a)). In addition to leakage current increasing with scaled oxide thickness, the issue of boron penetration through the oxide is a signi®cant concern. The large boron concentration gradient between the heavily p‡ -doped poly-Si gate electrode, the

undoped oxide and the lightly doped Si channel  causes boron to di€use rapidly through a sub-20 A oxide upon thermal annealing, which results in a higher concentration of boron in the channel region. A change in channel doping then causes a shift in threshold voltage, which clearly alters the intended device properties in an unacceptable way. The concerns regarding high leakage currents, boron penetration and reliability of ultrathin SiO2 have led to materials structures such as oxynitrides and oxide/nitride stacks for near-term gate dielectrics alternatives. These structures provide a slightly higher dielectric constant j than SiO2 (pure Si3 N4 has j # 7 compared to 3.9 for thermal SiO2 ) which reduces electron tunnelling by increasing the physical thickness of the gate dielectric (see Eq. (3)), reduces boron penetration due to the particular Si±O±N network bonding in oxynitride, and produces better reliability characteristics when small amounts of N (0.1 at.%) are present at or near the Si channel interface. Nevertheless large amounts of N near this interface degrade device performance due to excess charge and a high defect density at the Si channel interface. Despite these results scaling with oxynitrides/ nitrides appears to be limited to equivalent oxide thickness in the order of 1.3 nm.

C. Wyon / Nucl. Instr. and Meth. in Phys. Res. B 186 (2002) 380±391

3.1. Alternative high j dielectrics To reduce the leakage current while maintaining the same gate capacitance, a thicker ®lm with a higher dielectric constant j is required. The gate leakage current JDT is exponentially dependent upon the dielectric thickness (Eq. (3)), while the capacitance C is only linearly dependent on the thickness (Eq. (4)), 2 JDT ˆ …a=tdiel † expf 2tdiel ‰…2m q=h2 †

 …UB

Vdiel =2†Š

1=2

g;

…3†

C ˆ je0 A=tdiel ˆ jox e0 A=teox ;

…4†

where a is a constant, tdiel is the physical thickness of the gate dielectrics, Vdiel is the voltage drop across the dielectric, UB is the barrier height between the cathode and the conduction band of the dielectrics, m is the electron e€ective mass in the dielectrics, j is the dielectric constant of the dielectrics, jox is the dielectric constant of thermal silicon oxide …jox ˆ 3:9†; teox is the equivalent oxide thickness, e0 is the permittivity of free space …8:85  10 3 fF lm 1 † and A is the capacitor area. There is however another exponentially dependent term in the tunnelling current (Eq. (3)), i.e. the barrier height between the cathode and the conduction band of the insulator. Therefore, not only a material with higher dielectric constant is needed, but this material must also have a suitable

385

band gap, and barrier height to keep the gate leakage current within reasonable limits. Table 3 gathers some properties of alternative high j materials which are currently under investigation [8]. DEc =Si represents the barrier height between the top of the dielectrics band gap and the silicon conduction band. It is worth noting that the barrier height between Ta2 O5 , TiO2 and SrTiO3 and Si is not high enough to prevent any leakage gate current. High j materials have a tendency to degrade short-channel performance by the fringing ®elds from the gate to the source/drain regions. So high j materials with j higher than 50, like SrTiO3 , BaSrTiO3 , etc. are not recommended for CMOS gate materials [10,11]. Other properties are also required in order to select an alternative gate dielectric: (1) ®lm morphology, (2) thermodynamic stability, (3) interface quality, (4) compatibility with the current and expected materials to be used in processing for CMOS devices, (5) process compatibility and (6) reliability. As grain boundaries could serve as high leakage paths, polycrystalline gate dielectrics may be problematic unless an ultra-thin amorphous at the gate dielectrics/Si interface is used to reduce leakage current. So amorphous or single crystal layers (epilayers) are usually preferred. The gate dielectric morphology must be stable during all the

Table 3 Some properties of alternative high k materials Material j Band gap (eV) DEc =Si…eV† Notice Material

Si3 N4

Ta2 O5

TiO2

Al2 O3

Zr±Al±Si±O ZrO2

ZrO2 : Y2 O3

HfO2

ZrSiO4

HfSiO4

3.9 8.9

7 5.1

26 4.5

80 3.5

9 8.7

3±29

29.7

18±40 5.7

12.6 6

13 6

3.3

2

1±1:5

1.2

2.8a

CeO2

Pr2 O3

Gd2 O3

Y2 O3

SrTiO3

PbTiO3

PbZrO3

26±16:6 14.9

13.6

15±18 5.6

150±250 3.3

1000 3.4

3.7

Epi.

Epi.

1.3a Epi.

)0.1a Epi.

SiO2

La2 O3

j 30 Band gap 4.3 (eV) DEc =Si…eV† 2.3 Notice

25 7.8 1.4a

DEc =Si …eV†: energy o€set between the dielectric and silicon conduction bands. a Calculated by Robertson [9].

Epitaxy

1.5a

1.5a

CoTiO3

BaSrTiO3

LaAlO3

40±45

300

25.1

)0.1

386

C. Wyon / Nucl. Instr. and Meth. in Phys. Res. B 186 (2002) 380±391

thermal process steps following the gate dielectric deposition, especially during the ion implantation activation anneals (typically 1000 °C, 15 s). For all thin gate dielectrics, the interface with Si plays a key role and will determine the electrical properties of the CMOS device. The gate dielectrics/Si interface has to exhibit extremely high quality (midgap interface state density Dit # 1011 ± 1012 cm 2 , and ®xed charge density) as close as possible as the SiO2 =Si interface (Dit # 2  1010 cm 2 ), which is the main reason for the excellent performance of CMOS devices. Unfortunately most of the high j metal±oxides systems investigated thus far (Table 3) have unstable interface with Si: they react with Si under equilibrium conditions to form an undesirable interfacial layer. An investigation of the M±Si±O; (M ˆ Ta, Ti) ternary phase diagrams have shown that Ta2 O5 and TiO2 on Si tend to phase separate into SiO2 and metal±oxides and, possibly, silicide phases. The SiO2 interfacial layer is quite interesting to preserve the excellent quality of the Si=SiO2 interface but will be detrimental to preserve a high gate capacitance. Ultra-thin silicon nitride or oxynitride are sometimes deposited before the deposition of Ta2 O5 and TiO2 in order to prevent the formation of the SiO2 interfacial layer. In contrast to the Ta and Ti systems the Zr±Si± O phase diagram indicates that ZrO2 and ZrSiO4 will both be stable on Si up to high temperatures. The Hf±Si±O phase diagram has not been completely investigated, but due to the chemical analogy between Zr and Hf, HfO2 and HfSiO4 are also expected to be stable on Si. Due to their high dielectric constant, their barrier height with Si, their thermal and chemical stability with Si, Zr and Hf based dielectrics like ZrO2 ; ZrSiO4 ; HfO2 and HfSiO4 are currently the best candidates for alternative high j materials, despite the fact the amorphous structure is not

always thermally stable which leads to polycrystalline ®lms. Epitaxial ZrO2 ±Y2 O3 layers are also quite attractive because their single crystal morphology is thermally stable. Al2 O3 ®lms are amorphous and thermally stable, but their dielectric constant j is probably too low to replace SiO2 for advanced CMOS devices. 3.2. Metal gates Another quite important issue for integrating any advanced gate dielectric into CMOS standard device is that the dielectrics should be compatible with Si-based gates, rather than require a metal gate. Si-based gates are desirable because doping implant conditions can be tuned to create the desired threshold voltage Vt for both nMOS and pMOS. Nevertheless nearly all the investigated high j dielectric materials require metal gates. Si-based gates major drawback is represented by gate poly-depletion e€ect. As the operating bias is not scaled down at the same rate than the dielectric thickness, the average surface ®eld has increased. Combining this with a reduction of the e€ective poly-silicon depletion leads to a substantial poly-depletion e€ect which is equivalent to an increase in the gate dielectric thickness, and thus to a decrease in gate capacitance which induces degradation of the CMOS performances. Metal gates remove the poly-depletion problem but require compensation implants to obtain an optimal threshold voltage Vt for both nMOS and pMOS since the work function of the metal is located near silicon midgap. As buried channel is needed to ensure low Vt with metallic gate, it induces a buried channel depletion capacitance which leads to relaxed short channel e€ect in a similar way as for poly-depletion [12]. A ®rst approach is to use a single midgap work function (#4.6 eV) material which produces sym-

Table 4 Work function of gate electrodes from MOS system Gate material Work function (eV)

Ti 4:2±4:6

TiN 4.95

TiSi2 3:67±4:25

Ta 4:15±4:6

Gate material Work function (eV)

WNx 5

WSi2 4:55±4:8

Mo 4.6

MoN 5.33

MoSi2 4:6±4:9

TaN 4.15

TaSi2 4.15

W 4:55±4:75

Al 4.1

RuO2 5

IrO2 5

C. Wyon / Nucl. Instr. and Meth. in Phys. Res. B 186 (2002) 380±391

metric Vt for nMOS and pMOS with similar channel doping. Vt is usually too high for bulk-Si CMOS, but optimum Vt can be achieved with lower channel doping in fully depleted silicon on insulator (FDSOI) substrates by using mid-gap metal gate. Another approach is to use two di€erent metal gates for nMOS and pMOS with work function close to 4.1 eV (Work function for n‡ -doped silicon) and 5.2 eV (Work function for p‡ -doped silicon). Numerous candidates are available (Table 4). Integrating metal gates in CMOS device could face serious challenges. Conventional gate integration [13], involves etching of the gate material and the ability of the gate material to be stable during high temperature steps. This could limit the choice of materials for metal gate. Damascene gate or dummy gate appears to show more promise in this regard but not with added process complexity [14]. 4. Source/drain engineering The advancing miniaturisation of CMOS devices puts increasingly demands on the distribution of dopants in the active area. New technologies are needed to dope highly doped and highly abrupt ultra-shallow junctions (Table 2). Ultra-low thermal budgets are required to limit dopant di€usion, especially boron di€usion for pMOS, at the expense of activating dopants and process damage removal.

387

Ion implantation is currently the most widely used method for semiconductor doping, since the distribution doping pro®le can be readily controlled. Unfortunately introducing dopants by implantation inevitably induces transient enhanced di€usion (TED) due to the excess interstitials from the implant. The number of excess interstitials, and thus, TED is assumed to be approximately equal to the implantation dose (the ``plus one'' approximation). TED is expected to be reduced by decreasing the implantation energy, thus placing the doping ions and the implantation excess interstitials closer to the surface which is a sink for interstitials and for which the plus one approximation is no longer available due to the small amount of Frenkel pairs for this energy regime. Consequently ultra-low energy implantation is pursued for ultra-shallow junctions. Unfortunately reducing ion implantation energy too much leads to the sputtering of target material during ion implantation (self-sputtering) which can induce a 20% dose loss at 0.2 keV. So ultra low energy ion implantation will probably be limited to energies higher than 0.5 keV. Furthermore for subkeV boron implants di€usion remains enhanced limiting junction depths to 100 nm following 1050 °C, 10 s annealing. This enhancement is called boron enhanced di€usion (BED) and is correlated to the presence of silicon boride phase …SiB4 † when the boron concentration exceeds 6% [14]. Plasma doping (PLAD) uses negative bias pulses applied on the wafer to accelerate positively charged doping species from a plasma containing

Fig. 3. As implanted (a) and annealed (b) junction pro®les using I.I. and PLAD [18].

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C. Wyon / Nucl. Instr. and Meth. in Phys. Res. B 186 (2002) 380±391

these ions directly into the wafer surface. The primary advantage of this technique is the potential high throughput. PLAD using BF3 and B2 H6 has been compared with B and BF2 ion implanted samples. PLAD seems to improve junction depth (Fig. 3) and sheet resistance but does not prevent TED or BED [15,19]. Implantation using decaborane (B10 H14 ) molecular beams has been used to fabricate shallow junctions for 50 nm pMOS devices. Decaborane is 124 times heavier than B and so leads to less TED and higher dopant activation [16]. Atomic layer doping is performed by exposing the silicon surface to a source gas (AsH3 ; B2 H6 , Sb MBE) to form a dopant-adsorbed layer. A capping oxide layer is deposited to protect the adsorbed layer from the following processes, then junctions are formed by rapid thermal annealing (RTA) [17]. This technique, which requires ultra high vacuum method and hard masks, leads to shallower junctions than low energy implantation, but the maximum doping dose is limited by adsorption phenomena (6:8  1014 cm 2 for As). A promising technique for formation of ultrashallow junctions is gas immersion laser doping (GILD) which uses a combination of a large area pulsed excimer laser, a laser light re¯ecting mask and a dopant gas ambient at the wafer surface [18].

The laser pulse melts the surface of the exposed light absorbing Si regions allowing dopants to be incorporated in the melt layer. Rapid di€usion of dopants in the melt results in an abrupt, uniformly doped junction whose depth is determined by the melt depth. In order to reduce TED during post-implantation annealing the thermal budgets of the subsequent annealing has to be reduced. Several approaches are currently investigated to improve RTA performances: Spike anneal, laser annealing. Selective epitaxy is also used to realise elevated source/drain technology. Spike anneal technique consists in a ultra short anneal of the doped wafer using ramping up rate in the order of 250±300 °C s 1 , an in®nitesimal short time at peak temperature, and a ramping down at a rate around 80±100 °C s 1 . Spike anneal has a tendency to reduce TED (Fig. 4(a)). Laser annealing is equivalent of the GILD technique. It uses a excimer laser to melt the implanted layer. Since the di€usivity of boron in the liquid phase is about eight orders of magnitude higher than in the solid state, boron atoms become uniformly redistributed within the melt depth, thus forming a abrupt junction (Fig. 4(b)). Moreover, based on the fact that amorphous/damage layer has a lower melting point than crystalline Si, the

Fig. 4. In¯uence of a spike anneal (a) and laser annealing (b) on junction pro®les [19].

C. Wyon / Nucl. Instr. and Meth. in Phys. Res. B 186 (2002) 380±391

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portant as transistors in determining ULSI density and performance. Fig. 5 illustrates the gradual migration of the IC delay of critical paths from gates into wiring as the feature size is reduced [23]. In ULSI the time delay s is expressed as RC constant, where R is the line resistance and C is the line capacitance of the used structure, which can be approximately described by the relation s ˆ RC ˆ 2qje20 ‰…4L2 =P 2 † ‡ …L2 =T 2 †Š;

Fig. 5. IC delay as a function of the feature size (low j ˆ 2) [21].

preamorphised layer can be melted without melting the underlying Si [20]. As the annealing duration is in the order of nanoseconds, it is too short to induce any secondary defect formation to occur. Nevertheless laser annealing has major process integration issues: dopant deactivation, control of localised wafer surface melting especially on patterned device wafers, gate poly melting issues and compatibility for use with high j gate materials. The challenge of attaining ultra-shallow junctions with low sheet resistance Rs (Table 2) is greater for pMOS than for nMOS because of the lower solid solubility and higher di€usivity of B (as compared to As) in Si. As SiGe epilayers exhibit a higher solid solubility and di€usivity of dopants as compared to Si [21], they can be selectively deposited at low temperature (500±600 °C) in the source/drain regions in order to realise ultra-shallow junctions. Also, since enhanced activation is achieved in situ during the ®lm deposition, a subsequent junction activation anneal is precluded. The doping pro®le is easily controlled during the deposition (Fig. 5). Selective doped SiGe epitaxy could probably facilitate scaling of CMOS technology down to 100 nm and beyond [22]. 5. Interconnects When ICs are scaling down, wiring interconnects are now a signi®cant limiter and are as im-

…5†

where q is the metal resistivity, j the low dielectric constant of the insulator material, e0 the free space permittivity, L the line length, P the interconnect pitch and T the metal thickness. The time delay can be decreased by reducing the metal resistivity. This is currently performed by replacing AlCu …q ˆ 2:66 lX cm† wiring by copper connections …q ˆ 1:67 lX cm†. Moreover copper interconnections fabricated by a dual-damascene process o€er advantages of performance (high resistance to electromigration), cost and reliability over existing aluminium wiring processes. The time delay can also be reduced by minimizing the j value of the dielectric material. The use of low j dielectric materials present other bene®ts: reduced power and heat dissipation requirements and reduced interline cross-talk. Low j values are expected to decrease from 3 to 1.5 in the order of 10 years (Table 5). Many low j materials are investigating to be integrated with Cu interconnects. Fluorinated SiO2 (FSG; j ˆ 3:5±3:7) is the ®rst material which has been introduced, due to its compatibility with the conventional TEOS ILD. The dielectric constant of a matrix dielectric can be lowered by decreasing its density. This can be achieved by incorporating low molecular weight atoms (C and H atoms instead of Si and O atoms) and/or by adding more free volume to the structure. The development of low j materials is split between an organic spin-on dielectric and hybrid organic/inorganic silicate ®lms deposited by CVD or spin on processes. The silicates, like hydrogensilsesquioxanes (HSQ; j ˆ 3) siloxane based polymers, where the Si atoms are directly attached to O and H, and methylsilsesquioxane (MSQ; j ˆ 2:7), where a CH3 group bonds every Si atom, are

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Table 5 Back end processes ITRS roadmap (selected data [1])

extremely thermally stable, hard but fragile. On the opposite, organic materials like the highly aromatic bis(benzocyclobutenes) BCB and SiLKTM , have reasonable thermal stability, are tough but soft. In order to decrease its density, introduction of nanometer sizes pores into the material has been studied. The most widely used approach relies on the incorporation of a thermally degradable material (porogen) within a host thermosetting matrix. Upon heating, the matrix material cross-links and the porogen undergoes phase separation from the matrix to form nanoscopic domains. Subsequent heating leads to porogen decomposition and di€usion of the volatile by-products out of the matrix. To get high mechanical strength for the CMP step, pore sizes should be as small as possi-

ble. Nevertheless thermal conductivity decreases with porosity and use of highly porous low j materials may cause reliability issues. To be integrated in Damascene Cu interconnects a viable low j must exhibit a low water absorption, good chemical stability to lithography, etching and stripping processes, reasonable thermal stability ( 6 500 °C), an excellent compatibility with the required etch stop layers (SiNx ; SiCx , etc. which can strongly increase the e€ective dielectric constant of the layer) and the copper di€usion barrier (good adhesion to the CVD TaNx ; TiNx and Wx N, electroless Co:P and Ni:P) and a high planarisation capability (potential use of capping layers during CMP). Early integration of low j ®lms encountered an insidious problem of photoresist poisoning.

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6. Conclusions Scaling down the size of CMOS transistors require huge e€orts on research of new materials: high j thin ®lms, low j layers, on new technologies to realise ultra-shallow junctions, etc. No material and technology are readily available to satisfy the performances expected by the ITRS roadmap, but several promising solutions are under investigations, as reported in this paper. The developed materials and process modules also have to ful®l other criteria like cost, yield or reliability in order to provide a manufacturable CMOS process and to be accepted in production line. References [1] International Technology Roadmap for Semiconductors, 1999 edition. [2] D. Buss, International Eelectron Devices Meeting (IEDM) Tech. Digest (1999). [3] R. Chau, J. Kavalieros, B. Roberds et al., IEDM Tech. Digest (2000). [4] J. Systma, H. Van der Laan, M. Moers, in: Proceedings of the ULSI Characterization and Metrology, 2000, p. 339. [5] Y. Taur, E.J. Nowak, IEDM Tech. Digest (1997). [6] J.H. Stathis, D.J. DiMaria, IEDM Tech. Digest (1998) 167.

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