GaAs metal-oxide-semiconductor based nonvolatile memory devices embedded with ZnO quantum dots Souvik Kundu, Sankara Rao Gollu, Ramakant Sharma, Nripendra. N Halder, Pranab Biswas et al. Citation: J. Appl. Phys. 114, 084509 (2013); doi: 10.1063/1.4819404 View online: http://dx.doi.org/10.1063/1.4819404 View Table of Contents: http://jap.aip.org/resource/1/JAPIAU/v114/i8 Published by the AIP Publishing LLC.
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JOURNAL OF APPLIED PHYSICS 114, 084509 (2013)
GaAs metal-oxide-semiconductor based nonvolatile memory devices embedded with ZnO quantum dots Souvik Kundu,1,a) Sankara Rao Gollu,1 Ramakant Sharma,1 Nripendra. N Halder,2 Pranab Biswas,3 P. Banerji,3 and D. Gupta1,a)
1 Department of Metallurgical Engineering and Materials Science, Indian Institute of Technology, Bombay, Mumbai-400076, India 2 Advanced Technology Development Centre, Indian Institute of Technology, Kharagpur-721302, India 3 Materials Science Centre, Indian Institute of Technology, Kharagpur-721302, India
(Received 27 April 2013; accepted 12 August 2013; published online 30 August 2013) Ultrathin InP passivated GaAs non-volatile memory devices were fabricated with chemically synthesized 5 nm ZnO quantum dots embedded into ZrO2 high-k oxide matrix deposited through metal organic chemical vapor deposition. In these memory devices, the memory window was found to be 6.10 V and the obtained charge loss was only 15.20% after 105 s. The superior retention characteristics and a wide memory window are achieved due to presence of ZnO quantum dots between tunneling and control oxide layers. Room temperature Coulomb blockade effect was found in these devices and it was ascertained to be the main reason for low leakage. Electronic band diagram with program and erase operations were described on the basis of electrical C 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4819404] characterizations. V I. INTRODUCTION
Metal-oxide-semiconductor (MOS) devices based on silicon have been in use in memory technology since a long time and it is believed that in next generation, GaAs MOS will play a dominant role in non-volatile memory (NVM) application due to its high speed performance and low power dissipation.1–4 In this era of electronic gadgets, NVM devices are the most interesting research topic having the largest commercial share in the electronic industry since all modern electronic devices, viz., microprocessor based systems, digital cameras, notepads, USB ports, portable medical diagnostic systems, mobile phone, etc., are having NVM as a component in them. A NVM device should have the characteristics of high retention time, low power consumption, and could be electrically programmed and erased in the system itself.5 The use of low dimensional structures such as nano crystals,6 quantum dots (QDs),7 nano tubes,8 and nano needles9 as charge storing elements in MOS based non-volatile flash memory devices made it possible to replace conventional poly-silicon floating gate memory. Additionally, the memory devices are less prone to charge leakage when the low dimensional structures such as metallic nanoparticles (NPs) or QDs are employed, which allow low voltage operation and thus alleviates heat dissipation problem due to low power consumption. As an alternative, the thickness of the dielectric and the device dimension could also be decreased down to nano domain range for reliable operation and for increase in the storage density.10,11 Although GaAs MOS based NVM devices demonstrate several advantages, such as high speed of operation, low power dissipation, etc., over conventional Si based devices, there are only few reports available where metallic nanoparticles were used as the charge storing materials.1–4 In our earlier report, we have mentioned a)
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the problems associated with the metallic nanoparticles and also suggested need of replacing metallic nanoparticles by QDs as charge storing elements.4 On one hand, forming nanoparticles require high temperature thermal treatment, which is not favorable for GaAs based devices due to the chances of As evaporation at high temperature.3 Whereas at low temperature, embedding of charge storing materials in GaAs based systems is also a challenging task. For NVM devices, the commonly used charge storing semiconducting QDs are InP,4 SiGe,7 Ge,10 Si,11 and ZnO.12,13 Among these materials, ZnO can be the emerging choice for GaAs NVM devices because it can be processed at low temperature as compared to other materials and also the availability of its atomic defects which introduces trapping centre for electrons.12 High interface trap density (Dit) and Fermi level pinning at the dielectric/GaAs interface are major obstacles for developing high quality GaAs NVM devices.2–4,14 By doing proper surface treatment, the Fermi level pinning can be suppressed and a stable and passivated interface of dielectric/ GaAs can be achieved. Unfortunately, only sulfur passivated GaAs MOS based NVM devices are available in the literature,2–4 though prior to deposition of high-k dielectric, a large number of passivations techniques have been attempted to reduce the surface states of GaAs surfaces.15–17 Sulfur passivation can lead to inhomogeneous interfacial layers as a monolayer of sulfur atoms can be oxidized in air during device processing. Hence, GaAs based devices with sulfur passivation have high leakage current and interface trap density, with a deterioration in the device performance over time.14,18 Thus, sulfur passivation is not satisfactory and hence another stable passivation method is definitely required to fabricate high performance memory devices onto GaAs platform. Surprisingly, till now, no group has attempted to fabricate high performance GaAs memory devices with different passivation techniques. Previously, we have shown that passivation with an ultrathin InP layer
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reduces surface recombination density and surface band bending in GaAs surfaces.14 Further, aging time has no bearing on ultrathin InP passivation, as a result, good electrical and interfacial properties were obtained.14,19,20 Thus, in this present investigation, for the first time, we report ultrathin InP passivated GaAs NVM devices embedding with low temperature processed ZnO QDs. ZnO QDs were embedded in between tunneling and control layer of high-k ZrO2. The aim for this work is to achieve good retention property, low leakage current, and large memory window. Therefore, in details, we have investigated the charging, discharging, and retention properties of such devices. We also propose the energy band diagram of such devices with writing and erasing process on the basis of the results of the capacitance-voltage (C-V) characteristics. II. EXPERIMENT
p-GaAs (100) substrates with a doping concentration of 1 1016 cm3 were degreased by trichloroethylene, followed by boiling successively with acetone and methanol, and finally rinsing in deionized (DI) water. Then, the substrates were subjected to etch in a solution of H2O2–NH4OH–H2O in the ratio of 1:1:2 to remove native oxide and elemental As. They were again rinsed in DI water and finally dried by N2 gun. ZnO quantum dots were chemically synthesized and the preparation method was explained elsewhere.12 Ultrathin InP passivation on GaAs substrates was done by metal organic chemical vapor deposition (MOCVD) system. High-k dielectric, ZrO2 was used for both tunneling and control oxide layers, and the tunneling layer was first grown by MOCVD technique onto InP passivated GaAs surfaces. The details of InP and ZrO2 growth procedures can be found in our earlier works.4,14 Then ZnO QDs were embedded on tunneling ZrO2 and later ZrO2 control oxide layer was grown on it like tunneling oxide layer. The Al gate electrode having area 1.96 103 cm2 and low resistance Pd-Ag ohmic contact on the backside of GaAs were formed by thermal evaporation technique. It was followed by annealing at 300 C for 5 min in argon ambience. The thickness of each layer was measure by a Gaertner ellipsometer (model L-117). The thickness for InP, tunneling, and control oxide layers were measured to be 1.5, 5, and 15 nm, respectively. The quantum dots onto tunneling oxides layer were characterized by atomic force microscope (AFM, Veeco Multimode Nanoscope IV Scanning Probe Microscope), high resolution transmission electron microscope (HRTEM, Jeol Jem 2100 F), x-ray photoelectron spectroscopy (XPS, Vacuum Science Workshop Scientific Instruments Ltd., UK), and photoluminescence (PL, Varian Carry Eclipse) measurements. The electrical properties of the memory devices were recorded using a Keithley semiconductor parameter analyzer (4200-SCS).
J. Appl. Phys. 114, 084509 (2013)
FIG. 1. (a) Schematic of a GaAs NVM device with ZnO QDs embedded between tunneling and control oxide layer, and (b) energy band diagram of Al/ZrO2/ZnO QDs/ZrO2/p-GaAs memory devices.
using ultrathin layer of InP. The typical band diagram of such device is shown in Fig. 1(b). A quantum well is formed between tunneling and control layers where the charges can be trapped. The performance of the NVM devices depends on both size and shape of the quantum dots and their crystal orientation, which will influence the quantum confinement and Coulomb blockade effect. Therefore, AFM and HRTEM studies were carried out to examine the structure of ZnO QDs and their crystallinity onto tunneling layer. Both AFM and HRTEM image confirm the formation of ZnO QDs. Figure 2(a) shows the AFM image of ZnO QDs onto tunneling high-k layer. From this image, it was seen that the dots are homogenously distributed over the surface of tunneling ZrO2 layer. The HRTEM image of ZnO QDs is shown in inset of Fig. 2(a). From this image, the shape of the dots was found to be circular in shape and the average dot diameter was determined to be 5 nm. Fig. 2(b) shows the selected area diffraction pattern (SAED) for a single ZnO QD. Seven diffuse diffraction rings are shown in the SAED pattern of the ZnO QDs. The (100), (002), (101), (102), (110), (103), and (112) planes are indexed in the SAED pattern which depict the highly crystalline nature of ZnO QDs. The inter-planar spacing of a single ZnO QD was found to be 0.20 nm
III. RESULTS AND DISCUSSION
The schematic of GaAs MOS based non-volatile memory devices is shown in Fig. 1(a), where ZnO QDs were embedded in between tunneling and control ZrO2 layer. Prior to deposition of tunneling ZrO2, GaAs was passivated
FIG. 2. (a) AFM and HRTEM (inset) images of ZnO QDs onto tunneling oxide layer. A homogenous array of dots was obtained. (b) SAED pattern of ZnO QDs, and (c) HRTEM image of a single ZnO QD which confirms wurtzite structure.
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(Fig. 2(c)), which corresponds to the plane (002) of the wurtzite ZnO.21,22 To understand the chemical nature of ZnO QDs, we have performed XPS measurements. Fig. 3(a) shows the Zn 2 p spectrum which confirms the presence of ZnO QDs. Two peaks located at 1024.20 eV and 1046.80 eV correspond to the Zn 2p3/2 and Zn 2p1/2, respectively. Hence, the spin orbital splitting for the ZnO QDs was found to be 22.60 eV. Formation of ZnO was again confirmed with the O1s spectrum at 532.5 eV. According to the very small dimension of the dots, the charge carrier confined strongly within the QDs. The Bohr exciton radius (aex ) can be given by aex ¼ aHlemo , r where aH is the Bohr exciton radius for H2 atoms and its value is 0.053 nm, e is the free space permittivity and its value is 8.85 1012 F m1, lr is the reduced mass of the charge carrier and is given by l1 ¼ m1e þ m1h , me and mh are the effective r mass of the hole and electron in ZnO having values 0.29 m0 and 1.21 m0 , respectively, m0 is the mass of the electrons having value 9.1 x1031 kg.23 Bohr exciton radius was calculated to be 17.42 nm for ZnO ODs. We have assumed the charge carrier confined in a three dimensional quantum box and the states of energies of the free carriers will be split according to the relation En ¼
2 K 2 h 2lr
nx 2 Lx 2
þ
ny 2 Ly 2
þ
nz 2 Lz 2
E0 ¼
h2 2m
1=3
9 PqFGaAs 8
2=3 ;
(1)
where m* is the electron effective mass in GaAs substrate, É is the reduced plank’s constant and FGaAs is the field in GaAs substrate. Using WKB approximation, the tunneling probability can be written as24 DðE0 Þ ¼ ½Sin2 h2 Cosh2 ðh3 h1 Þ þ Cos2 h2 Cosh2 ½h3 þ h1 þ lnð4Þ1 ; and hi can be written as ð 1 xi ½2m ½VðxÞ Eg 1=2 dx; hi ¼ h xi1
(2)
(3)
where V(x) is the potential energy which can be represented as VðxÞ ¼ qFGaAs x;
x
