Letter pubs.acs.org/NanoLett
InAs Nanowires Grown by Metal−Organic Vapor-Phase Epitaxy (MOVPE) Employing PS/PMMA Diblock Copolymer Nanopatterning Yinggang Huang,† Tae Wan Kim,† Shisheng Xiong,‡ Luke J. Mawst,*,† Thomas F. Kuech,‡ Paul F. Nealey,‡ Yushuai Dai,§ Zihao Wang,§ Wei Guo,§ David Forbes,§ Seth M. Hubbard,§ and Michael Nesnidal∥ †
Department of Electrical and Computer Engineering, University of WisconsinMadison, 1415 Engineering Drive, Madison, Wisconsin 53706, United States ‡ Department of Chemical and Biological Engineering, University of WisconsinMadison, 1415 Engineering Drive, Madison, Wisconsin 53706, United States § NanoPower Research Labs, Rochester Institute of Technology, 156 Lomb Memorial Drive, Rochester, New York 14623, United States ∥ Firefly Technologies, 2082 Hackberry Lane, Shakopee, Minnesota 55379, United States ABSTRACT: Dense arrays of indium arsenide (InAs) nanowire materials have been grown by selective-area metal−organic vapor-phase epitaxy (SA-MOVPE) using polystyrene-b-poly(methyl methacrylate) (PS/PMMA) diblock copolymer (DBC) nanopatterning technique, which is a catalyst-free approach. Nanoscale openings were defined in a thin (∼10 nm) SiNx layer deposited on a (111)B-oriented GaAs substrate using the DBC process and CF4 reactive ion etching (RIE), which served as a hard mask for the nanowire growth. InAs nanowires with diameters down to ∼20 nm and micrometer-scale lengths were achieved with a density of ∼5 × 1010 cm2. The nanowire structures were characterized by scanning electron microscopy and transmission electron microscopy, which indicate twin defects in a primary zincblende crystal structure and the absence of threading dislocation within the imaged regions. KEYWORDS: Nanostructures, selective-area growth, MOVPE, nanowires, semiconducting III−V materials, solar cells
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utilized in the formation of large-scale parallel and aligned arrays of silicon NWs.8 Diblock copolymer lithography has also been utilized for the formation of semiconductor quantum dots9 and arrays of Au nanoparticles.10 Nanowires with a small diameter and relatively defect-free microstructures can now be synthesized by a variety of methods. On GaAs, (111)B-oriented substrates are generally used for nanowire growth, since this surface choice results in the nanowires aligning perpendicular to the substrate surface. In the Au-catalyzed VLS growth technique, the nanowires will incorporate some Au from the Au-containing liquid droplet. The Au solute introduces a known deep level state, which drastically reduces the minority carrier lifetime within the nanowire and impacts the optical performance of the material in applications such as solar cells. An alternative approach to nanowire formation is liquid-free selective-area metal−organic vapor-phase epitaxy (SA-MOVPE), which eliminates the metalinduced deep levels. SA-MOVPE results in flat-top nanowire
nterest in semiconductor nanowires has been growing tremendously over the past 10 years, as the size of fieldeffect transistors (FETs) has reached tens of nanometers and approaches the quantum region. Nanowires have attracted interest as new components for nanoscale electronic and photonic applications because of their inherent one-dimensional transport and two-dimensional quantum confinement effects. Devices based on nanowires have been proposed and demonstrated within logic circuits,1 nanoscale photodetectors,2 solar cells,3 and light-emitting diodes (LEDs).4 Catalyst-assisted growth, in which a nanoparticle on the growth surface is used to catalyze nanowire growth, is a widely used method to fabricate III−V group nanowires. Au nanoparticles are used which form a eutectic solution with the growth constituents. The catalyzed nanowire growth proceeds through the vapor−liquid−solid-phase (VLS) growth mechanism.5 Wagner and Ellis initially reported the VLS growth of Si whiskers using Au as a catalyst6 in 1964. Selfassembly and patterned growth methods of nanowire fabrication were reviewed by Zacharias et al., and nanowire formation employing block copolymer nanopatterning was first proposed.7 PS-b-PMMA block copolymer nanopatterning was © 2013 American Chemical Society
Received: August 23, 2013 Revised: November 16, 2013 Published: November 25, 2013 5979
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Figure 1. Schematic view of process flow for InAs nanowire formation using DBC lithography and SA-MOVPE growth.
growth as well as provides greater flexibility in nanowire placement and a broader range of growth conditions.11−13 In SA-MOVPE, the substrate is initially coated with a thin dielectric which subsequently is patterned to create openings to the substrate. The patterned substrate confines the nucleation of the epitaxial growth to the opening in the mask and ultimately serves to define the diameter of the growing nanowires. The most common method to form the nanowire template is through electron beam lithographic patterning of a “hard mask”, such as SiNx or SiO2. The pattern formed in the resist is easily transferred to the hard mask through a wet chemical etching process such as buffered hydrofluoric acid etch. However, typically the openings in hard masks defined using this method have diameters in the range of 50−200 nm. The diameter of the mask opening is a sensitive function of electron beam dose and the transfer process, particularly at the smallest opening size.11,12 Nanosphere lithography has also been used as a low-cost wafer-scale nanopatterning technique suitable for the SA-MOVPE growth of GaAs nanowires.13 A polystyrene/ polymethyl methacrylate (PS-b-PMMA) diblock copolymer (DBC) patterning technique is used here for the formation of dense InAs nanowires. This patterning technique is a low-cost and large-area (full) wafer process employing a simple spincoating and annealing process. It can be used to create mask pattern openings with diameters in the range of ∼20 nm at a high density (5−10 × 1010 cm2) with a narrow size distribution. Experimental Procedure. The DBC nanolithography process employed mimicked that used previously for selectively grown quantum dots in (100) GaAs and is described in ref 9. A schematic view of the entire nanowire fabrication process employed is shown in Figure 1. Briefly, a 10 nm thick SiNx layer is deposited on a (111)B GaAs substrate using plasmaenhanced chemical vapor deposition (PECVD). This SiNxcoated sample is annealed under AsH3, with hydrogen as a carrier gas, at 600 °C in order to densify the dielectric mask and to relieve thermal expansion-induced stresses that could cause cracking and delamination of the nanopatterned mask during the MOVPE growth.14 The 10 nm SiNx layer/GaAs substrate was coated first with a “brush” material9,15 and then with a 1% (w/w) toluene solution of the cylinder-forming PS-b-PMMA DBC (MW: 46 kg/mol for PS and 21 kg/mol for PMMA, polydispersion index of 1.09) by spin-coating. Upon annealing at 190 °C under vacuum, the brush layer directs the PMMA
segment of the DBC to segregate into a close-packed array of cylinders embedded in a PS matrix and oriented such that the long axis of each cylinder is parallel to the substrate normal. After self-assembly, the PMMA cylinders were removed through exposure to UV radiation, which preferentially degrades the PMMA component allowing its removal in acetic acid to produce nanosized holes in the PS. A plasma-based reactive ion (RIE) etching technique using CF4 was employed to transfer the pattern of holes into the SiN layer. A fixed recipe of CF4 dry etch was used consistently, that is, 10 sccm of CF4 gas was flowing with the pressure of 10 mTorr and the power of 100 W. The process is stated as follows: first 50 W of 10 sccm O2 plasma with 10 mTorr was used to etch away 6 nm of polymeric brush layer9 from within the cylindrical openings; then the CF4-based plasma gas was introduced, etching the exposed dielectric layer and accomplishing the pattern transfer. The remaining PS was completely removed by an O2 plasma (40 sccm, 100 mTorr, 150 W using a Unaxis 790 RIE etcher). A short wet etch of the exposed semiconductor in the openings using acetic acid was employed to remove any plasma-induced damage16 from the GaAs surface. This etching process consisted of an initial dip into 10% (volume) acetic acid for 20 s and then 1:1:8 (volume ratio) of HCl:CH3COOH:H2O for 20 s.17,18 The nanowire growth was carried out in a vertical chamber MOVPE (3 × 2) reactor with a close-coupled showerhead (CCS) gas delivery system. The InAs nanowire growth conditions were similar to those reported in ref 19. The reactor working pressure was set to 100 Torr. The partial pressures for TMIn and AsH3 were 3.7 × 10−7 Torr and 9.9 × 10−2 Torr, respectively. The growth temperature was initially ramped up to 600 °C under a flow of AsH3 which removes any native oxide from the exposed GaAs within the nanopatterned openings in the SiNx. The patterned substrate was then cooled down to 550 °C where upon InAs nanowire growth was initiated. The NW size, morphology, and microstructure were characterized by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Results and Discussion. Characterization of Nanopatterned Dielectric Mask and Nanowires. SEM characterization of the nanopatterned substrates was used to initially assess the integrity of the pattern transfer. Figure 2 presents an SEM image of the patterned SiNx mask after the polymer was completely removed. This specific sample was produced by a 35 5980
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etching times as determined from SEM micrographs. Samples prepared using an RIE etch time of 35 s yielded the highest nanowire growth density. Etching times less than or equal to 28 s resulted in little or no nanowire growth. Etch times greater or equal to 40 s lead to a drop in nanowire density. This drop is presumably due to the contamination of the nanopattern openings during the long etching process. Further increasing the etching time leads to complete removal of the nanopatterned mask. This optimal etching time was observed to drift between subsequent process runs indicative of the process sensitivity of the pattern transfer and the stability of the RIE tool employed in this study. These etch times are therefore system-specific. Structural Characterization of Nanowires. High-density nanowires were achieved from selected samples in which a large fraction of holes were fully open in the dielectric mask. The optimal CF4 etching time was determined for this specific process run, due to the sensitivity of the transfer process to variations of the RIE tool. Figure 4a,b presents plane-view and
Figure 2. Top-view SEM image after pattern transfer from polymer to SiNx hard mask. The polymer was removed in this image.
s pattern transfer CF4 RIE etch. The status of the holes, as to whether they are completely opened down to the GaAs substrate, cannot be determined from these images. Therefore, we employed a variation of the CF4 etching time, followed by nanowire growth, to optimize the RIE mask etch step to ensure the nanosize holes are fully opened. The sparse dark regions in these micrographs (Figure 2) are believed to be areas corresponding to defects in the initial polymer mask or in the pattern transfer process. Most likely these areas are regions where the SiNx mask was excessively etched and undercut the nanopattern. Such defects can be eliminated through improvements in the DBC and dry etching pattern transfer process. InAs nanowire growth was carried out for eight samples which had been etched using CF4-based plasma at different plasma etch times which ranged from 19 to 40 s. This spread in etch times was employed to ensure that there was sufficient etching required for pattern transfer and subsequent exposure of the substrate within the openings. Too short of an etch leads to partial opening of the pattern holes, while overetching leads to a damaged pattern or pattern removal. The density and uniformity of the nanowires was also used as an indicator of successful pattern transfer. Figure 3 shows how the fraction of open holes where nanowire growth occurs changes with CF4
Figure 4. (a) Top view and (b) cross-sectional SEM micrographs showing a high density of nanowires. The pattern was transferred using a 25 s CF4 etch.
cross-sectional SEM images, respectively, for a sample containing a high density of InAs nanowires. There are several notable features in these micrographs. There appear to be regions where there was rapid lateral growth noted by large islands in Figure 4a. Note that, in Figure 4a, the sharp contrast difference among nanowires in the top-down image is attributed to the variation in the NW length. However, quantification of the length variations can only be discerned from the cross-sectional view of Figure 4b. These islands may consist of adjacent merged nanowires due, perhaps, to the merging of adjacent pattern openings. Additionally these large islands could result from a degradation of the mask during the growth itself which may be ameliorated by the use of a thicker dielectric mask. There are also areas of no growth. We believe
Figure 3. Measured fraction of open holes versus CF4 etching time as determined by the presence of nanowire growth. 5981
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the absence of localized nanowire growth is associated with the aforementioned defects in the initial pattern due to incomplete pattern transfer. The sample in Figure 4 was etched using CF4 for 25 s. The length of the nanowires is ∼2.2 μm for a growth time of 900 s. There is a substantial variation in the nanowire length, as shown in Figure 4b. Such local variation in length is also seen in high-density VLS growth and is a function of the complicated reaction−diffusion process characterizing the nanowire growth. The minor statistical variations in the initial length could become enhanced with growth due to the narrow interwire diffusion pathways as well as the complicated, orientation- and diameter-dependent growth rate. The variation in heights of the nanowires can be attributed to several effects. If the initial openings within the mask are not uniform, the initial growth of the nanowire will take place at different rates. Given the small internanowire spacing, all openings are communicating with each other due to the large diffusion length of the In on the masking material. Initial stages of growth will initiate on those areas which are exposed to the incoming flux as well as strain relaxed. Once a phase is formed on the surface, the tendency for In atoms arriving at the surface would be to attach to any initially available site or nucleated island. This will give a preference to the initial growth of nanowires within openings that are larger and free of native oxide as well as any residual masking material. Any initial perturbation in growth can be exacerbated by the nature of the growth process. Nutrients will more readily travel to those wires which are higher as they protrude further into the nutrient-rich environment. Such reaction−diffusion models which build upon perturbations are well-known in the crystal growth literature. It is difficult at this point to have a quantitative model which correlates the very initial stages of growth to final wire length. This is in part due to our inability to quantify the available substrate area within an opening in the presence of possible masking materials and opening variation. Further uniformity in the nanowire lengths can perhaps be achieved with improved control over the critical dry etching pattern transfer process to the nitride mask. We also anticipate that the use of a thicker SiNx layer and thicker DBC film will help reduce mask defects as well as improve the uniformity of the nanohole sizes. Based on analysis of the image presented in Figure 4b, the average nanowire length observed here is 2.2 ± 0.8 μm. Nanowires formed by the VLS growth mode have been reported with similar length variations of 2.2 ± 0.4 μm.20 The cross section of the nanowires is hexagonal, as evident in Figure 4a, bounded by 6 {110} facets perpendicular to (111)B plane. The DBC patterned SA process is capable of generating an extremely small diameter (∼25 nm as determined from TEM images) InAs nanowires with a high aspect ratio (at times >100) by MOVPE. The defect and structural properties of the InAs nanowires were analyzed by transmission electron microscopy (TEM) using an FEI Tecnai F20 high resolution transmission electron microscope (HRTEM) operated at 200 kV. Cross-section samples for TEM were prepared using two face-to-face bonded cleaved pieces of the wafer. A coarse cross-section lamella was cut from the center of the NW bundle and transferred to a tripod grinder before ion-milling. The lamella was sliced into thin sections using a Gatan 691 Precision Ion Polishing System (PIPS) Ar-ion-milling technique. All measurements and fast Fourier transform (FFT) were performed by Image J software.21
Low-resolution TEM images of Figure 4 indicate that the nanowires have a tight diameter distribution with nanowires that range in length from 1 to 3 μm. To further investigate the interface of InAs/GaAs heterostructures, Figure 5 shows highresolution TEM images of the nanowire sample shown in Figure 4 (25 s CF4 etch) taken with the beam aligned along the ⟨110⟩ zone axis of the GaAs substrate. InAs nanowires grew
Figure 5. (a) Low- and (b) high-magnification TEM micrographs of an InAs nanowire grown on a GaAs (111)B substrate with notations; (c) high-magnification TEM micrographs of an InAs nanowire grown on a GaAs (111)B substrate without notations. 5982
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normal to the (111)B GaAs as shown in Figure 5a. Although SiNx cannot be observed in Figure 5a, it is clear the nanowires were nucleated and grown only in selected regions of SiNx from the periodic spacing observed in both the TEM and SEM images. Notice that NWs are narrower at the base surrounded by the SiNx mask but then become wider for the portion which protrudes above the mask. At the base, the nanowire is confined inside the SiNx patterning pores with the diameter confined to approximately 25 nm. Once the nanowire length exceeds the thickness of the SiNx mask, lateral growth can occur in addition to vertical growth. From the TEM image in Figure 5, we estimate that the diameter increases from ∼25 nm at the base to ∼27 nm above the SiNx mask. The dark and bright stripes seen in Figure 5a indicate that twin planes or stacking faults exist22,23 along the length of the nanowire. This can be seen clearly in Figure 5b as a change in the direction of the columns of atoms along the length of the nanowire. The resulting zigzag pattern of the side facets seen along the length of the nanowire is also evidence of a primarily zinc blende (ZB) structure with extensive twinning. The ZB structures follow an ABCABC stacking sequence with each letter representing a bilayer of InAs pairs. A twin plane defects occur when a single bilayer is incorrectly stacked in a ZB crystal, which reverses the stacking sequence from ABC to CBA. For example, in a section ABCABACBA, growing from left to right, A is the faulted stacked layer that creates the twin plane. Sequential twin planes or equivalently sequential twinned bilayers result in a platelet of the wurtzite (WZ) ABAB structure.24,25 Elevated growth temperatures are known to promote twin defect formation in GaP and GaAs nanowires.23 In fact, Joyce et al. have shown that nanowires grown at higher temperatures (Tg > 500 °C) and with V/III ratios greater than 50 tend to have a higher density of twin planes within a primarily ZB lattice than nanowires grown below 425 °C with V/III ratios less than 50.24 Additional studies could lead to alternative growth conditions that be further optimized to reduce the density of twin planes. Measurements of the InAs diameter yield a uniform diameter of 25 ± 3 nm along the growth direction, correlating well to the SEM measurements. Also based on the top-view SEM images, little to no tapering is observed along the nanowire length in SA-MOVPE, in contrast to previously published results where InAs nanowires were grown using the VLS process utilizing Au seeds.26,27 The interface between the InAs nanowire and the GaAs substrate is also visible in Figure 5b. The dotted line was drawn as a guide to the eye and connects a number of interfacial misfit dislocations observed at the InAs−GaAs interface. The curved GaAs substrate to InAs nanowire interface was likely formed during the dry etching process since GaAs is slowly etched by CF4. A few interfacial misfit dislocations were observed at the GaAs−InAs interface under these diffraction conditions. Misfit dislocations relieve the lattice mismatch strain at the interface between the nanowires with larger diameter (>20 nm) and the substrate, as reported previously.28 Beyond the interface, in the bulk of the InAs nanowire, a series of twins with 1−4 ML periods are observed. Figure 6a−c present the associated fast Fourier transform (FFT) power spectrum patterns taken from the GaAs substrate (region a), InAs−GaAs interface (region b), and InAs nanowire (region c) as indicated in Figure 5b. Three diffraction planes for ZB materials are labeled in Figure 6a and b as a guide to the eye. As can be seen in Figure 6a, the GaAs substrate is characteristic of a ZB structure (lattice constant was fixed at
Figure 6. Fast Fourier transform patterns obtained from the TEM micrograph of Figure 5b from the regions indicated: (a) the GaAs substrate, (b) InAs−GaAs interface region, and (c) the bulk of the InAs nanowire.
0.565 nm).1 However, in Figure 6b, InAs nanowires initially grow with a ZB structure on GaAs substrate. Two interwoven but distinguishable diffraction patterns are observed with lattice constants 0.57 ± 0.01 and 0.59 ± 0.03 nm (relaxed InAs has a lattice constant of 0.605 nm). This shows that the InAs/GaAs interface is relatively sharp and strain is partially relieved at the interface misfits.29 There may also be some degree of In−Ga intermixing, although the experimental uncertainty in the lattice constant measurement precludes making this determination with certainty (region b).12 Finally, the FFT in Figure 6c shows an overlapping pattern of a ZB pattern possessing many twin 5983
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defects.30 The elongated streaks are due to the rotational twins of the nanowire ZB lattice.31 Summary. Catalyst-free InAs nanowires were grown by selective-area MOVPE on (111)B GaAs substrate using a DBC patterning technique. A dense array of narrow diameter (∼25 nm) nanowires (∼ 5 × 1010 cm−2) has been achieved. Nonuniformities in the nanowire length were observed and may be due to an interplay between variations in the mask opening diameter and the growth process. TEM measurements indicate that fully strain-relaxed nanowires are achieved with interfacial misfit dislocations near the growth interface but otherwise appear to be threading dislocation-free while exhibiting twin defects in a primary ZB crystal structure.
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(13) Madaria, A. R.; Yao, M.; Chi, C. Y.; Huang, N.; Lin, C.; Li, R.; Povinelli, M. L.; Dapkus, P. D.; Zhou, C. Toward Optimized Light Utilization in Nanowire Arrays Using Scalable Nanosphere Lithography and Selected Area Growth. Nano Lett. 2012, 12, 2839−2845. (14) Park, J. H.; Khandekar, A. A.; Park, S. M.; Mawst, L. J.; Kuech, T. F.; Nealey, P. F. Selective MOCVD growth of single-crystal dense GaAs quantum dot array using cylinder-forming diblock copolymers. J. Cryst. Growth 2006, 297, 283−288. (15) Kim, M.; Safron, N. S.; Han, E.; Arnold, M. S.; Gopalan, P. Fabrication and Characterization of Large-Area, Semiconducting Nanoperforated Graphene Materials. Nano Lett. 2010, 10, 1125−1131. (16) Mawst, L. J.; Park, J. H.; Rathi, M. K.; Kuech, T. F.; Verma, V. B.; Coleman, J. J. Selective MOCVD growth of InGaAs/GaAs and InGaAs/InP quantum dots employing diblock copolymer nanopatterning. Proc. SPIE 2009, 7224, 722407. (17) Kitatani, T.; Tsuchiya, T.; Shinoda, K.; Aoki, M. In situ etching of InGaAsP/InP by using HCl in an MOVPE reactor. J. Cryst. Growth 2005, 274, 372−378. (18) Park, J. H. Ph.D. Thesis, University of WisconsinMadison, Madison, WI, June 7, 2010. (19) Tomioka, K.; Mohan, P.; Noborisaka, J.; Hara, S.; Motohisa, J.; Fukui, T. Growth of highly uniform InAs nanowire arrays by selectivearea MOVPE. J. Cryst. Growth 2007, 298, 644−647. (20) Dayeh, S.; Yu, E.; Wang, D. III-V Nanowire Growth Mechanism: V/III Ratio and Temperature Effects. Nano Lett. 2007, 7, 2486−2490. (21) Schneider, C. A.; Rasband, W. S.; Eliceiri, K. W. NIH Image to ImageJ: 25 years of image analysis. Nat. Methods 2012, 9, 671−675. (22) Dick, K. A.; Caroff, P.; Bolinsson, J.; Messing, M. E.; Johansson, J.; Deppert, K.; Wallenberg, L. R.; Samuelson, L. Control of III−V nanowire crystal structure by growth parameter tuning. Semicond. Sci. Technol. 2010, 25, 024009. (23) Johansson, J.; Karlsson, L. S.; Dick, K. A.; Bolinsson, J.; Wacaser, B. A.; Deppert, K.; Samuelson, L. Effects of Supersaturation on the Crystal Structure of Gold Seeded III−V Nanowires. Cryst. Growth Des. 2009, 9, 766−773. (24) Joyce, H. J.; Wong-Leung, J.; Gao, Q.; Tan, H. H.; Jagadish, C. Phase perfection in zinc blende and wurtzite III- V nanowires using basic growth parameters. Nano Lett. 2010, 10, 908−915. (25) Caroff, P.; Dick, K. A.; Johansson, J.; Messing, M. E.; Deppert, K.; Samuelson, L. Controlled polytypic and twin-plane superlattices in iii−v nanowires. Nat. Nanotechnol. 2009, 4, 50−55. (26) Dick, K. A.; Deppert, K.; Samuelson, L.; Seifert, W. InAs nanowires grown by MOVPE. J. Cryst. Growth 2007, 298, 631−634. (27) Dick, K. A.; Deppert, K.; Maartensson, T.; Mandl, B.; Samuelson, L.; Seifert, W. Failure of the vapor-liquid-solid mechanism in Au-assisted MOVPE growth of InAs nanowires. Nano Lett. 2005, 5, 761−764. (28) Kavanagh, K. L. Misfit dislocations in nanowire heterostructures. Semicond. Sci. Technol. 2010, 25, 024006. (29) Paladugu, M.; Zou, J.; Guo, Y.-N.; Zhang, X. Nature of heterointerfaces in GaAs/InAs and InAs/GaAs axial nanowire heterostructures. Appl. Phys. Lett. 2008, 93, 101911. (30) Kang, J. H.; Gao, Q.; Parkinson, P.; Joyce, H. J.; Tan, H. H.; Kim, Y.; Guo, Y.; Xu, H.; Zou, J.; Jagadish, C. Precursor flow rate manipulation for the controlled fabrication of twin-free GaAs nanowires on silicon substrates. Nanotechnology 2012, 23, 415702. (31) Ikejiri, K.; Ishizaka, F.; Tomioka, K.; Fukui, T. GaAs nanowire growth on polycrystalline silicon thin films using selective-area MOVPE. Nanotechnology 2013, 24, 115304.
AUTHOR INFORMATION
Corresponding Author
*Tel.: 1-732-447-7671. E-mail:
[email protected]. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors gratefully acknowledge the financial support of NASA STTR NNX11CC58C. Work at UWMadison was also supported in part by The National Science Foundation Materials Research and Engineering Center (DMR-1121288). The authors also thank S. Babcock for technical discussions.
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