Interconnects for a symmetric-self-electro-optic-effect-device cellular-logic image processor

Interconnects for a

symmetric-self-electro-optic-effect-device cellular-logic image processor F. A. P. Tooley,

S. Wakelin and M. R. Taghizadeh

An optical circuit is successfully operated by interconnecting

two arrays of 128 symmetric self-electro-optic-

effect devices. The holographic interconnect used in this cellular-logic image processor is described. The design issues (noise orders, efficiency,and ease of alignment) associated with the interconnect and and extensions of it are discussed. Key words: Binary phase gratings, diffractive optics, computer-generated hologram, optical interconnection, free-space digital logic.

1.

Introduction

This paper describes the interconnect used in the demonstration of a symmetric self-electro-optic-effect (S-SEED) cellular-logic image processor." 2 The work described deals with the practical implementation of a nearest-neighbor interconnection in an optical circuit and extensions of it. * In Section 2, generic issues pertaining to the implementation of optical interconnects are discussed. This discussion is specific to an interconnect suitable for use in a cascadable optical circuit with minimal loss. Section 3 is a discussion of computer-generated holography: binary and multilevel diffractive optics. Section 4 highlights the effects of noise orders on the performance of a system. Section 5 is a discussion of extensions of the use of computergenerated holograms as optical interconnects. 2.

Optical Interconnects

Investigation of the performance of optical interconnections may be performed with the interconnection module independently. 3 5 Such an analysis is often performed without regard to the constraints on loss, spot size, uniformity, and pitch that it is necessary to consider when a complete system is designed, particularly one in which the optically connected devices are

The authors are with the Department of Physics, Heriot-Watt University, Edinburgh EH14 4AS, UK. Received 4 June 1993; revised manuscript ber 1993.

received 14 Septem-

0003-6935/94/081398-07$06.00/0. 3 1994 Optical Society of America. 1398

APPLIED OPTICS / Vol. 33, No. 8 / 10 March 1994

cascaded. The design of the interconnect is intimately coupled to the design of the other parts of the system. The interconnect described here is one that is suitable for use in a system that uses devices such as S-SEED's. Constant Radiance Theorem

The product of the numerical aperture (N.A.)squared and the cross-sectional area of a beam is constant. 6 7 When fan-in is performed by division of aperture, a consequential reduction in N.A. is necessary. When N identical incoherent beams are combined to form a beam of the same aperture, the resulting beam can carry only 1/Nth of the total incident power. This power loss does not occur when the beams are fanned into N times larger cross-sectional area or one with a N.A. that is Hi times the N.A. that the original beam possessed. The implication is that a larger area detector is necessary to minimize loss. All system experimentsl 8 -' 2 that use S-SEED's have avoided this problem and have achieved lossless fan-in by the use of a fan-out of 2 of a beam illuminating a 5 jim 5 [um window and a fan-in of 2 of these beams to illuminate a 5 Aimx 10 jlm window (Fig. 1). Coherent Fan-In

If mutually coherent beams are fanned into the same spatial mode, interference will occur. For successful fan-in of all possible optical power, constructive interference must occur across the whole detector aperture. Any departure from this optimum condition will result in power being directed into another order. Coherent fan-in is illustrated by Fig. 2. This is a photograph of the device plane and spot array used in

and the two beams fall on the same area. Figure 2 shows the S-SEED array with two spots fanning into each device window, which causes nonuniformity in

intensity acrossthe array. Space Variance and Space Invariance

The space variance of an interconnection is a measure

ofthe complexityof the permutation that it performs.

Fig. 1. Photograph of S-SEED windows and spot array that shows fan-in of two beams to each horizontal window on a 20-pLmpitch.

5 plm

the optical circuit described in this paper.'

10 ALm

A space-invariant interconnection (SII) performs the same operation on all the inputs (e.g., shift"8 ); a space-variant interconnection (SVI) may route all or some of the inputs differently (e.g., Banyan). A SII is easier to implement than a SVI. Lower hardware complexity is required. A SVI can be made by (1) making more connections than those required with a SII and masking those that are not needed, e.g., Banyan,"1-'3 (2)combining a number of SII's, e.g., the perfect shuffle,5 14 or (3) making a faceted interconnect.' 5 The ability to provide a SVI is a powerful advantage of optics that often permits the reduction of the complexity of other system hardware. However, even simple SII's that are optically implemented can perform useful tasks. This paper discusses issues pertaining to the implementation of a SII. 3.

Fan-out

was performed by a 1 x 2 binary phase grating (BPG).

Figure 1 shows the optical case as implemented in the circuit that connects nearest neighbors horizontally. The period of the BPG was chosen such that the focal spots were not fanned into the same area on the device, the spots did not overlap, and no coherent effects were evident. However, rotation of the BPG by 90° fans each beam to vertical nearest neighbors,

Fig. 2. S-SEED array that shows coherent fan-in when two spots overlap, resulting in nonuniformity.

Surface-Relief Structures

Binary Surface-Relief Structures

Illuminating a simple binary phase or an amplitude periodic structure will provide a spatially modulated binary phase or amplitude wave. On transformation with a lens, the far-field diffraction pattern will be an array of focal spots, with position and intensity determined by the structure of the grating. This is an isoplanatic device that replicates the input beam profile in the derived beams. Optical elements that can generate regular or irregular patterns of beams of equal or arbitrary predetermined powers by using this technique are now standard components in photonic switching circuits and parallel digital optical computingdemonstrators.18- 2 6 Fourier-domainarray generators, pioneered by Dammann and G6rtler,17 which are typically one-dimensional (1-D) or twodimensional (2-D) phase gratings with an optimized periodic structure, are particularly favored for these purposes. Their binary phase nature, which requires a simple fabrication procedure, together with their relative ease of design, have been the primary advantages of this class of components over alternative approaches. By application of a stochastic method of simulated annealing to Dammann's coding techniques, it has been possible to design arrays with > 1000 x 1000 spots.18 The disadvantage of this type of array generator is the poor theoretical diffraction efficiency of typically (8/r 2)2 (66%) for a 2-D array generator that consists of rectangular patterns only (separable). By the use of trapezoids instead of rectangles (nonseparable), the efficiencies can be increased to 75% for a 2-D array. This is at the expense of increased computational and fabricational complexity. 10 March 1994 / Vol. 33, No. 8 / APPLIED OPTICS

1399

Multilevel Surface-Relief Kinoforms

For the majority of array generators needed for optical computing applications, the 65-75% range of efficiencies is sufficient. However, if the elements are going to be used as a SII, then it is desirable that the power in the higher diffraction orders is minimized. An increase in diffraction efficiency can be achieved by the use of periodic multilevel or continuous phase profiles, the so-called kinoform. A variety of techniques can be employed to fabricate this type of element including photolithography and reactive ion etching,' 8 direct-write electron-beam and laser beam lithography of resist, 9 2 0 and volume holography.' 5 Our preferred fabrication method is based on VLSI technology. This requires N electron-beam-generated binary amplitude masks, photolithography, and reactive ion-etching steps for the fabrication of array illuminators with K = 2 N equally spaced relief depth levels in fused silica. Table 1 shows the comparison between binary and multilevel separable and nonseparable gratings.21 For low fan-out, significant improvements can be obtained by multilevel nonseparable designs. For large fan-out, the difference between separable and nonseparable multilevel solutions is insignificant. Implementation

The required interconnection is carried out in the Fourier plane of a 4-f system. An array of focal spots generated by a BPG is used as the input. The phase grating makes a change to the phase profile so that on retransforming, the output from each pixel in the array has undergone a fan-out to nearest neighbors. Thus a fan-in from nearest neighbors in the input array is also performed. A 1 x 2 transmission BPG was fabricated. The component was used to implement a 1-D nearestneighbor interconnection between two arrays of SSEED's. The theoretical efficiencyof a 1 x 2 grating is 81% (8/Ir 2 ), 40.5% of the energy going into each of the first-order beams and the rest into higher diffraction orders in a sinc2 distribution. An advantage of this grating is that the power in the two first-order beams are identically equal as no mechanism exists to spoil the perfection of the splitting. This is of benefit in maintaining uniformity in the array of beams. There are additional losses that are due to (1) the reflectivity (4%) of the glass-air interface, (2) the finite reflectiivity of the antireflection coating on the Table1. Comparisonof Efficiencies betweenBinaryand MultilevelGratingsa

Type

2x 2

4x 4

8x 8

16 x 16

32 x 32

DG NG MG NMG

65.7 65.7 65.7 90.6

50.0 77.5 84.2 94.1

58.1 75.6 89.3 90.7

66.6 76.2 91.6

67.9 74.4 91.7

aDG, separable binary Dammann grating; NG, nonseparable binary stripe-geometry grating; MG, separable 16-level grating; NMG, nonseparable multilevel grating. 1400

APPLIED OPTICS / Vol. 33, No. 8 / 10 March 1994

other side of the substrate into which the BPG is etched (which is 1.7% for a quarter-wave of MgF2 on fused silica), and (3) residual light in the zero order. This can, with low yield in the fabrication process and tight specification on the operating wavelength, be brought below 1%. In the grating used in this work, 1.5% of the incident light remained in this order. These effects reduce the light in both first-order beams to only 75% of the incident light. As a 1-D interconnect, the grating pattern was simply parallel stripes of phase depths 0 and mr. The period is equal to 2fX/D, where D is the spot spacing, f is the focal length of the transform lens used to create the array of spots on the S-SEED, and Xis 850 nm, the wavelength that corresponds to the zero applied field exciton peak absorption. The pitch of the S-SEED is 20 m. However, to avoid coherent fan-in, the spacing of the beams after the BPG is 17.5 jim. This places the two beams 5 m apart in the center of the 10-im window. The BPG was used with a 7.79-mm focal-length transform lens. The period used was therefore 757 jLm. A BPG with such a large period is relatively easy to fabricate. The period is reduced if the pitch increases, as it will with smart pixels (devices with a large area because of surrounding electronics), or if an interconnect to a position farther than nearest neighbors is desired. If the period is 10 jim, fabrication problems are severe, especially with regard to specifying the period to the required precision of one part in a thousand. The BPG was used successfully in the circuit, with no problems caused by coherent fan-in because of the fan-out spacing. The 1-D nearest-neighbor interconnection was used in the implementation of the noise removal algorithm described in Ref. 1 in which logic was performed on fanned-in signal inputs from nearest neighbors. The interconnect was found to be easy and convenient to align by the use of the novel optomechanics (slot plate and cells) described in Refs. 22 and 23. 4. Noise Orders

The intensity envelope function of the orders for a transformation is a sinc2 function. Careful optimization of the design and fabrication procedure can permit reduction of the power directed into the zero and unwanted higher orders, but the binary nature of the phase structure determines the minimum power in the noise orders to be 19% for a 1 x 2 BPG. The intensity profile of the sinc2 envelope function shown in Fig. 3 determines the intensity of the noise orders for a 1 x 2 BPG. Orders occur at phase (2n 1)'r/2, where n is the order number, and the intensity of the order n beam is sinc 2 [r/2(2n - 1)]. When this intensity is normalized to the power in the first-order beams, the relative power is (1/2n - 1)2, where n is an integer. The spacing of the noise orders s, the window spacing x, and the width 2p will determine which orders coincide with the windows on the device array. The distance of the nth spot from the zero

receive a 19% contribution from the noise orders. In this case, APG/P = (19/40.5)%. The nonuniformity is equivalent to 47% of the power of a first-order beam. Consider the effects of this when a device is latched (i.e., a single input). For correct operation of a S-SEED, the signal input power ratio must be greater than T (the minimum input contrast required for switching). For nonuniformity to be taken into account, the worst case must be considered. This

1 7

Relative Intensit)

1 .

.

.

,

.

.

-57r -3n-r /2 /2

requires

,

.

/2

/2

.

.

.

.

i

37n

51r

/2

/2

.

.

phase (radians) Fig. 3. Relative intensity of the orders produced by a 1 x 2 BPG 2 show a sinc form.

order is equal to (2n - 1)s, the distance of the mth window from the zero order is equal to mx ± p, and so coincidence occurs when (2n - 1)s = mx + p, where m and n are integers. Device Tolerance to Power Contributed by Noise Orders

The tolerance study described in Ref. 24 discusses the merit of restricting the number of fanned-in signals to two. (In addition, tolerance studies for S-SEED's are discussed in two papers in this issue.2 5 26) This restriction is required so that the implementation of logic functions was sufficiently tolerant to signal nonuniformity to permit correct operation over the whole array. The uniformity of the power in an array of beams incident upon an array of devices is decreased because of power in the noise orders. This is the situation described in Refs. 24-26. The power in the noise

that

the

equation

[1 - (PG/P)]/

be satisfied, where C is the Given that APG/P = 47% and output contrast. T = 1.4, then for correct operation C > 2. The conditions for latching are only just satisfied for the usual contrast. This assumes the presence of no other nonuniformity. With a fan-out, there are two inputs, and a logical decision is necessary to determine the state. Logic gates are less tolerant to nonuniformity than latches. Specificcases must be examined to determine whether logic will be performed correctly. The ratio of the inputs (signals and noise) is evaluated and compared with the device input contrast T. The situation is shown in Fig. 5, with two signal inputs incident upon [1

> T/C 2 42 6

+ (APG/P)]

the device windows, with a contrast

of 3. A two-

input operation is performed with a (1, 1) input and a (1,1) INPUT

0.47

C

0.47C

1 1

orders may be thought of as a global nonuniformity

APG/P, the magnitude of which determines whether the devices can operate correctly. For the effect of the noise orders to be quantified, specific cases of implementation must be analyzed. Consider the case in which the 1 x 2 BPG fans to the centers of nearest-neighbor windows, as illustrated in Fig. 4. Initially, coherent effects are ignored. The contributions from all the noise orders must be taken into account for the center elements in the array. The worst affected pixel will therefore

0.47C

(1,0) INPUT

I

C

0.47

1

--

Fig. 5. Each set of two squares represent the set and reset WY2 Fig. 4. If two arrays are interconnected

windows of a S-SEED. The upper [lower] figure shows the situation for a (1, 1)[(1, 0)] logic input with a contrast of 3. The by a 1 x 2 BPG, then

there willbe fan-out of the state of the first array to the centers of the nearest neighbors in the second array.

labeled arrows on the left represent the powers of the beams present in these logic inputs. The labeled arrows on the right show the contributions from noise orders. 10 March 1994 / Vol. 33, No. 8 / APPLIED OPTICS

1401

(1, 0) [worst-case] input. The noise orders contribute 0.47 of one signal input to one window and 0.47C

no

(i.e., 1.41 of one signal input if C = 3) to the other

Coherent fan-in must be taken into account because the array generation previous to the 1 x 2 BPG will produce some focal spots that are in phase. For the (1, 0) input, the input contrast ratio is

_-Ipl

n

1.2%, and n 6 contributes 0.8% of

3 4%

Ci 4 2%

O 5 1.2%

m

CDi

6 0.8%

Fig. 6. Rectangles represent device windows;the circles represent positive orders produced by a 1 x 2 BPG labeled with the percentage of the first-order power.

1402

,lie /

"*\

rI5

I ~Si

no

'

n-2

10

- _-Npl

1 or C (the noise orders occur in complementary pairs). If the input ratios are evaluated with these noise contributions for a (1, 0) input when C = 3, the ratio is changed by 40% to 1.4. Somewhat counterintuitively, increasing the signal contrast actually makes things worse: an increase to C = 6 increases the input ratio to greater than 70% to 1.7. The (1, 0) input is the limiting case at these values of C so it can be seen that a larger contrast can cause a reduction in tolerance to effects of the noise orders because the noise also has a higher contrast. In practice, performance of logic on fanned-in signals was carried out successfully even with additional nonuniformities present. The magnitude of the nonuniformity contributed by the noise orders was relatively small and found to be of little significance as nonequal pitch and spot spacing was used.

0Oa1 c)

5

10

The 1 x 2 BPG may be designed so that it fans out to one side of the nearest-neighbor windows.13 The device pitch is not the same as the spacing of the noise orders, so a large proportion of the noise is not incident upon any windows. This is possible with the device array used in the circuit implementation described in Ref. 1. The 5 jim x 10 jim windows are on a 20-jim pitch, so fan-out to positions spaced at 17.5 jim permits significant noise contributions only from < 10% of the second order, < 20% of the fourth order, the fifth, and the sixth noise orders, and the zero order (see Fig. 6). In this situation, each window will also received power from neighboring pixels on either side. Figure 6 shows the positions of the noise orders with respect to the zero-order beam (the first-order beam is the desired beam). Figure 7 shows the beams (signals and noise) that coincide with each window. From each side of the window, there are contributions from n2 of 0.9%, from n 4 of

2 11%

v

ne

Nonequal Beam and Device Pitch

0 1 1.5% 100%

n4

.0-

,-VW

rI

C = 3. This requires that 1.3 < T < 1.7 for correct operation of the gate. This change in the input ratio is unacceptable for practical implementation.

ED [M Ci cm

-

-4

changed by 32%, from 1 to 1.32, when C = 3. The (1, 1) input is changed by 43%, from 3 to 1.7, when

0.3%, n5 contributes

n -2e 10

n-2

10

APPLIED OPTICS / Vol. 33, No. 8 / 10 March 1994

n4 5

n -4

n5

5

n 6

Si

II S

2

no Fig. 7. Rectangles represent the signal and return windows of a S-SEED. The labeled arrows represent the signal beams (S's) and noise orders (n's) incident upon a two-input logic gate for the situation of unequal spot spacing and device pitch shown in Fig. 6.

5.

Discussion

The problem with using a phase grating as an optical interconnect is that unwanted noise order power falling on detectors reduces the input contrast. In some circumstances, for example nondifferential data representation, low contrast or high initial nonuniformity that is due to array generation, the cross talk caused by noise orders could make a system of this type unworkable. There are at least three other actions that can be taken to minimize the potential problem. First, a nonseparable multilevel phase grating will reduce the noise order power (Table 1). This technique is not applicable to the case considered here (a 1 x 2 grating). Second, as first suggested in Ref. 13, the power in the relevant orders can be totally eliminated (suppression) by the use of a binary grating with a more complicated structure. The total efficiency decreases only slightly when this is done. Instead of the noise orders dropping smoothly (sinc2 ), extra transition points are introduced into the design of the BPG, which redistributes the 19% arbitrarily. For example, in this system, increasing the power in the third- and seventh-order beams at the expense of reducing it in the fourth-, fifth-, and sixth-order beams is desirable. This technique has been explored, and 1 x 2 gratings of this type have been designed and fabricated to suppress problems with cross talk associated with performing fan-out after a perfect shuffle. Thirdly, the grating can be rotated slightly. This has the effect of moving the first-order beam slightly off the windows, but it also has the benefit of moving the other orders completely off the windows. A roll of only a few degrees is required.

-1

0i

+1

0

E Z 0

-1

+1

~~~0 Fig. 8.

Split and shift interconnect

implemented

with a 1 x 3

BPG. Reading the array (zero order) on the left side of the window implements a right shift (upper figure) whereas reading the array on the right implements a left shift with no change to the interconnect.

So far, the use of a BPG has been discussed only for use as a nearest-neighbor interconnect. Clearly the principal advantage of using an optical interconnect, as opposed to an electrical one, is the relative ease

with which nonlocal interconnection is achieved. References 13 and 14 present the use of a 1 x 3 and 1 x 2 BPG to perform a banyan and a perfect-shuffle

interconnect, respectively. We have also adopted the proposal outlined in Ref. 14 and adapted it for use as a cascadable 2-D folded perfect shuffle on dual rail

data. This interconnect, which consists of a 2 x 2 grating following by a 2 x telescope, will be used in the

demonstration of a sorting module that is currently under construction. In addition, the phase grating approach can be used to implement an interconnect to any number of neighbors (fan-out not equal to 2). For example, there can be an arbitrary and predetermined weighted interconnect to nearest and nextnearest neighbors. Such an interconnect may have potential in neural networks. Another extension of the simple nearest-neighbor interconnect includes the use of a 1 x 3 phase grating that, as shown in Fig. 8, can implement a split and shift interconnect. The read-beam position is chosen to give a split to either the left or the right (or up or down). This is an unusual type of dynamic interconnect in that the hardware of the interconnect remains the same and the programmability is achieved by choice of two possible sets of read beams. Finally, the fixed interconnect can, of course, be replaced by a dynamic interconnect. 2 7

28

This allows

the interconnect to alternatively be turned off, fanout horizontally or vertically, and fan-out by different pitches on different clock cycles.

The use of pixel-

lated electrically addressed phase-only spatial light modulators

is particularly well suited to this role as

the typical period required is well matched to the spatial light modulator pixel pitch. 6.

Conclusions

The implementation of nearest-neighbor interconnections by the use of a simple phase grating was discussed. Effects of coherent fan-in may be significant if a device is to be well aligned with beams fanning together. Local interconnection in a system

may be carried out simply and effectively if consideration is made of the issues that arise with particular methods. The experimental work was funded by the Sciences and Engineering Research Council and Boeing Aerospace and Electronics. The BPG's were etched by J. M. Miller and N. Ross. The support of S. D. Smith, B. S. Wherrett, and A. C. Walker is acknowledged. References 1. F. A. P. Tooley and S. Wakelin, "Design of a symmetric self-electro-optic-effect cellular-logic image processor," Appl. Opt. 32, 1850-1862 (1993). 2. S. Wakelin, "Design and construction of a free-space digital

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