Low Power FPAA Design Based on OTA Using 90nm CMOS technology Soliman Mahmoud1 ,Kareem Ali2 , Mahmoud Rabea3 , Abdallah Amgad2 , Ahmed Adel3 , Ahmed Nasser3 , Hussien Mohamed3 , Yehea Ismail2 Sharjah University, Sharjah, UAE1 ; Nile University, Cairo, Egypt2 ; Fayoum University, Fayoum, Egypt3 Email:
[email protected],
[email protected]
Abstract—This paper presents a low power Field programmable Analog Array (FPAA) based on operational transconductance amplifier (OTA) implemented in 90nm 1.2V CMOS technology achieving an operating frequency of 288MHz. Different continuous time filters in a frequency range from 52MHz to 282MHz can be implemented on that FPAA design achieving a max power of 62 mWatt for a 6th order band pass filter. Index Terms- FPAA, OTA, CAB and CMFB.
I. I NTRODUCTION FPAA is considered as one of the most important ICs in analog signal processing applications. Due to the high non-recurring cost of IC design and the need for having a reprogrammable chip makes Field programmable Analog Array as an important device of microelectronics. Field programmable analog arrays (FPAAs) aren’t as flexible or usable as their digital counterpart FPGAs so they are mainly used in some specific applications, this made FPAA a great topic for research centers and universities to develop it to be more flexible with lower cost in order to increase its market share, and was our motivation for developing and improving the design of FPAA [1]. For digital circuits, field programmable gate arrays (FPGAs) are highly developed and became indispensable as both development tools and application platforms, while FPAA is used to deal with analog signals, where most of analog signals sources need filtering before higher signal processing, so one of the main applications where field programmable analog array (FPAA) used in, is to implement a reconfigurable and adaptable filters. In wireless communication high bandwidth is needed, so if filtering is done in continuous time there will be no need for sampling and the degradation effects that may be result from sampling like bandwidth degradation and sampling noise will be bypassed. FPAA has been proven to be suitable for analog front-ends in signal-processing and is commonly used as interfaces for sensor-readouts. Also FPAA is used in implementing adaptable filters when signal bandwidth or data rate is variable, e.g. in reading the channels of hard disk drives and in wireless communication. FPAA is also used as pre-stage for analog to digital converters to amplify and filter the signal before being sampled. Software defined radio (SDR) is an emerging field, where one reconfigurable hardware platform is used to provide
all necessary signal processing for multiple wireless communication standards, so FPAA can be used as an SDR hardware. Hence, in this work the main focus was on analog filters for high frequencies to be suitable for wireless communication. In this paper, the hexagonal structure proposed by J.Becker [2] is used in this work using 90nm 1.2V CMOS technology. Section II discusses the hexagonal structure and the architecture of the configurable analog block (CAB) which is the basic building block of the FPAA. The basic element of the FPAA (OTA), which was designed using 90nm 1.2V CMOS technology and simulated using LTspice is discussed in section III. Programmability and configurability of the FPAA are discussed in sections IV and V, then the results of implementing some applications on FPAA is shown in section VI. Finally conclusions are provided in Section VII. II. FPAA ARCHITECTURE A. FPAA Structure The FPAA structure is a very effective criterion which must be taken into account because of its effect on the response of the applied application. The proposed FPAA [2] consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice as shown in Fig.1. Each CAB contains a central node which is considered as an integrating capacitance node. Six outputs of tunable Gm-cells are connected to that node from the six neighboring CABs, six inputs tunable Gmcells which exist in the same CAB are connected to that node too, and also an additional self feedback one is connected to that node to allow getting a first order feedback in any configuration, in addition to another six tunable Gm-cells for signal input, whereas the central CAB does not contain input Gm-cell. The FPAA can implement filter up to the 8th order by using all the available CABs. Three independent filters can be implemented on FPAA by using different CABs and different inputs at the same time. The integrating node in each CAB is also connected to a CMFB circuitry to ensure the OTAs stability. B. CAB structure Each CAB in the FPAA contains six tunable Gm-cells whose outputs are connected to the integrating nodes of the neighboring CABs and inputs are connected to the integrating node of the CAB which they are inside, and additional tunable Gm-cell makes self feedback to the same integrating node
978-1-4673-0465-8/11/$26.00 978-1-4673-0465-8/11/$26.00 ©2011 ©2011 IEEE IEEE
Fig. 2.
structure of switchable transconductance amplifier [2].
TABLE I M ODES OF OPERATION OF OTA AND ITS CONTROL BITS .
Fig. 1.
FPAA architecture proposed at [2].
inside that CAB. The output currents from the Gm-cells are integrated at the integrating node at the center of each CAB due to the existence of parasitic capacitance which acts as integrating capacitance that converts current into voltage to be the input for the Gm-cells connected to that integrating node. III. OTA DESIGN
b 0 0 1 1
Po 0 1 0 1
Mode Off Off Negative Positive
Vb1 Bias Bias Bias Bias
Vb4 GND GND Bias Bias
Vb5n VDD VDD Bias VDD
Vb5p VDD VDD VDD Bias
Vb6 GND GND Bias Bias
Fig.2 shows the structure of the OTA. The configuration bits are entered to the OTA throughout a shift register, the control word then shifted to the control logic circuit that determines the operation of the switchable OTA.
A. Switchable folded cascode OTA Operational transconductance Amplifier (OTA) design is considered one of the most important stages during the design of FPAA as it is the basic building block of the structure. Because of the output of OTA is current , it is considered as an advantage for using OTA as a basic building block in FPAA design. As the summation of the voltage at the integrating node is not a trivial matter so OTA is preferred. Folded cascode OTA topology proposed by Henrici [3] is used in this work, while other topologies like telescopic and gain boosted OTAs could be used depending on the required specification. As OTA design wasn’t our main concern so high specifications for the OTA wasn’t our goal. One of the advantages related to the proposed OTA by [3] is the constant stray capacitance at the input of the OTA, but to maintain a constant parasitic capacitance at the output of OTA, additional dummy transistors must be added to the output node, and this technique is proposed in [4]. Another technique may be used by minimizing the dimensions of the transistors that contribute to the parasitic capacitances at output node in comparison with the dimensions of the transistors at the input of the OTA. Two additional transistors M10n, M12n are added to the basic folded-cascode to operate it in the inversion mode which means an inverted output (negative mode of OTA). Depending on the control word, OTA mode can be tuned. Table.I shows the modes and its control words. One of the drawbacks of using Folded-Cascode OTA topology is the need for large number of biasing voltages, so a biasing circuit should be designed carefully.
IV. GM-CELL In literature, Many of Gm-C filters were designed and proposed, the main advantage of using a constant parasitic capacitance OTA will appear in using the parasitic capacitance as an integrating capacitance at the output node. The reason for using the metal oxide gates capacitance of MOSFETs was proposed in [4]. As the high double poly capacitor is not available in digital CMOS technology. Metal-to-metal structure based capacitors may be used but it has the disadvantage of low capacitance specific value and it’s realized using special techniques, So MOSFETs gates’ capacitances are used instead as it has large specific capacitance value and it’s well controlled capacitors. A. How to maintain parasitic capacitance constant The Folded-cascode OTA proposed in [3] does not use any additional dummy transistors to maintain constant parasitic capacitance, but it relays on the idea of dominating the parasitic capacitance of the input over the parasitic capacitance of the output by making the dimensions of the input transistor (M2-M3) larger than the output transistors (M6-M12). B. Tunability of Gm-Cell Each Gm-cell consists of six operational transconductance amplifiers (OTAs) connected in parallel as shown in Fig.3, and the cells gain depends linearly on the number of switched on OTAs. This allows coarse tuning of the Gm-cell. The foldedcascode OTA can be switched on or off and the signal can be
TABLE II A SPECT R ATIOS OF TRANSISTORS OF OTA. MOS W(um) L(um)
M1 28 0.5
M2 11 0.29
M3 10 0.25
M4 4 0.18
M5 2 0.2
M6 4 0.2
inverted, without switches in the signal path, by controlling the state of the OTA using digital logic circuit. Each OTA has its own bias circuit to reduce cross-talk between OTAs while switching them on and off. Each tunable Gm-cell includes a programmable floating gate current source, which sets the reference current for its six OTAs independent of other cells. It allows control of the OTA tail current, no routing network and bandwidth limiting switches in the signal path are necessary. By switching a tunable Gm-cell off, the signal path between the two cells is cut. If switched on, the tunable Gm-cell together with the receiving node capacitance forms an integrator or Gm-C filter element.
Fig. 4.
DC-response of the OTA
V. DIGITAL CONFIGURATION LOGIC As FPAA is configurable where it can be reprogrammed many times using configuration bits that can be produced using search algorithm like genetic algorithm or it can be produced using previously known configuration bits for a well known types of filters. So that mean we need a shift register to store those configuration bits and then pass them to combinational logic in order to switch the OTA to the required state (OFF, Positive or Negative) as depicted in Table.I.
Fig. 5.
Derivative of Iout vs Vin on the horizontal Axis.
B. B. Tunable Gm-cell results The following Gm-cell is tuned by changing the integer value n within range [16].Table.III shows the increase in the unity gain bandwidth ft by changing the value of n. Also Fig.7 shows simulation responses of a tunable Gm-cell. ft =
n.gm 2.Π.Cpar
(1)
Where ft is the transient frequency, gm is the transconductance gain, n is the number of switched on OTAs and Cpar is the load parasitic capacitance. From simulations we can estimate the parameters in Table.III and obtain the results proposed in Table.IV Table V shows the characteristic frequency and power for both a 2nd order and 6th order LP/BP filters. C. Filter implementation on FPAA Fig. 3.
Multiple unit Gm-cell [2].
VI. RESULTS A. OTA results The OTA is designed with aspects ratios shown in Table.II, where it was required to obtain an OTA with gm=450 A/V and linearity range= 40mV, achieving a phase margin of 90 degree result in high stability for the OTA, and consuming total power of 1.28mwatt for the six parallel OTAs (GM-cell).
In literature, many filters topologies were proposed; Fig.8 shows a bi-quad filter structure proposed in [1]. TABLE III E STIMATED PARAMETERS FROM parameter ft(MHz)
gm 449uA/V
SIMULATIONS
Cpar 1.49pF
Ao 19dB
TABLE IV CHANGING THE VALUE OF N AND THE RESULTING TRANSIENT FREQUENCY
n ft(MHz)
1 48
2 96
3 144
4 192
5 240
6 288
Fig. 6.
Fig. 10.
AC-response of the OTA
Simulation of Band pass filter response on FPAA
TABLE VI M ODES OF OPERATION OF OTA AND ITS CONTROL BITS . Filter 1 2 3 4 5 6
Fig. 7.
n1 2 3 4 5 6 2
n2 2 3 4 5 6 3
n3 2 3 4 5 6 4
n4 2 3 4 5 6 5
LPF,fc(MHz) 104.7 151 204 239 282 223
BPF,fo(MHz) 87.1 125.9 169.8 196.7 243.4 195
Table.VI shows different center and cutoff frequencies that can be obtained from the bi-quad band pass filter - low pass filter respectively which measured from Fig.9 and Fig.10 respectively.
Simulation of tunable Gm-Cell
VII. C ONCLUSION A complete design for OTA and FPAA structures have been presented during this work using 90nm CMOS technology with maximum operating frequency of 288MHz. Many Filter topologies were implemented on the FPAA structure and proposed cut- off frequencies for Low pass filter between (52MHz - 282MHz) and center frequencies for Band pass filter between (44.66MHz -243.4MHz ) with max power of 62 mWatt for a 6th order LP/BP filter. Fig. 8.
Fig. 9.
R EFERENCES
Biquad filter structure proposed at [2].
Simulation of Low pass filter response on FPAA TABLE V
C HARACTERISTIC FREQ .
Presented filter Charact. frequency power
AND POWER FOR FILTER
2 ND
2nd order LP/BP 243.4 MHz 31.27 mWatt
AND
6 TH
ORDER
6th order LP/BP 243.4 MHz 62 mwatt
LP/BP
[1] S.A.Mahmoud, E.A.Azab, A.M.Soliman, J. Becker and M. Ortmanns ”Low Voltage Full Differential Current Conveyor Based FPAA ”, Journal Of Circuits, Systems and Computers (JCSC),Dec.2011,. [2] J. Becker, F. Henrici, S. Trendelenburg, M. Ortmanns, and Y. Manoli”A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13um CMOS with 186MHz GBW”, in: Proc IEEE International SolidState Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, USA 2008, pages 70 -71, 596,. [3] F. Henrici, J. Becker, M. Ortmanns, and Y. Manoli, ”A Switchable FoldedCascode OTA without Transmission Gates in the Signal Path”, in: Proc Norchip, Tallin 2008 [4] Widely Programmable High-Frequency Continuous-Time Filters in Digital CMOSTechnology Shanthi Pavan, Yannis P. Tsividis, Fellow, IEEE, and Krishnaswamy Nagaraj [5] Design of Analog CMOS Integrated Circuit , McDraw Hill, Behzad Razavi , 2000 reference page 313 , ISBN 0-07-118839-8 [6] S. DasGupta, E. Eichelberger, and T. Williams, ”Current-mode amplifier/integrator for a field-programmable analog array”, in: Proc IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical.
