MBOA/WiMedia UWB Transceiver Design in 0.13µm CMOS (Invited Paper) C. Sandner∗S.Derksen∗ D.Draxelmayr∗ S.Ek∗ V.Filimon† G.Leach‡ S.Marsili∗ D.Matveev∗ K.Mertens∗ H.Paule† M.Punzenberger∗ C.Reindl∗ R.Salerno∗ M.Tiebout† A.Wiesbauer∗ I.Winter‡ Z.Zhang∗ ∗ Infineon
Technolgies, Austria Technolgies, Germany ‡ Riverbeck UK Email
[email protected] † Infineon
Abstract— A highly integrated, WiMedia/MBOA compliant RF transceiver for Ultra-Wideband (UWB) data communication in the 3-5GHz band is presented. The design includes receiver, transmitter and fast-hopping synthesizer. It is designed in a 0.13 µm standard CMOS technology for a single supply voltage of 1.5V. The receiver features a measured noise figure (NF) of 3.6 to 4.1dB over the three sub-bands. The transmitter supports a maximum TX power of 0 dBm at 20 dB EVM. Index Terms— transceiver, CMOS, UWB, LNA, PA, PLL, fast-hopping.
TX
LO Generation
RX
I. I NTRODUCTION The recently evolving wireless ultra wideband (UWB) standard aims at data rates up to 480 MBit/s in the frequency spectrum of 3 to 10 GHz. The data transmission is based on multi-band OFDM [1], requiring a huge digital processing power. UWB aims at short range high data rate communications, e.g. between digital camera, mobile and laptop or as a general USB-cable replacement. This is clearly a consumer market, which puts a tremendous stress on the chip suppliers for a low cost solution. This requirement is a good reason to aim for a complete CMOS solution as shown in Fig. 1. Although realistic external losses of antenna filter and duplexer must be added, the required output power of -41dBm/MHz seems feasible with an integrated CMOS PA. Next crucial point for the performance of the UWB-receiver is the RF input stage,
Fig. 2.
chip photograph
which has to provide a low noise figure (NF) and a high linearity as this wideband standard will suffer severely from strong blocking RF signals out of WLAN sources at 2.4 GHz and 5 GHz bands. Last but not least the new UWB standard requires a fast hopping from sub-band to sub-band which requires the synthesizer to hop by 528 MHz within 9ns. Special care has to be invested into the synthesizer design in order to meet the spectrum mask imposed by [2]. This work presents a pure CMOS ZEROIF transceiver (Fig. 3) optimized for output power, NF and low spur LO-generation. The presented transceiver outperforms previous published CMOS designs [3], [4] and performs comparable to SiGe BiCMOS based designs [5]. II. R ECEIVE PATH
Fig. 1.
low cost through high integration
The fully differential receiver includes an LNA with high and low gain mode, and a programmable gain amplifier (PGA) with 4 gain steps to enable optimum receive performance for different signal strengths and interferer scenarios [6]. For best performance in terms of NF, gain, chip area and linearity the LNA was realized as a two
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V2I
I
V2I
Q
TX PA
PGA
Power Detect O°
90° fref
ADC
OSC
Fast Hopping Synthesizer
264MHz Control Interface
3.432, 3.960, 4.488 GHz Bandgap Bias
balun
RX
O°
LNA
Fig. 3.
LVDS
90° BUF
I
BUF
Q
PGC
ZERO-IF transceiver block diagram
VDD
RF
out
L1
L1
R1
R1
Cx
Cx
inx
in
R2
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outx
R2
Fig. 5. Fig. 4.
PA concept and schematic
LNA schematic
characterization of all receive chain impairments. stage transimpedance feedback circuit as shown in Fig. 4. The RF-amplifiers are followed by a Gilbert-type downconversion mixer, which generates quadrature (I and Q) outputs. It is based on a class A-B voltage-to-current converter, a Gilbert Quad, and a load which implements both a current-to-voltage converter and a low noise filter used to suppress large out-of-band interferer signals. The position of the filter poles (around 500 MHz) can be calibrated digitally by tuning filter capacitors, thus achieving good transition-band and stop-band accuracy in the presence of process variations. The analog I/Q chip interface is driven by an output buffer with a bandwidth of 1 GHz to enable
III. T RANSMIT PATH On TX side the baseband I/Q analog input signal is converted to current by a highly linear voltage-to-current converter and fed into Gilbert-type folded upconverting mixers. To reduce the LO leakage caused by DC-offset within the mixer stage, a compensation DAC is added and controlled by a serial interface bus. The differential output signal of the mixer is converted to single ended, followed by a programmable gain stage and a singleended integrated 3-stage power amplifier (Fig. 5). The 3 required coils in the PA are realized by stacked inductors.
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TX I channel
SSB I-R OM fref
8.448 GH z PLL
:2
Fig. 6.
RX
4.224 GHz
Q-R OM hop control
I-D AC
3.432, 3.960, 4.488 GH z
Q-D AC
+/- 264 MHz, -792 MH z
SSB
TX Q channel RX
the photograph of the chip, which is packaged in a lowcost very thin profile quad flatpack no-lead (VQFN) plastic package with 48 pins. It is fabricated on Infineon’s 0.13µm standard digital CMOS technology with 1-poly 6-layer copper metal stack and MiM-Capacitors used as the only RF add-on feature. V. E XPERIMENTAL R ESULTS
LO generation block diagram
Gain-switching is implemented by a capacitive divider with switchable divider ratio, yielding a variable gain range of 30dB with a resolution of 1 dB for high gain settings. A power detector followed by an ADC with 6bit resolution is implemented to measure the output voltage of the PA. Taking into account some back-off due to external losses, antenna and impedance mismatch this enables costefficient control of the actual output power to fulfill TX emission mask requirements without need for additional external components. IV. FAST H OPPING LO G ENERATION Figure 6 shows the block diagram of the LO generation. To generate the three required LO frequencies of 3.432, 3.960 and 4.488 GHz with minimal transition time when hopping an open-loop topology is required. Principle idea [7] is to add/subtract a fixed frequency of 4.224 GHz with a variable low frequency (LF) of +/-264 MHz or 792 MHz, respectively. The proposed implementation includes a phase locked loop (PLL), two single-sideband (SSB) mixers (for I and Q channels), and a direct digital synthesizer (DDS) approach for generating the LF frequencies. Advantage of this concept is that there is only one SSB mixer stage within the LO generation chain, which eases control of all unwanted spurious generated in the chip. Due to the DDS approach the inherent harmonics of the LF signal are much lower compared to generating the LF out of divider chains or logic operations. The reference clock is fed to a PLL locking an integrated LCVCO to 8.448 GHz. This frequency is divided by 2 to generate I/Q signals at 4224 MHz. Two current-steering 4bit-DACs running at a sample rate of 4.224 GHz generate the three LF frequencies of +/-264 MHz and -792 MHz . This sample rate was chosen carefully to avoid additional generation of spurs. The sinusoidal I/Q-waveforms are stored in ROM lookup-tables, which can be selected via the hop control commands. The transceiver is completed by a bandgap-based biasing and a high-speed control interface. The latter is required for real-time update of gain and hopping settings. It is implemented with low voltage differential signals running at 264 Mbps to fulfill the requirements of high control speed and low noise coupling from the interface to the RF part. Fig. 2 shows
The transmitter is tested with an OFDM WiMedia/MBOA compliant signal [1]. Figure 9 shows the EVM in band 1 while varying the output power. For large output power levels when the PA is approaching its compression region the EVM degrades. At a power close to 0dBm, the transmitter still meets the required EVM of -20dB [1]. Fig. 7 represents the spectrum at the PA output when operating in time frequency interleaved (TFI) mode [1], hopping between all 3 bands. The resolution bandwidth set at the spectrum analyzer is 1MHz as recommended in [2]. The two graphs show the spectrum with power level set close to -41.3dBm/MHz, and without external bandpass filter (TDK DEA453960BT). Using the filter all spurious are well below -30dBc. The measured conversion gain and NF of the receiver for all 3 bands are shown in Fig. 8. The maximum gain and the minimum NF are 37.8dB and 3.6dB, respectively. Operating at band 3 the NF increases to 4.1dB. The gain variations over the entire baseband frequency range and across all UWB Mode-1 bands are less than 1dB. At low (high) gain setting the IIP3 is +2dBm (-22dBm). The phase noise of the LO generation is characterized at the TX output. From 100Hz to 100MHz offset the integrated jitter is below 1.2 ps RMS for all three bands corresponding to an EVM level of 29.5 dBc for band 3. The measured hopping time of LO generation and receive chain is 2 ns, which is well below the required 9.5 ns described in [1] and mainly limited by the filter pole of the mixer output stage. The performance data of the UWB RF transceiver is summarized in Table I. VI. C ONCLUSION The presented CMOS RF transceiver fulfills WiMedia/MBOA requirements in terms of TX power, TX EVM, settling time, and RX NF. It shows a 2dB improvement in NF to previous CMOS and even BiCMOS transceivers, and compares favourable to previous best-NF BiCMOS transceiver. In TX the CP1dB is improved by 10dB compared to previous designs. R EFERENCES [1] A. Batra et Al., “ Multiband OFDM Physical Layer Specification, Online: http://www.multibandofdm.org, Release 1.0 ,” jan. 2005. [2] FCC, “ Online: http://www.fcc.gov/Bureaus/Engineering Technology/Orders/2002/fcc02048.pdf ,” feb. 2002. [3] B. Razavi et Al., “ A 0.13 m CMOS UWB Transceiver ,” in ISSCC Proceedings, Feb. 2005, pp. 216–217.
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TABLE I T RANSCEIVER PERFORMANCE SUMMARY. RX NF High gain band 1 / 2 /3 RX High gain band 1 / 2 /3 RX minimal Gain RX gain ripple within one band RX IIP3 high / low gain RX S11 high gain LO frequencies LO phase error 100Hz to 100MHz, band 1 / 2 /3 LO hopping time, all bands TX EVM band 1 / 2 /3 @Pout = -4dBm Current consumption RX Chain @1.5 V Current consumption TX Chain @1.5 V @Pout = -4dBm Current consumption LO Generation @1.5 V Chip area Technology
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