ARTICLE IN PRESS
Nuclear Instruments and Methods in Physics Research A 509 (2003) 171–175
Medipix2 parallel readout system V. Fanti*, R. Marzeddu, P. Randaccio Dipartimento di Fisica dell’Universita" e INFN Sezione di Cagliari, S.P. per Sestu km. 0.7, 09042 Monserrato (CA), Italy
Abstract A fast parallel readout system based on a PCI board has been developed in the framework of the Medipix collaboration.1 The readout electronics consists of two boards: the motherboard directly interfacing the Medipix2 chip, and the PCI board with digital I/O ports 32 bits wide. The device driver and readout software have been developed at low level in Assembler to allow fast data transfer and image reconstruction. The parallel readout permits a transfer rate up to 64 Mbytes/s. r 2003 Elsevier Science B.V. All rights reserved. PACS: 07.05.Hd; 87.59.Hd Keywords: Medipix; X-ray imaging; Data acquisition; Parallel readout; PCI bus
1. Introduction The system we describe here is designed for dynamic X-ray imaging, which can be particularly interesting in angiographic applications. The visualization of the real-time flowing of contrast medium in blood vessels gives more detailed diagnostic information with respect to static angiography. Our system is designed to be connected to the fast parallel readout of the Medipix2 chip and has been implemented on a standard extension board. Nowadays, the PC is the most widely used platform in the development of imaging systems as it represents the best compromise taking into
*Corresponding author. Tel.: +39-070-675-4982; fax: +39070-510212. E-mail address:
[email protected] (V. Fanti). 1 http://medipix.web.cern ch/MEDIPIX/
account performance, design time and cost. A commercial PC combined with the proper interface can be used to acquire, process, visualise and store the image data.
2. Requirements of the readout system Medipix2 [1] has 256 256 square pixel channels 55 mm 55 mm each for a total active area of 1.4 1.4 cm2 and is bump bonded to a solid-state sensor for direct conversion of incoming photons. It has been designed to minimize the dead area between chips when they are put together to cover large areas. This configuration is used to obtain flat-panel X-ray detectors for real-time radiography. A dynamic imaging system should acquire at least 25 frames/s. The amount of data which must be read in a single frame is determined by the
0168-9002/03/$ - see front matter r 2003 Elsevier Science B.V. All rights reserved. doi:10.1016/S0168-9002(03)01567-5
ARTICLE IN PRESS V. Fanti et al. / Nuclear Instruments and Methods in Physics Research A 509 (2003) 171–175
172
number of chips in the flat panel, the number of pixels in one chip and the length of the data word (14 bits) of each pixel cell. For a minimal system with eight chips (covering an area of about 15 cm2), the amount of data in a single frame is 7 340 032 bits which gives a requested acquisition rate of about 180 Mbit/s using the serial readout or 5.7 Mword/s using the 32-bit parallel port. During the readout phase Medipix2 is blind to X-rays so, if we want to reduce the dead time down to 10%, we should reach frequencies 10 times higher. The acquisition frequencies required are then 1.8 GHz and 57 MHz, respectively, for serial and parallel readout.
3. Description of the readout system In order to sustain the above-mentioned rates, the acquisition system must be directly linked to one of the internal busses of the PC. The internal architecture of a PC is based on a series of interconnection systems called bridges (Fig. 1). The North bridge connects the highest speed devices, namely the memory and Accelerated Graphic Port (AGP) to the CPU, with a throughput up to 200 MHz. The South bridge connects lower speed devices as disks, PCI expansion bus and I/O ports with a maximum throughput between 33 and 133 MHz depending on the connected device.
CPU
The design of a fast acquisition system can then be based on AGP port or PCI bus. We based our readout on a PCI board in the 32-bit, 33 MHz configuration which is now the most common standard for interface development. As previously mentioned, the acquisition speed required for a dynamical imaging system based on eight Medipix2 chips is about 57 MHz. Therefore, the performance of a 33 MHz PCI device is not adequate for a system with eight chips but is ok for prototype development using a reduced number of Medipix2 chips, whereas the final configuration should be based on a 66 MHz, 64-bit PCI standard. The readout system is implemented on two electronic boards communicating via flat cables. The first board (the motherboard) directly interfaces Medipix2 for I/O operations and control, and the second one (the PCI board) links the motherboard to the PC. 3.1. The motherboard The motherboard (Figs. 2 and 3) houses the Medipix2 chips, the line drivers and the connectors for data and control signals and contains the DACs and ADCs for adjusting the settings for analog signals. The prototype described here houses just one chip, but the design of the board with eight chips is an extension of the present setup and is already at an advanced stage. The input section converts CMOS control signals coming from the PCI board to LVDS before sending them to the Medipix2 chip. The
NORTH AGP
BRIDGE
Memory Medipix2 BUFFER OUT
SOUTH Disks
BRIDGE
PCI bus Fig. 1. PC architecture.
I/O Ports
TEST BOARD 2.2 V
CMOS→LVDS Z-adapter
Fig. 2. Block diagram of the motherboard.
ARTICLE IN PRESS V. Fanti et al. / Nuclear Instruments and Methods in Physics Research A 509 (2003) 171–175
173
Fig. 3. Picture of the motherboard.
Registers OUT
Buffers IN
Clock 3.3 V
CPLD PCI BRIDGE
EEPROM
Fig. 4. Block diagram of the PCI board.
output section amplifies signals coming from Medipix2 before sending them to the PCI board (Figs. 4 and 5). The board also houses a voltage regulator needed to match the bus power supply voltage (3.3 V) to the chip voltage (2.2 V). 3.2. The PCI board A PCI device is seen by the PC as a memory block with offset address and range assigned during the configuration phase. Reading from Medipix2 can be considered as moving data from
consecutive memory locations to another memory area. After each read operation, the memory address is incremented automatically while the hardware sends the clock signal to Medipix2 to allow the output of the next word from the parallel port. In a similar way, control and status signals needed for configuration and acquisition phases are memory mapped. Therefore, each operation corresponds to the writing of a bit pattern in a preassigned memory location. Every operation in a PCI device is easily accomplished by a PCI bridge which has two main tasks. The first one is the conversion of PCI bus signal environment, based on a pile up of incident and reflected wave [2], to the logic signal standard based on two voltage levels. The second task is the conversion of the PCI bus protocol to the much simpler protocol of a local bus. The local bus consists of a 32-bit data bus, 28-bit address bus and some control signal lines (clock, chip select, read, write, etc.). The PCI bridge we used is the PLX PCI9054 [3] which allows bus mastering to perform DMA transfers. Read/write operations can be performed in two different ways: single and burst mode. In the single mode, each operation requires four clock
ARTICLE IN PRESS 174
V. Fanti et al. / Nuclear Instruments and Methods in Physics Research A 509 (2003) 171–175
Fig. 5. Picture of the PCI board.
cycles, so that the maximum achievable transfer rate is 8.25 Mword/s. The burst mode accelerates the I/O operations exploiting the FIFO present inside the PCI bridge. When the FIFO is empty, the first I/O operation fills the FIFO with data coming from 16 sequential memory locations at the maximum clock frequency. Next, I/O operations access data directly from the FIFO without the need to access the bus until the FIFO is empty. This feature can be clearly seen in the timing diagram shown in Fig. 6 where LA2, LA3, LA4 correspond to the lowest address bits in the local bus. Every time the address changes another word is read from the local bus directly connected to the Medipix2 parallel port and incoming data are stored into the FIFO. When the FIFO is full the transmission through the local bus stops for a while allowing the transfer to the main memory through the PCI bus.
These operations are transparent to the software because the bridges of the PC architecture and PCI bus manage all transactions. From the software point of view, reading the Medipix2 data matrix through the parallel port is simply a loop of move instructions from a memory block (the one assigned to the PCI device) to an area of PC main memory. The average speed reached so far with our prototype is 16 Mword/s, to be compared with the performance of 57 Mword/s needed for dynamic imaging with a system of eight Medipix2 modules. 3.3. The software operations Raw data coming from Medipix2 do not correspond to the content of the pixel cells because every line in the 32-bit parallel port works as a serial output. Furthermore, the sequence of 14 bits corresponding to the content of a cell is encoded
ARTICLE IN PRESS V. Fanti et al. / Nuclear Instruments and Methods in Physics Research A 509 (2003) 171–175
175
PCI bridge reads 16 Lword from Medipix2 parallel port through local bus
CPU reads data from FIFO Acquisition rate is about 64 MByte/s : 32 bits - 16 MHz mean acquisition rate Fig. 6. Timing diagram of burst mode reading.
by the pseudo-random number counter of the internal Medipix2 logic. In order to obtain the matrix image, the raw data need to go through a reconstruction process. This operation is executed during the photon counting phase which lasts at least 36 ms, if we consider a time interval of 40 ms between two frames and a 10% of this time for the readout phase.
The results obtained with our prototype are promising and show that the configuration for the final system should be based on 66 MHz–64 bits PCI bus. Image reconstruction made by software simplifies hardware design.
References 4. Conclusions The Medipix2 parallel readout system has been conceived for dynamic imaging acquisition at 25 frames/s. It is based on a PCI device working on a standard PC. Interfaces based on PCI bus are easy to develop and the hardware complexity is transparent to the software thanks to the bridges.
[1] X. Llopart, M. Campbell, R. Dinapoli, D. SanSegundo, E. Pernigotti, Medipix2, a 64 k pixel readout chip with 55 mm square elements working in single photon counting mode, Proceedings of the IEEE Nuclear Science Symposium and Medical Imaging Conference, San Diego, California, November 4–10, 2001, M7-4, IEEE Trans. Nucl. Sci. 49 (5) (2002) 2279. [2] T. Shanley, D. Anderson, PCI System Architecture, Addison-Wesley, Reading, MA, 1999. [3] http://www.plxtech.com/products/9054.
