Nanoelectronic architectures
Descrição do Produto
Nanoelectronic Architectures
Greg Snider QSR, Hewlett-Packard Laboratories © 2004 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice
Overview •
Crossbars
•
Conventional logic
•
Defects and faults
•
Unusual latches
•
Strange logic and weird state machines
•
Demo—compilation and simulation
August 14, 2006
2
Crossbars
interlayer August 14, 2006
3
Crossbars
40
August 14, 2006
nm 100 nm 1110 mm μm 100 μm μm
4
Imprint Lithography
Mold Mold Mold Polymer Polymer Substrate Substrate Substrate US Patent 6432740
August 14, 2006
5
Nanoscale Molecular Devices
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6
Nanoscale Molecular Devices
August 14, 2006
7
Configurable Crossbar = Tile
Crossbar
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8
Configurable Crossbar = Tile
interlayer August 14, 2006
9
Configurable Crossbar = Tile
Crossbar
junction August 14, 2006
10
Configuring a junction
+V
junction -V August 14, 2006
11
Interfacing: one scenario silicon substrate
Substrate provides through microwires: power clock data I/O configuration I/O August 14, 2006
12
Tiles Æ Circuits
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13
Tile Types
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14
Mosaics = tiles of different types +V
configurable p-FETs
Ground
configurable n-FETs
configurable switches
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Mosaic: p-FET / resistor logic V+
A A B
B C
C AB + C
GND August 14, 2006
16
Mosaic: Diode / resistor Logic +
+
+
+
A A B B C C
AB + AC
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17
Mosaic: n-FET / p-FET logic +V
August 14, 2006
Ground
18
Are Tiles / Mosaics necessary? •
Adds complexity to manufacturing.
•
Can we simplify?
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Are Tiles / Mosaics necessary? •
Adds complexity to manufacturing.
•
Can we simplify?
Strategy:
Fold mosaics… tile Æ layer !!!
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20
Folded Mosaics
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21
Multi-folded Mosaics
(c)
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22
Defects But…Defects! “stuck closed”
broken wires “stuck open”
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23
Defect Avoidance V+
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24
Defect Avoidance as a Resource Allocation Problem A C A B B D C
August 14, 2006
+
=
D
25
Defect Avoidance as a Resource Allocation Problem A C A B B D C
+
=
D
Embedding problem (graph monomorphism) August 14, 2006
26
But, many ways to create circuits… 3-bit adder B2 A2 -B2 -A2
-A0 -A1 -A2 B2 -B0 A1 A2 B1 -B1 -B2 A0 B0 S2 S1 S3 S0
-A1 -B1 B1 A1 A0 B0 -A0 -B0
S2 S3 S1
S0
Multi-level diode logic
August 14, 2006
2-level diode logic
27
Example: tic-tac-toe • • • • • • • • • • • • • • • • • • •
int game3Response(int moveNumber, int humanMove) { int response; if (moveNumber == 1) response = I; else if (moveNumber == 2) { if (humanMove == E) response = G; else response = E; } else if (moveNumber == 3) { if (humanMove == D) response = H; else response = D; } return response; }
. . .
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Target: defective diode crossbar
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29
Tic-tac-toe compiled onto target
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30
2-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 28 x 24 rel. area = 1.0
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
31
2-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 32 x 28 rel. area = 1.3
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
32
2-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 40 x 38 rel. area = 2.3
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
33
2-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 48 x 48 rel. area = 3.4
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
34
2-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 56 x 58 rel. area = 4.8
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
35
2-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 80 x 78 rel. area = 9.2
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
36
2-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 96 x 96 rel. area = 13.7
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
37
Area = f(defect rate) 10 8
2-level
4
2
1 0% August 14, 2006
10% 20% Defective junctions (stuck open)
30% 38
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 24 x 32 rel. area = 1.0
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
39
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 28 x 40 rel. area = 1.5
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
40
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 32 x 48 rel. area = 2.0
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
41
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 40 x 56 rel. area = 2.9
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
42
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 48 x 64 rel. area = 4.0
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
43
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 56 x 80 rel. area = 5.8
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
44
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 64 x 96 rel. area = 8.0
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
45
multi-level logic 1.0 Prob. of successful allocation
( 20 compiles per point)
.5 80 x 112 rel. area = 12
0 0%
10%
20%
30%
Defective junctions (stuck open) August 14, 2006
46
Area = f(defect rate) 10 8
2-level
4 multi-level 2
1 0% August 14, 2006
10% 20% Defective junctions (stuck open)
30% 47
4-bit microprocessor… target: Routing
Bidirectional Buffers
Logic Fabrics
August 14, 2006
48
…compiled onto defective mosaic:
August 14, 2006
49
4-bit microprocessor mapping algorithms 3.0
relative area
6 inputs
2.0
4 inputs
1.0 8 inputs
0 2
4
6
8
10
12
14
16
18
20
% defects
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50
Fault Tolerance •
Error correction
•
Error detection
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51
Triple Modular Redundancy (von Neumann)
x y
f (x, y)
August 14, 2006
z
52
Triple Modular Redundancy (von Neumann) Voter assumed reliable! x ⇒voter small f (x, y) z y ⇒coarse-grained
f (x, y) x f (x, y)
majority vote
z
y f (x, y)
August 14, 2006
53
What if voters are flaky?
August 14, 2006
54
What if voters are flaky? •
Probabilistic approach
•
Each logic signal Æ “fuzzy” value (0…1)
0.0
August 14, 2006
0.5
1.0
55
What if voters are flaky? •
Probabilistic approach
•
Each logic signal Æ “fuzzy” value (0…1) false
0.0
August 14, 2006
0.5
1.0
56
What if voters are flaky? •
Probabilistic approach
•
Each logic signal Æ “fuzzy” value (0…1) false
0.0
August 14, 2006
true
0.5
1.0
57
What if voters are flaky? •
Probabilistic approach
•
Each logic signal Æ “fuzzy” value (0…1) false
0.0
August 14, 2006
mostly true
0.5
1.0
58
What if voters are flaky? •
Probabilistic approach
•
Each logic signal Æ “fuzzy” value (0…1) mostly false
0.0
August 14, 2006
mostly true
0.5
1.0
59
What if voters are flaky? •
Probabilistic approach
•
Each logic signal Æ “fuzzy” value (0…1) mostly false
0.0
August 14, 2006
failure!
0.5
mostly true
1.0
60
Parallel Restitution (von Neumann)
x
f (x, y)
z
y
1. Replace each wire with “bundle” August 14, 2006
61
Parallel Restitution (von Neumann) x1 x2 x3 x4 f (x, y) y1 y2 y3 y4
z1 z2 z3 z4
1. Replace each wire with “bundle” August 14, 2006
62
Parallel Restitution (von Neumann) x1 x2 x3 x4 f (x, y) y1 y2 y3 y4
z1 z2 z3 z4
2. Replace function with redundant version, F August 14, 2006
63
Parallel Restitution (von Neumann) x1 x2 x3 x4 F(x, y) y1 y2 y3 y4
z1 z2 z3 z4
2. Replace function with redundant version, F August 14, 2006
64
Parallel Restitution (von Neumann) x1 x2 x3 x4
f (x, y)
majority vote
z1
Each signal becomes a f (x,bundle y) of N signals.
majority vote
z2
majority vote
z3
majority vote
z4
random permute flaky!
y1 y2 y3 y4
Voters can be f (x,=>y)fine-grained.
f (x, y) F(x, y)
August 14, 2006
65
Self-correcting circuits
in 1
encode
in 2
encode
f
h
decode
out
g
Error correcting code
August 14, 2006
66
Self-correcting circuits
in 1
encode
in 2
encode
f
h
decode
out
g
Do efficient codes exist?
Error correcting code
Add, multiply, shift Æ yes! Others Æ no! August 14, 2006
67
Self-checking circuits inputs
logic function
encoded output
check symbol generator
output
totally self-checking checker error indication
Error detection is cheaper than correction:
Execute machine cycle.
If no errors: latch results, advance state machine,
Otherwise restart current cycle.
August 14, 2006
68
Example: self-checking circuit +V
(a) 3-bit incrementer
in
3
+1
3
inputs
out
in2 -in2 in1 -in1 in0 -in0 out2 out1 out0
outputs
(b) 3-bit incrementer with error detection
in
+1
3
parity predictor
3
out2 out1 out0
parity generator
p
g
totally self-checking equality checker error indicator
August 14, 2006
out
in2 -in2 in1 -in1 in0 -in0
parity predictor p parity generator totally self-checking equality checker
g
error indicator: 1 0 Æ correct
69
Unconventional Stuff
August 14, 2006
70
Hysteretic Resistors
Current (μA)
10
5
0
-5
-10 -2.0
-1.0
0.0
1.0
Voltage (V)
August 14, 2006
71
Hysteretic Resistor Latch (voltage)
Opposite “polarities”
August 14, 2006
72
Hysteretic Resistor Latch (voltage) Enable
August 14, 2006
ControlA ControlB
73
Hysteretic Resistor Latch (voltage) Enable
August 14, 2006
ControlA ControlB
74
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
75
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
76
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
77
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
78
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
79
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
80
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
81
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
82
Programming Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
83
Output Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
84
Output Mode (non-inverting) Enable
ControlA ControlB
0 1 1 0 0 0 1 1
0 August 14, 2006
1 85
Output Mode Enable
ControlA ControlB
0 1 1 0 0 0 1 1
August 14, 2006
86
Output Mode (inverting) Enable
ControlA ControlB
0 1 1 0 0 0 1 1
1 August 14, 2006
0 87
Hysteretic Resistor Latch (impedance encoding)
But wait… only need one hysteretic resistor: • •
Open Æ logic 1 Closed Æ logic 0 August 14, 2006
88
2-bit counter: strange diode-logic, impedance-encoded latches φ2 R
bit0 bit1
August 14, 2006
φ1
89
Logic with Hysteretic Resistors?
What if all you had were hysteretic resistors? Can you do logic as well as latches?
August 14, 2006
90
Logic with Hysteretic Resistors?
What if all you had were hysteretic resistors? Can you do logic as well as latches?
YES August 14, 2006
91
Logic with Hysteretic Resistors? Catches
Must destroy some junctions to “stuck open”
Complex driving signals
August 14, 2006
92
Circuit
A A B B Y = AB + AB input AB AB OR gate, latch out latch August 14, 2006
93
Circuit
A A B
= good junction
B Y input AB AB OR gate latch out latch August 14, 2006
94
Latch inputs
A A B B
input latch August 14, 2006
95
Latch inputs
A A B B
input latch August 14, 2006
96
Close First Minterm Switches
A A B B
input AB latch August 14, 2006
97
Close First Minterm Switches
A A B B
input latch August 14, 2006
98
Compute minterm 1
A A B B
input AB latch August 14, 2006
99
Latch minterm 1 result
A A B B Y = AB input AB latch August 14, 2006
100
Open minterm 1 switches
A A B B Y = AB input latch August 14, 2006
101
Close minterm 2 switches
A A B B Y = AB input latch August 14, 2006
102
Compute minterm 2
A A B B Y = AB input latch August 14, 2006
AB 103
Accumulate Results
A A B B Y = AB + AB input AB AB OR gate latch out latch August 14, 2006
104
Open minterm 2 switches
A A B B Y = AB + AB input AB AB OR gate latch out latch August 14, 2006
105
Read output latch
A A B B Y = AB + AB input AB AB OR gate latch out latch August 14, 2006
106
Hysteretic Resistor Systems
Logic
August 14, 2006
Routing
Logic
107
Demo—software tools •
Development environment
•
Compiler (C code Æ nanocircuits)
•
Logic simulator
•
SPICE simulator
These will be open sourced
August 14, 2006
108
Questions and Answers
August 14, 2006
110
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