Microelectronic Engineering 82 (2005) 497–502 www.elsevier.com/locate/mee
Nickel-silicide process for ultra-thin-body SOI-MOSFETs M. Schmidt a,*, T. Mollenhauer a, H.D.B. Gottlob a, T. Wahlbrink a, J.K. Efavi a, L. Ottaviano b,c, S. Cristoloveanu c, M.C. Lemme a, H. Kurz a a
Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, Huyskensweg 25, 52074 Aachen, Germany b CNR-IMM Dezione Catania, Stradale Primosole 50, 95121 Catania, Italy c IMEP-ENSERG, 23 rue de Martyrs, Grenoble, France Available online 18 August 2005
Abstract A self-aligned nickel-silicide process to reduce parasitic source and drain resistances in ultra-thin-body silicon-oninsulator (UTB-SOI)-MOSFETs is investigated. An optimized nickel-silicide process sequence including nickel sputter deposition, rapid thermal diffusion and compatible silicon nitride (Si3N4) spacers is demonstrated in UTB-SOI n-MOSFETs. Transistor on-currents and source/drain-resistivity are extracted from output and transfer characteristics and compared for various device layer thicknesses from 80 nm down to 15 nm. On-currents are improved up to a factor of 100 for the thinnest transistors by the introduction of self-aligned NiSi. Front and back gate interface qualities are extracted to evaluate their potential impact on mobility and on-currents specifically for ultra-thin devices. 2005 Elsevier B.V. All rights reserved. Keywords: Nickel silicide; Salicide; Ultra-Thin-Body (UTB); SOI-MOSFET
1. Introduction Scaling of CMOS transistors has reached a point, where new materials and new architectures are needed to fulfil the requirements set by the International Technology Roadmap for Semiconductors (ITRS) [1]. Silicon on insulator (SOI) is a promising material for future nanoscale CMOS *
Corresponding author. Tel.: +49 241 8867 232/207; fax: +49 241 8867 571. E-mail address:
[email protected] (M. Schmidt).
circuits, especially if the thickness of the top-silicon or device layer is scaled far below 100 nm. Devices manufactured on such ultra-thin SOI are fully depleted in the off-state and exhibit superior short channel behaviour compared to bulk silicon or even partially depleted, thick SOI [2]. A major concern with ultra-thin-body (UTB) SOI MOSFETs is a large parasitic source to drain resistance due to extremely thin top-silicon films (see schematic in Fig. 1(a)), which severely limits device on-currents and performance. Promising solutions to reduce the resistivity are raised source
0167-9317/$ - see front matter 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2005.07.049
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Fig. 1. Schematic of an ultra-thin body MOSFET on SOI material (a) and an illustration of electrical shorts between the source/drain and gate region (‘‘bridging’’) (b).
and drain areas manufactured by selective epitaxy [3], by self-aligned polysilicon [4] or by self-aligned silicidation [5]. Nickel silicide has excellent electrical properties and has been investigated for reduction of source/ drain resistivity [6] and as gate electrodes for next generation nano-CMOS devices [7]. In this work, a self-aligned nickel silicide process for source and drain leads of UTB MOSFETs on SOI is studied. Electrical parameters such as on-currents, source/ drain resistivity and front and back interface trap densities are discussed for different devices with top-silicon thicknesses down to 15 nm.
2. Device fabrication UTB MOSFETs have been fabricated using SOI-material with a buried oxide thickness (BOX) of tBOX = 200 nm and a top-silicon film in Æ1 0 0æ orientation of tSi = 100 nm. The channel has been implanted with a Boron dose of 7E + 12 ions/cm2 at 18 keV, followed by a rapid thermal anneal (RTA) at 1100 C for 4 min in inert ambient. The top-silicon layers have been thinned down to 80, 60, 30 and 15 nm, respectively, using dry oxidation and subsequent HF wet etch. The top-silicon etching for source, channel and drain ‘‘mesa’’ definition has been achieved with an Oxford Plasma Lab 100 reactive ion etching (RIE) tool. A gate oxide of tox = 8 nm has been thermally grown followed by low pressure chemical vapour deposition (LPCVD) of a 150 nm polysilicon gate. A highly selective HBr etch process has been used to define the active gate areas [8].
Self-aligned arsenic (As) source/drain double implantations have been adjusted to correlate with the top-silicon-thicknesses with adequate conditions shown in Table 1. All samples have been annealed (RTA) at 900 C for 45 s in inert ambient to achieve source and drain doping concentrations of 1E + 20 ions/cm2. A silicon nitride (Si3N4) spacer has been formed by deposition of an LPCVD Si3N4-layer and a subsequent highly anisotropic RIE-process using CHF3 and O2 to eliminate electrical shorts (bridging) between the source/drain and the gate region (see schematic in Fig. 1(b)). The samples have then received an HF-dip to remove the native oxide, followed by a nickel (low damage) sputter process at a precisely controlled deposition rate of 0.04 nm/s. The thickness of the nickel film has been chosen to match the respective top-silicon layers according to reaction equation (1) [9]. 1 nm Ni þ 1.84 nm Si ! 2.2 nm NiSi.
ð1Þ
NiSi formation has been achieved by rapid thermal processing for 30 s at 500 C in N2 ambient. The unreacted nickel film on buried oxide and the sidewalls of the Si3N4 spacer has been removed Table 1 Conditions for source/drain implantations for different topsilicon thicknesses tSi (nm)
Dose (ions/cm2)
Energy (keV)
80 60 30 15
5.00E + 15 5.00E + 15 5.00E + 15 5.00E + 15
50/90 45/50 35/40 20/25
Step1/Step2
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Fig. 2. Scanning electron micrograph cross sections of a NiSi layer after silicidation of 30 nm of Nickel on 100 nm top-silicon film (a) and of a silicided MOSFET structure (b).
by selective wet chemical etching in an H2O2 + H2SO4 (1:3) solution. Reaction equation 1 is confirmed in a scanning electron micrograph cross section of an SOI-sample in Fig. 2(a), which has been silicided to a NiSi thickness of TNiSi = 65 nm using 30 nm of Ni on 100 nm top-silicon. In Fig. 2(b), a scanning electron micrograph of a resultant nickel-silicided MOSFET structure is shown. The source of the transistor is fully silicided, while the thicker polysilicon gate is only partially silicided. Thus, the gate resistivity is reduced as a beneficial side effect. No diffusion under the Si3N4 spacer occurred during silicidation, indicating no excess of nickel and thereby confirming excellent process control during sputter deposition.
3. Experimental results and discussion All measured transistors have gate lengths of L = 2 lm and gate widths of W = 20 lm. Output and transfer characteristics have been measured before and after nickel silicidation using an Agilent Parameter Analyser (4156B). Fig. 3(a) shows typical output characteristics – drain current IDS against source/drain voltage VDS – of an n-MOSFET on 15 nm top-silicon without nickel silicidation. The output characteristics after silicidation are shown in Fig. 3(b). In both cases, the drain/ source-current is standardised to channel width W. The punch through (PT) effect appears at a VDS about 2 V lower after silicidation compared to non-silicided samples (see Figs. 3(a) and (b)).
Fig. 3. Output characteristics of a fully silicided UTB SOI n-MOSFETs on 15 nm top-silicon with gate lengths of Lg = 2lm before (a) and after (b) silicidation. Transfer characteristics of the same devices (c).
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S/D-resistance [Ohm]
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Fig. 4. Improvement factors for top-silicon thicknesses between TSi = 15 nm and TSi = 80 nm (a). Comparison of source/drainresistances before and after silicidation (b).
While the applied source/drain voltages VDS are equal for both cases, the S/D-resistance is much lower after silicidation. The effective voltage at the gate/drain overlap and – consequently – the effective lateral field across the channel is therefore much higher in the case of silicided MOSFETs, resulting in the earlier onset of punch through observed. In order to compare the transistors with different top-silicon thicknesses, on-currents (Ion) have been extracted for all devices before and after silicidation at VGS = 2 V and VDS = 6 V as indicated in Figs. 3(a) and (b). In case of tSi = 15 nm, the oncurrent is 0.136 lA/lm before and 13.17 lA/lm after silicidation. The transfer characteristics of these devices in Fig. 3(c) show well behaved MOSFET operation and indicate a pronounced increase in on-currents. For these transistors (MOSFETs), the on-current is nearly two decades higher for silicided source/drain leads compared to implanted leads. The subthreshold swing S, which indicates the sharpness of the transition from off- to on-state in the transfer characteristics is S = 64 mV/dec in both cases. This is an excellent value nearly matching the ideal value of S = 60 mV/dec at room temperature. The result of Ion after silicidation divided by Ion before silicidation is defined as ‘‘improvement factor’’. It has been extracted for all MOSFETs investigated and plotted against top-silicon thickness tSi in Fig. 4(a). For thicker SOI films, Ion gain by sil-
icidation is much less pronounced than for thin SOI: The improvement factor for tSi = 80 nm is 4 compared to 97 for tSi = 15 nm. The on-current is mainly limited by the total transistor resistance, which in turn mainly consists of the parasitic lead resistance and the channel resistance. For further analysis, the total transistor resistance between source and drain has been extracted from the linear slope in the output characteristics. It is plotted in logarithmic scale against different top-silicon thicknesses before and after silicidation in Fig. 4(b). While the absolute value for thin SOI is higher than for thick SOI, the silicidation process yields a larger improvement of the source/ drain resistance of a factor of 33 for tSi = 15 nm compared to a factor of 7.8 for tSi = 80 nm. As with on-currents, the benefit is larger for UTB MOSFETs. Since the silicidation process only affects the parasitic leads, a larger improvement for thin SOI films hints at excessively high S/D lead resistance in the implanted silicon due to non-uniform dopant distribution in the thinner films. This is overcome by the formation of metallic nickel-silicide with a stronger impact for thinner SOI. The second contribution to the total S/D resistance, the channel resistance, strongly depends on channel electron mobility l. It has been shown that the mobility in ultra-thin-body MOSFETs is affected much more by the interface between the BOX and the top-silicon film than in conventional, thicker SOI devices [10]. Therefore, the electrical
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Fig. 5. Front gate transfer characteristics for various back gate voltages (VG2) (a) and back gate transfer characteristics for various front gate voltages (VG1) (b) for interface trap density extraction.
quality of both gate oxide/top-silicon and top-silicon/BOX interfaces, reflected by the subthreshold slope S and the interface trap density Dit, have been investigated. The front gate subthreshold swing S1 is described by the following equation kT C it1 C Si 1þ S 1 ¼ 2.3 þ a1 . ð2Þ q C ox1 C ox1 Here k is the Boltzmann constant, T is the absolute temperature, Cox1 is the gate oxide capacitance, Cox2 is the BOX capacitance, Cit is the interface trap capacitance and CSi is the silicon film capacitance. a1 is an interface coupling coefficient: ox2 þC it2 a1 ¼ CSiCþC including BOX capacitance ox2 þC it2 Cox2, which accounts for the influence of backinterface traps and BOX thickness on front channel current [11]. The back-gate subthreshold swing S2 is described by replacing Cox1, Cit1 and a1 with their counterparts for the BOX interface Cox2, Cit2 and a2. The front and back gate transfer characteristics – drain current ID versus front and back-gate voltage (VG1 and VG2), respectively – measured at room temperature and a constant source/drain voltage of VDS = 50 mV for an n-MOSFET on 60 nm top-silicon is depicted in Figs. 5(a) and (b). From these graphs, the subthreshold slopes for front and back interfaces have been extracted. The subthreshold swing for these transistors are S1 = 79 mV/dec for the front gate and S2 = 775 mV/dec for the back gate. In addition, S1 and S2 have been used to derive the interface-
trap density Dit1,2 = Cit1,2/q. Cit1 can be neglected with respect to Cox1 for the calculation of a2. With known Cit1Dit2 and a1, Dit1 can be obtained from equation (2). The interface trap density values calculated for transistors with tSi = 60 nm are Dit1 = 4 · 111 cm2 eV1 and Dit2 = 5 · 1011 cm2 eV1. Even though these values show a comparable gate oxide quality of the two interfaces, the close proximity of the second interface (BOX/ top-silicon) to the inversion channel in the 15 nm thin UTB MOSFETs is suggested to be responsible for lower on-currents due to mobility degradation.
4. Conclusions In this work, a self-aligned nickel silicide process for ultra-thin-body SOI-MOSFETs has been successfully demonstrated. An increase of transistor on-currents Ion with a factor of up to 100 after silicidation has been observed. This gain is much more pronounced if the top-silicon thickness is decreased and this is attributed to dopant fluctuations in non-silicided source/drain leads in UTB MOSFETs with tSi = 15 nm. Even though it has been shown that the BOX/top-silicon interface has a comparable quality to the front gate oxide interface, a reduction of on-currents in thinner devices despite source/drain silicidation is attributed to the presence of the second interface in close proximity to the inversion channel. These results
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show the viability of using fully silicided source/ drain leads to alleviate resistivity issues and point out potential intrinsic limitations of UTB SOI MOSFETs. Acknowledgements Financial support by the Bundesministerium fu¨r Bildung und Forschung (bmb+f) under contract number 01 M 3142 A ‘‘KrisMOS’’ and by the European Commission under the frame of the Network of Excellence ‘‘SINANO’’ is gratefully acknowledged.
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