Novel design for testability schemes for CMOS ICs

i C r f JOURNAI OF SOI ID-STATF CIRCUIT\, V O L . 25, NO.

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Novel Design for Testability Schemes for CMOS IC’s MICHELE FAVALLI, P I E R 0 OLIVO, MAURIZIO DAMIANI, BRUNO RICC6, MEMBER, IEEE

Abstract -This work presents novel ideas to improve design for testability (DIT) of CMOS digital IC’s. In particular, two new techniques are suggested for non-stuck-at faults that avoid the drawbacks of previous solutions. Furthermore, an original method is proposed for on-line detection of delay faults, so far not yet considered in the context of DIT. All suggested schemes require limited extra hardware and minimal degradation of circuit performance.

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when in the faultless circuit it would be V, = V,, or YO= 0, respectively). In this case, the restandardized signal leads to a logic error that can be detected at the primary outputs by means of suitable test patterns. Often, however, the signal degradation is weak enough (because the resistance of the faulty conductive paths is large) for the analog voltage to be on the correct side of V,L, thus no logic error is produced and the faults cannot I. INTRODUCTION be detected with conventional testing procedures [11-[41. EST PATTERN generation methods and design for Nevertheless, this type of fault is important because it can testability (DFT) techniques are still largely con- degrade the circuit dynamic performance and should conceived for the detection of faults (such as stuck-ats) result- sequently be considered in order to improve circuit ing in logical errors in the circuit steady-state response. quality. The signal degradation described above can be proUnfortunately, these faults represent only a part of the duced by different physical causes such as gate oxide actual failures degrading the performance of real circuits [l], [2]. Consequently, there is a problem in detecting shorts or failures typically modeled as transistor stuck-on faults that do not result in logical errors. This work or bridging faults [ll-[3]. Fig. l(a) and (b) shows two examples of undetectable presents novel DFT techniques that significantly improve analog faults: a transistor stuck-on in the pull-down netfault detection in CMOS circuits. Failures not described by means of stuck-at models can work of a CMOS NAND gate, and a bridging between two be classified into two large categories (partially coincid- NAND outputs to be used as the input of a NOR gate, ing), hereafter called analog and delay faults. The first respectively. If we assume n- and p-channel devices to includes all types of failure giving rise to degraded electri- have approximately the same conductance when ON, in cal signals (under static conditions) corresponding to volt- Fig. l(a> the gate output voltage Y,, lies on the correct side of the gate threshold voltage because the resistance ages different from the ideal cases of power supply (V,,) or ground. Such a degradation is produced by the pres- of the faulty pull-down network is much larger than that ence of faulty conductive paths from V,, to ground, of the pull-up branch. Under the same conditions for the leading to analog voltage distributions along circuit transistor conductances, in Fig. l(b) the shorted outputs will be driven above VTL because of the higher conducbranches. Because of the high voltage gain of CMOS gates, with tance of the pull-up network. Consequently, the NOR the propagation of signals through a few successive logic output will remain at logic ZERO, as in the fault-free levels, the degraded signal voltages are rapidly standard- circuit. The other category of cases of interest concerns the ized to V,, or 0 and this process can result in two so-called delay faults [5]-[7],namely failures resulting in different cases. If the fault-induced degradation is very strong (depend- correct signal transitions which take place too late (after ing on the resistance of the faulty conductive path), the the end of a sampling period determined by the edge of a analog signal voltage (V,,) can end up on the wrong side clock command). This type of fault can be the conseof the gate logic threshold (i.e., Vor < V,, or VOf> VTL, quence of the analog faults mentioned previously, but it can also be produced by other failures such as increased resistance of correct conductive paths due to faulty device Manuscript received November 30, 1989; revised March 31, 1990. threshold voltages [7]. M. Favalli, P. Olivo, and B. Ricc6 are with the Department of Electronics, DEIS, University of Bologna, 40136 Bologna, Italy. Delay faults can be detected at primary outputs (PO’s) M. Damiani is with the Center for Integrated Systems, Stanford (by monitoring circuit timing) if the line at which they University, Stanford, CA 94305. IEEE Log Number 9037789. occur is directly accessible or sampled by internal memory

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(b) Fig. 1. Examples of undetectable analog faults. (a) The transistor stuck-on in the pull-down network, if activated, leads to an intermediate output voltage lying on the correct side of the gate threshold voltage (because of the higher conductance of the pull-up network). (b) The shorted line voltage (Vof > VTL)does not produce a logical error at the NOR Output because the conductance of the pull-up network prevails on that of the pull-down circuit.

elements and then propagated as steady-state errors to able solutions E91 and by presenting no undetectable sinPO’s. Even in these cases, however, problems may arise gle faults capable of affecting the circuit behavior. In fact, the previous approach [9] proposed for detectbecause of masking by complex 1/0 circuitry, ATE inaccuracies, and unavoidable uncertainities on the sample ing analog faults substantially improves circuit testability, but presents some drawbacks in that it introduces subtime of internal flip-flops. In this paper we consider both analog and delay faults stantial modifications in the network logic design (by and present new DFT techniques conceived for their inverting each gate output) in order to correctly propadetection. In particular, the next section introduces two gate the faulty values, and it presents faults in the testing schemes to detect static analog faults (regardless of their circuitry that can be detected only by means of current position with respect to the gate logic threshold) that monitoring. In particular, the drawbacks due to modificaavoid the high-resolution measurements needed for “cur- tions are rather serious because the required modificarent monitoring” [8], which in practice is not applicable tions put severe constraints on design style, which in most because of nonnegligible static currents due to reverse cases prevents circuit optimization. junction leakage. Such techniques improve the state of The two solutions proposed in this work (Section 11) do the art by removing some major drawbacks of the avail- not suffer from problems due to design modifications, and

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the faults in the added circuitry are either detectable or have no effects on the normal operation of the circuit. Moreover, compared with [9], both methods lead to smaller hardware overhead, and the second technique also results in shorter testing time. With regard to delay faults, all proposed DFT approaches [101-[12] make use of latches. Furthermore, they do not allow testing during the circuit normal operating mode. These drawbacks are overcome by the simple and versatile circuit proposed in this paper (Section 111). 11. DFT

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ANALOG FAULTS

The techniques described in this section operate under static conditions and present substantial advantages compared with the method of [9] because they do not require any modification of the circuit logic structure. As a consequence they are compatible with any design style as well as being easily applicable to already designed logic networks.

Fig. 2. Modified gate for analog fault testability. The control lines f and tdown in test mode are alternately set at intermediate voltaig values to make MI and M , suitably resistive.

its correct ground value can be easily detected by driving tdown with a suitable intermediate voltage I/fdmun (for inA. Conr3ersion of Analog Faults into Stuck-ats stance = V,, -2IV,J, where I / f p denotes the threshold of The method suggested here operates by altering the p-channel devices). In the proposed schemes, the values of yupand I/fd,,, ratio between the output voltage of faulty gates and VTL, so that stuck-ons and bridgings become equivalent to in conjunction with the geometry of the transistors M I stuck-at faults. The implementation of the proposed tech- and M , determine the minimum value of the conductance of the faulty path that can be detected. nique is shown in Fig. 2. The DFT scheme of Fig. 2 presents two undetectable In normal mode both FET’s MI and M z are conducting (since t u , and tdownare at logic ZERO and ONE, faults, namely M I and M 2 stuck-on. They, however, do respectively), thus they have no effect on the gate logic not alter the gate behavior in normal mode, while in test function. In this case the only drawback is the induced mode they can produce masking problems only in the case degradation of the gate switching performance to be of multiple analog faults. traded off for area occupation. In test mode, instead, suitable intermediate voltages B. Distributed Testing Logic are applied to either M , or M , so that the involved devices become significantly more resistive than in normal The technique presented in this section is schematically operating conditions. illustrated in Fig. 3. In essence, CMOS gates are modified To illustrate the scheme’s operation, let us first con- with the insertion (between ground and the n-channel sider the problem of faults that lower the gate high networks) of n-channel FET’s ( M , ) whose drains (nodes output voltages (in the faultless circuits = V,,) such as, represent the inputs of a NOR gate realized with for instance, the examples shown in Fig. 1. To detect n-channel drivers M,, and a p-channel pull-up device these faults, with tu, and tdownat their normal values, an M T L . Such a gate can be designed as a noncritical ratioed input pattern must first be applied to activate the faulty logic as shown in Fig. 3 or, alternatively, as a dynamic conductive path. Successively an intermediate voltage V , gate (for improved speed and accuracy). In the latter case UP (for instance = 2V,,, where V,, denotes the threshold of the p-MOSFET M,, used to precharge the NOR output can be driven by the signal i. n-channel devices) is applied to tu?. Under this condition, the resistive path (including M , ) For simplicity, let us first describe the circuit operation and that through the faulty network try to drive opposite assuming that the NOR sensing gate is designed as a static values at the output. If the resistance of M , is sufficiently ratioed logic element. In normal mode the control line t high, the final outcome of the conflict between pull-up is at logic ONE, so all M , transistors are ON while M,, is and pull-down networks is that the output voltage will be OFF (hence no power is dissipated in the testing network). driven below VTI-,and the fault is then made essentially Thus the only effect of the DFT circuitry is an increase of equivalent to a stuck-at 0. parasitic capacitances. In test mode the circuit operates in the following way: On the contrary, if no fault is present the output will, of course, remain high. It is obvious that, with complemen- the command signal t is first set to O N E and suitable test tary type of operations, faults raising the gate output from patterns are applied to activate the possible faults; succes-

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Fig. 3. Schematic representation of the distributed testing logic suggested for analog fault detection. The transistors M,, and M,, represent the drivers and the load of a ratioed NOR gate used for testing.

sively t is switched to ZERO. If no fault is present, no conducting path is established between the power supply and the nodes N,, that consequently remain at logic ZERO. Hence, all the drivers of the test NOR are OFF and ttest is high. On the contrary, in the case of a fault realizing a connecting path through the pull-down and pull-up networks of the CMOS circuit, Nlow can be charged to a high value, thus M , becomes conducting and ttest is lowered to logic ZERO. The circuit presented in Fig. 3 requires extra hardware constituted by two lines (control and test line, t and ttest, respectively) and two FET's for each gate (while the resistive load can be shared). The proposed DFT circuit presents two untestable device faults, namely M , stuck-on and M,, stuck-open. These, however, do not affect the gate behavior in normal mode, although possibly masking other (hence multiple) faults. The design of the ratioed NOR gate is noncritical since the input voltage due to the presence of a fault will rise to a high value ( = V,, - yn)regardless of the resistance of the faulty path, thus making it possible to also detect transistor stuck-on at resistive values that represent a problem for the technique presented in Section 11-A. With our method the number of test patterns required for analog fault detection is drastically reduced, since test vectors are only required to activate the faults. Moreover, since only a single transistor is inserted in series to the pull-down network, the gate dynamic behavior is minimally altered. In CMOS implementations featuring small logic networks, more gates can share M , (and then M,,), thus reducing the number of extra devices and undetectable faults. In this case, M , must be suitably designed to avoid dynamic problems.

C. Comparison of the Two Methods A comparison of the two methods described in Sections 11-A and B shows that: a) both techniques are practically equivalent in terms of area overhead, essentially due to added devices and wiring, in the former and the latter case, respectively; b) the second technique presents a smaller degradation of dynamic performance since only one series transistor is added; c) in the first technique a test vector must satisfy fault activation and propagation conditions. In the second, however, since the presence of a fault is directly observable at the outputs of the testing circuitry, only fault activation is necessary and this results in shorter test sequences; d) the second technique is particularly suitable in structured design approaches (because extra NOR'S can be easily placed), while the first can be conveniently used to modify existing designs. 111. DFT

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As shown in Fig. 4, delay faults are due to transitions on critical lines (typically PO's and state variables) occurring after a valid sampling time (in the figure determined by the falling edge of the clock 4). This type of fault has not yet been adequately considered in the context of DFT, therefore we are presenting a technique that, with limited extra hardware, allows delay times (tdelay) < 1 ns to be detected. The circuit, to be derived from the output of combinational blocks (as illustrated in Fig. 5), is shown in Fig. 6.

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The devices M , and M , are controlled by the clock VDD-V TN phases and $ 2 =&,respectively, whiIe the monitored signal S controls the CMOS gate formed by MA and M B . 0 For a correct operation, the capacitance (C,) at node N should be at least four times larger than those (C,) at tsmplc tr nodes NA and NB. Fig. 7. Schematic timing diagram used to operate the circuit of Fig. 5. Such a circuit operates essentially in the following way. The transitions (rising and falling) of and (see Fig. 7) mark the end of valid “reading” time (tsample) and and OFF, respectively, hence the voltages at nodes NA and switch off transistors M , and M,. Two possibilities are NB are VNA= V,, and VNB= 0 while V, = V D D . When S then in order: rises both MA and M B change their state, hence nodes N a) if no delayed transition of the signal S occurs at and NB are connected through M B . A charge-sharing t > T,,,~,~, nodes NA and N, remain in their previ- process then takes place and V, rises to a high value because of the large capacitance ratio C,/C,. ous state (at V,, and ground, respectively); and Fig. 7 shows a diagram of the resulting waveforms with b) if, instead, S (because of a delay fault) changes after a capacitance ratio C,/C, = 4 that is enough for the M , and M2 have been turned off, a change occurs NB to reach the maximum possible value voltage at node in the circuit output nodes NA and NB. V,, - yn. It is easy to verify that a fault leading to a As an example of this latter case, let us assume that S delayed falling transition of S results in a final low value rises at tf -- tsample tdelay.At t < t f , MA and M B are ON

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The induced change in VNAor VNFcan then be detected with the simple scheme shown in Fig. 8 where the added NAND and NOR gates can be driven by lines coming from different sensing circuits. In this scheme, the presence of a delay fault will be revealed by the output of final NOR going to 0. The time accuracy of the sensing circuit and its sensitivity to possible skews in the transition of 4 , and + 2 have been studied by means of SPICE simulations. The analysis has shown that, if 41 and 42 change simultaneously, delays in the subnanosecond range can be easily revealed (the main limitations in this case come from transistor switching times). In the presence of clock skews, a delayed transition of S may occur between those of c $and ~ 4 ~In~ this . case a delay fault may not be detected. This is the case in the example illustrated in Fig. 9, where a delay on the falling transition of S is not detected. In fact, when MA is switched ON, a charge-sharing process between nodes N and NA takes place, but since M , is still ON, node NA is recharged and only a voltage glitch is produced.

The number of undetectable delay faults can be made negligibly small by: a) optimizing clock distribution throughout the chip; and b) using dynamic schemes for the NAND and NOR gates of the testing network, as illustrated in Fig. 10 where 4, and 42 are used to precharge the gates output. In order to explain the advantages of this latter scheme, let us refer again to the timing diagram of Fig. 9. If the voltage glitch on VNA is large enough, a p-channel MOSFET in the pull-up network of the dynamic NAND is switched ON, thus charging the gate output. In this way, with suitable transistor design, the scheme can be made almost insensitive to clock skews. The technique described above is not affected by inaccuracies introduced by 1 / 0 circuitry or connections to testing instruments. Furthermore, it presents several advantages compared with the detection of delay faults by means of flip-flops [lo]-[12] because it: a) introduces smaller inaccuracies (especially with respect to latches); b)

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detecting delay faults during the circuit normal operating mode. IV. CONCLUSIONS

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This paper presents novel ideas on the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the steady-state response). In particular, two techniques are proposed for the detection of analog faults, namely those resulting in intermediate voltages along circuit branches due to faulty conductive paths between the power supply and ground. These techniques remove important limitations of the methods already available in the literature. In addition, a last method is presented for the detection of delay faults, namely those resulting in correct signal transitions taking place after the sampling time. This technique is able to operate during normal circuit operation. All the proposed techniques require little extra hardware and lead to minimal performance degradations. REFERENCES

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(b) Fig. 10. Dynamic NAND/NOR schemes that can be used at the output of the sensing blocks of Fig. 6 in order to reduce the effects of clock skews.

requires a significantly smaller area overhead; and c) directly detects a delayed transition as an error, without any comparison with the expected circuit response. This last point is extremely important because, with this method, the detection of delay faults does not require that the state of sampled lines be compared with expected values, thus making it possible to operate during the IC’s normal working mode. For this reason, the proposed scheme represents a classical application of built-in self test (BIST), for the first time addressing the problem of

R. L. Wadsack, “Fault modeling and logic simulation of CMOS and NMOS integrated circuits,” Bell Syst. Tech. J . , vol. 57, pp. 1449-1474, 1978. J. Acken, “Testing for bridging faults (shorts) in CMOS circuits,” in Proc. Design Automation Conf., 1983, pp. 717-718. J. M. Soden and C. F. Hawkins, “Test considerations for gate oxide shorts in CMOS ICs,” IEEE Design & Test, vol. 3, pp. 56-63, Aug. 1986. D. Baschiera and B. Courtois, “Testing CMOS: A challenge,” K S I Syst. Design, vol. 5, pp. 58-62, 1984. C. Lin and S. M. Reddy, “On delay fault testing in logic circuits,” in Proc. IEEE Int. Conf. Computer Aided Design, 1986, pp. 148-151. Y. Malaiya and P. Narayanaswany, “Testing for delay faults in synchronous sequential circuits,” in Proc. IEEE Int. Test Conf ., 1985, pp. 34:-349. S. Koeppe, Modeling and simulation of delay faults in CMOS logic circuits,” in Proc. IEEE Int. Test Conf., 1986, pp. 530-535. Y. K. Malaiya and S. Y. H. Su, “A new fault model and testing technique for CMOS devices,” in Proc. IEEE Int. Test Conf., 1982, pp. 25-34. D. Liu and E. McCluskey, “Designing CMOS circuits for testability,” IEEE Design & Test, pp. 42-49, 1987. Y. Malaiya and P. Narayanaswany, “Testing for timing faults in synchronous sequential integrated circuits,” in Proc. IEEE Int. Test Conf., 1983, pp. 560-571. S. Kundu, S. Reddy, and N. Jha, “A method of delay fault test generation,” in Proc. IEEE Int. Conf. Computer Aided Design, 1988, pp. 240-243. S. Devadas, “Delay test generation in synchronous sequential circuits,” in Proc. IEEE Int. Test Conf., 1989, pp. 144-152. Michele Favalli received the Dr. Eng. degree in electrical engineering from the University of Bologna, Bologna, Italy, in 1987. Since 1987 he has been working in the Department of Electronics at the University of Bologna as a Research Assistant, currently supported by a grant from SGS-Thomson. His research interests are in the area of IC testing, including design for testability, pseudorandom testing, fault simulation, and modeling. Piero Olivo was born in Bologna, Italy, in 1956. He graduated in 1980 from the University of Bologna, Bologna, Italy, and received the Ph.D. degree from there in 1987.

1246 Since 1983 he has been an Assistant Professor of Applied Electronics at the University of Bologna. In 1986-1987 and the autumn of 1989 he was a Visiting Scientist at the IBM Thomas J. Watson Research Center. His scientific interests are in the area of solid-state devices, including SiO, physics, electron transport and trapping through thin SiO, structures, oxide breakdown and reliability, MOS measurements techniques, and thin oxide properties. He is now also interested in IC testing, with emphasis on design for testability and fault simulation.

Maurizio Damiani received the Dr. Eng. degree in electrical engineering from the University of Bologna, Bologna, Italy, in 1987 He is currently working towards the Ph.D degree at Stanford University, Stanford, CA. From February 1987 to August 1988 he was with the Department of Electronics, University of Bologna, as a Research and Teaching Assistant. His research interests are in the area of logic synthesis and testing, including design for testability and built-in self-test techniques, high-level synthesis, and coding theory.

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Mr. Damiani received an AEI Scholarship and a Rotary International Fellowship in 1988 and 1989, respectively.

Bruno Ricc6 (M’85) was born in Parma, Italy, in 1947. In 1971 he graduated in electrical engineering from the University of Bologna, Bologna, Italy, and in 1975 received the Ph.D degree from the University of Cambridge, England, where he had been working at the Cavendish Lab. In 1980 he became Full Professor of Applied Electronics at the University of Padova, Italy. In 1983 he joined the Department of Electronics of the University of Bologna. In 1981 he was a Visiting Scholar at the University of Stanford and, later, at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. His scientific interests concern solid-state devices and integrated circuits. In particular, he has worked on electron transport in polycrystalline silicon, tunneling in heterostructures, silicon dioxide physics, hot-electron effects in MOSFET’s, latch-up in CMOS structures, and Monte Carlo simulation. He is also interested in circuit design and testing. Prof. Ricc6 was appointed Associate Editor for Europe of the IEEE ON ELECTRON DEVICESin 1988. TRANSACTIONS