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Reconfigurable Systems for Digital TV Environment Article · July 2012
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3 authors: Rodrigo Ribeiro de Oliveira
Eddie Filho
Envision AOC, Brazil
Federal University of Amazonas
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Reconfigurable Systems for Digital TV Environment Rodrigo Ribeiro de Oliveira
Eddie Batista de Lima Filho
Vicente Ferreira de Lucena
Universidade Federal do Amazonas Centro de Ciênc., Tec. e Inov. do PIM Universidade Federal do Amazonas Av. Rodrigo Octávio J. Ramos, 3000 Rua Salvador, 391 69057040, Av. Rodrigo Octávio J. Ramos, 3000 69077000, Coroado I. Manaus, AM Adrianópolis, Manaus, AM 69077000, Coroado I. Manaus, AM +55(092)81143441 +55(092)21235833 +55(092)81586371
[email protected]
[email protected]
ABSTRACT This paper details the current status of the development of a complete methodology for reconfiguring a receiver through the Digital TV broadcast signal. This project aims the design of platforms with reconfigurable features, whose goal is to minimize the legacy (old devices) that arises when deploying a new transmitting system. The reconfiguration of the FPGA is performed through a bit stream containing the synthesized hardware, which is transmitted as generic data embedded in the digital TV multiplex. The methodology used in the reconfiguration process and the partial results obtained during the update process are presented in this paper. As a result, future revisions in digital television standards could take place without immediately replacing the reception devices.
Categories and Subject Descriptors B.4.1 [Data Communications Devices]: Receivers (e.g., voice, data, image), Transmitters.
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Most digital TV Set-Top Boxes (STB) available in market use a common hybrid system strategy, with modules developed in hardware, like video decoders, silicon tuner and demodulators, and also in software, running on higher-capacity processors [2]. Thus, the preparation of the system for being capable of upgrade should be performed during the design phase, according to the intended system framework. In order to synthesize a code, written in a hardware description language such as Very High Speed Integrated Circuit HDL (VHDL) or Verilog, it is necessary to use a Computer Aided Design (CAD) tool. The result of this process is a bit stream containing the hardware description. In the context of a digital television (DTV) system, the bit stream can be regarded as data that is transmitted along with the HDTV content of the television program (Figure 1). A DTV system is composed of several blocks, which include data preparation for transmission and complete signal reception, with subsequent content filtering.
General Terms Algorithms, Design, Standardization.
Keywords SBTVD, HDTV, DTV, FPGA, VHDL, VERILOG, NRE e DATACASTING.
1. INTRODUCTION Currently, the Field Programmable Gate Array (FPGA) plays a more dominant role in integrated systems design, mainly due to higher demands in logic capacity and on-chip resources. The new generation of FPGAs overcame limitations presented by the Moore's law, and now these devices are capable of meeting most design requirements [12]. The use of FPGAs was boosted by the semiconductor industry, due to the development of several Hardware Description Language (HDL) examples codes, which are normally provided in modules and can be directly incorporated into other projects. Besides, there also are bit streams synthesized for different architectures and HDLs for circuit simulation, test and validation [3] [6]. Another important issue is that the current FPGA cost is similar to the ASIC one, which is essentially given by the amortization of the cost of Non-Recurring Engineering (NRE) among customers of each integrated circuit (IC) family [3]. It then reinforces the use of FPGAs in embedded systems design, in such a way that the lifecycle of the final product becomes easier to control.
Figure 1 - Transmission of the hardware reconfiguration stream. The transmitted information is usually composed of audio, video and data packets; the latter, in the present work, carry the hardware reconfiguration data. The generation of the reconfigurable stream is performed during the FPGA Module Synthesis Step (Figure 1(a)). In this step, the FPGA module is synthesized and, after passing test procedures, the resulting bit stream is ready to be sent. The hardware reconfiguration stream, which is part of the generic data, may be encapsulated by a mechanism of datacasting (see Section 2). In the TS multiplexing step, audio, video and data (which include the hardware description) are interleaved, which
gives rise to a Transport Stream (TS), which is necessary for transmitting information in a DTV system [1]. Finally, in the transmission step (Broadcaster), the resulting signal is then modulated and sent through the DTV channel. On the other side, Figure 1(b), the receiver detects and decodes the signal. The result of this initial process then goes through the demultiplexing step, which extracts audio, video and data packets, while part of the latter is used for reconfiguring the FPGA. The reconfiguration is performed through user interaction, with the aid of a resident control system, present in the STB, which notifies users when new updates are available. When an update is triggered, the system retrieves the reconfiguration stream and reassemblies it in a persistent storage module. Following that, the FPGA is automatically restarted, now with a new operation description.
STB236, which is based on the PNX8735 processor. The PNX has a Digital Signal Processor (DSP) responsible for decoding video, whose output is then routed to the video encoder output (Digital Encoder - DENC, which provides signals suitable to the standards adopted in a given country), before reaching the analogto-digital conversion, and also to the digital outputs subsystem (e.g. HDMI).
This article is divided into five sections. The next one, which is section 2, contains a brief explanation about data broadcast and the mechanisms for signal transmission and reception. Section 3 discusses the reconfigurable modules and the technologies related to this process. All concepts presented earlier are then used in the formulation of the case study, in section 4. Section 5 contains the concluding remarks.
2. DATA BROADCAST Data broadcast (datacasting) is one of the most interesting features of a digital TV system and offers the opportunity to make a more intelligent use of the channel bandwidth, allowing the delivery of generic data to receivers located in the coverage area. As the MPEG-2 is the standard adopted for multiplexing data in open DTV systems, the existing mechanisms make use of its facilities and structures for providing datacasting services. There are four known transport mechanisms: data piping [9], data streaming [9][10], multiprotocol encapsulation (MPE) [8][10] and Carousels, which are divided in data carousels and object carousels [9][10].
3. RECONFIGURABLE MODULES
Figure 2 – Reference design platform STB236 The front-end, which is composed by a PLL, a demodulator and peripheral devices, performs the reception of the transmitted signal (air interface) and outputs a TS. Following that, when the TS reaches the back-end (processors and decoders), it is demultiplexed, separating audio, video and data. The demultiplexer filters the TS, through filters based on packet identifiers (PID2), and sends the resulting data to suitable processing modules. In order to create a new architecture, the target device (receiver) must integrate a FPGA circuit and a FLASH memory (deployed in the grid area), which is illustrated in Figure 3. This architecture was prepared for reconfiguring the H.264 video decoder using a FPGA.
The electronics industry is adopting hardware reconfiguration in several products [9]. In the digital TV segment, FPGAs has been used for implementing some functions of the receiver, like time control and output interfaces [7]. Recently, research projects seen in [4] and [5] have shown the use FPGAs for decoding video H.264 [11]. In [5], research efforts regarding H.264 video decoding aim to join efforts for developing intellectual property for the Brazilian Digital Television System (SBTVD1). Also, the target device (FPGA) used for the synthesis process was a XILINX Virtex-II Pro XC2VP30; resources required for this process include 21,200 LUTs, 8465 slices, 5671 registers, 21 internal memory modules and 12 multipliers. In [4], the target device used in the validation process and also for testing was a XILINX Virtex-II 2VP30FF896 – Pro. The results were satisfactory and indicate that these devices can be used in DTV receivers. Figure 3 - Architecture with FPGA integrated
4. CASE STUDY AND RESULTS In this case study, it was considered the update of the H.264 video decoder module, given that it is possible to transmit any synthesized FPGA module through datacasting. The base platform (reference design – Figure 2) used in this project was the NXP -
In order to perform this task, it is necessary to synthesize the H.264 video decoder [11] to a specific FPGA model and generate the bit stream. After that, the reconfiguration stream must be multiplexed with the digital TV content (audio and video). The transport stream multiplexing is performed using any multiplexing
1
2
SBTVD – Brazilian System of Digital Television.
PID – Packet Identifier.
tool. For enabling the hardware reconfiguration (the upgrade of the H.264 decoder [11]) feature, which is the focus of this study, the transmitted data are regarded as bounded and can be divided into a finite number of slices of predetermined size, before being fed to the transport mechanism. Besides, from the perspective of timing requirements, the data are asynchronous, because the bit stream does not need any synchronization with other data types or media elements.
of module types allowed by the synthesizable core type field of a UIT.
After evaluating many possible mechanisms for transporting data, the streaming through private sections was chosen for the present work. The mechanism for data streaming via private sections is simpler and provides tools for error detection, ensuring system reliability. In addition, it also offers support to asynchronous and bounded data and uses less complex structures when compared to carousels. Among the selection criteria that were taken into consideration, it is worth noticing that some of the most important ones were the necessary computational resources, implementation complexity and packaging strategy (multiplexing) of the TS. By adopting the data streaming mechanism through private sections, the reconfiguration bit stream can be broken up into sections of 4084 bytes of payload, plus 8 bytes of header and 4 bytes of CRC, which are then tagged according to the slice insertion order (each 4084 bytes of data) of the bit stream. This mechanism also allows the adjustment of the section repetition rate. Thus, the reconfiguring application running on the receiver is able recover the transmitted information, in the original order established by the encapsulation process. After the transport stream generation procedure, it is necessary to employ a broadcast system for transmitting the related content, using a specific channel.
Table 3 shows the core description sent by the broadcaster. The field manufacture_id informs the manufacture of the FPGA (e.g. Xilinx-Virtex II, etc) intended to be updated. The HDL_used field holds the name of the HDL used during the module synthesis procedure (e.g. VHDL, Verilog, etc), and the target_device field presents the device type for which the core was synthesized (e.g. 2VP30FF896-Xilinx).
The resident software is responsible for controlling sections/tables filtering and finding hardware updates, which are accomplished in a systematic way. So, a new table was created to make the receiver aware of a reconfiguration stream, which is called update information table (UIT) (Table 1), whose goal is to broadcast the availability of an update regarding video decoding and the PID of packets carrying the reconfiguration bit stream.
Table 2 – Description the field synthesizable_core_type. Synthesizable_core_type 0x0000 0x0001 0x0002...0x7FFF
Description reserved_future_use H.264 Syntetizable Decoder Undefined
Table 3 – Description of the update_identifier field. Data structure update_identifier (){ manufacture _id HDL_used target_device }
Bit rate 16 8 16
Bit string uimsbf uimsbf uimsbf
After filtering this table, the PID of the reconfiguration stream is retrieved (see data flow, Figure 4). This then allows the download of the bit stream, through a PID filter allocated in the demultiplexer. The download is done directly in FLASH memory, which is then followed by a data reassembly procedure, ensuring the correct organization of the reconfiguration file. Finally, with the binary file (bit stream) correctly recorded in memory, the processor then restarts the FPGA-based system, which makes the new decoder operational. After completing the reconfiguration process, video decoding is restarted and then video packets are sent to the FPGA through a standard interface (e.g. DVB-CI – Common Interface or USB 2.0).
Table 1 – UIT -- Update Information Table. Data Structure update_information_table(){ table_id section_syntax_indicator reserved_future_use reserved section_length synthesizable_core_type section_number last_section_number reserved_future_use reconfiguration_data_PID Reserved update_loop_length for (i=0; i
