S-UMTS Processor Key Technologies demonstrator

S-UMTS Processor Key Technologies Demonstrator Christopher Topping, Andrew Bishop, Tony Craig, David Howe and Jesse Hamer Astrium Ltd. Gunnels Wood Road, Stevenage Hertfordshire SG1 2AS, UK [email protected]

Piero Angeletti

Alan Senior

European Space Agency Keplerlaan 1, 2200 AG Noordwijk The Netherlands [email protected]

SEA (Group) Ltd. Beckington Castle 17 Castle Corner Somerset BA11 6TA, UK [email protected]

Abstract— The S-UMTS Processor Key Technologies demonstrator (built under ESA contract 16024/02/NL/JA) is a Digital Signal Processor (DSP) prototype demonstrating a number of architectures and technologies relevant to the next generation of mobile missions. An advanced testbed capable of simulating a variety of antenna types has been constructed. Two beamforming techniques are implemented and preliminary test results are presented.

I. INTRODUCTION It is clear that future mobile satellite missions will feature ever larger antenna systems and provide higher capacity. As the number of beams grows, improved beamforming capabilities are required in addition to greater flexibility both in routing between beams and in frequency planning. The demands of such complex missions are best satisfied with Digital Signal Processors (DSPs) such as the Astrium Inmarsat 4 processor [1]. The increasing functionality of the processor will require advances in processor technologies and architectures. The key objective of the ESA S-UMTS Processor Key Technologies contract (16024/02/NL/JA) is to examine processor technologies and architectures relevant to this next generation of mobile missions. This ESA S-UMTS project is split into three phases that are responsible for the analysis, design and implementation of a laboratory demonstrator for a next generation mobile communications processor. The first phase of the project performed an analysis of the requirements for future mobile communications satellites, in particular the processor and antenna. Various scenarios were examined for L-band and Sband frequencies providing either regional or global coverage. The types of carriers examined varied from 200 kHz TDMA to 5 MHz CDMA depending on the coverage and frequency band. The general overview of a digital processor for this type of application comprises channelisation, beamforming, switching and recombination of the channels. Contiguous channelisation permits a wideband signal to be routed and beamformed as a number of separate sub-channels. A transparent processor of this type is thus effectively independent of the air interface used. Although the project was envisaged in the context of SUMTS, the algorithms and architecture remain relevant to the next generation of standards.

As the number of antenna elements and processed bandwidth increases, the complexity of the beamforming becomes increasingly significant. A key area of study was new methods of beamforming that would allow a reduction in the overall processor complexity. To meet the varying mission requirements, two different antenna types were examined: the Direct Radiating Array (DRA) and the Array Fed Reflector (AFR). In the case of a general multiple-element antenna, beamforming is accomplished by multiplying the signal from each antenna element by a complex weight and summing over all elements. However, it is possible to reduce the arithmetic complexity of beamforming for both of the above antenna types through the use of suitable beamformer architectures. For the AFR, each beam is formed using a subset of the total number of feeds. A new type of beamformer architecture, designated as a matrix beamformer, has been designed to exploit this property by only processing those feed signals which contribute to the required beam. This minimises the number of multiplications required. In the case of the DRA, however, all elements are generally required for forming every beam and the efficiency gains of the matrix beamformer are lost. Fortunately, the constant phase gradient across the DRA, which is required to form a spot beam in the far-field, permits an architectural simplification: rather than multiplying by a coefficient for each element, it is possible to use an FFT to achieve the same result with reduced complexity. The disadvantage of using an FFT for beamforming is that the size, shape and locations of the beams are fixed for a given FFT/antenna combination and not all beams may be useable in the required coverage region. Use of an oversized FFT, where the number of antenna elements is less than the FFT dimension, can provide more beams with reduced spacing. However, this is achieved at the cost of increased complexity in the beamformer and a loss of beam orthogonality. The second phase of the project was responsible for the detailed design of the laboratory demonstrator. This work has been the catalyst to a series of further improvements/upgrades of the latest processors including the High Throughput processor [2], [3] and the Alphasat processor. The design work that has been undertaken in this second phase comprises detailed implementation of the processor algorithms and detailed design of hardware for the demonstrator and special test equipment.

The third phase of the project is close to completion at time of writing (July 2008). The hardware has been manufactured and validated, the test systems have been implemented and the functional performance testing is nearly complete.

II. SYSTEM ARCHITECTURE The demonstrator architecture (illustrated in figure 1) is a substantial and representative subset of the return half of a complete processor. Two mobile side modules, each containing eight ADC/demux pairs, allow the processing of analogue inputs from 16 notional antenna elements. Inmarsat 4 uses 120 antenna elements so the input processing capacity of the demonstrator represents more than 10% of a realistic processor for mobile communications. The ADC sampling rate is 112 MHz giving a useful bandwidth of 50 MHz (sufficient to cover the extended L-band mobile satellite services bandwidth). This is significantly greater than the 30 MHz bandwidth of Inmarsat 4. The demuxes divide the incoming spectrum into 280 200 kHz channels and output the complex samples for each channel on two 140 slot TDMs. The channelisation process is contiguous allowing wideband signals to be routed as multiple separate sub-channels. The demuxes can also produce critically sampled, non-contiguously routable 800 kHz channels. The feeder module contains two beamformers with identical interfaces. Normally these are configured as a matrix beamformer and an FFT beamformer but could both be the same type if required. There is no architectural difference between the two beamformer types outside of the beamformer block itself. Both beamformers can be operated simultaneously. Each beamformer is connected to both mobile modules via high speed serial links. More high speed serial links within the feeder module carry the beamformer output data. All modules contain a TDM mux which performs time and spatial switching in addition to level control functions. For the purposes of testing, the FFT beamformer actually contains three selectable FFTs: a 7 point hexagonal FFT (implemented as a single one-dimensional FFT), a 12 point 3N2 hexagonal [4] FFT (implemented as a 2x2 FFT followed by a 3 point FFT), and a 16 point (4x4) square FFT. In order to test larger antenna and beamformer sizes, the demux functions can be replaced by signal generators which each simulate 10 antenna elements and their associated demuxes (but produce fewer channels). The muxes are replaced by self-contained measurement blocks in this configuration. In this digital test mode, no use is made of the DACs or ADCs and processing is limited to switching and beamforming. The digital test mode supports the use of larger FFTs for beamforming: a 127 point hexagonal FFT (onedimensional), a 147 point 3N2 hexagonal FFT (a 7x7 FFT followed by a 3 point FFT), and a 144 point (12x12) square FFT. The matrix beamformer can be used without major modification in both analogue and digital testing modes; the number of elements used is entirely flexible. The matrix beamformer can be used with either an AFR or a DRA antenna

although it can produce more beams for the same arithmetic complexity when used with an AFR. III.

HARDWARE IMPLEMENTATION

The S-UMTS Processor Key Technologies Demonstration Hardware (SDH), designed, manufactured and tested by SEA (Group) Ltd, is a full implementation of the architecture described in section II. The SDH consists of a rack containing three cards (corresponding to the feeder and two mobile modules) connected via a simple backplane. Each component shown in figure 1 is implemented as a Xilinx Virtex-II Pro FPGA. The FPGAs are programmed using JTAG with different designs being loaded for the analogue and digital test modes. The ADCs and DACs are clocked at 112 MHz; data entering the demuxes is deinterleaved by two thus enabling the FPGAs to operate at a clock rate of 56 MHz. The ADCs and DACs are 12 bit devices whose performance exceeds that of an ideal 9 bit converter. Data samples are represented as 20 bit signed complex numbers between the demuxes and muxes. Each beamformer FPGA has 20 incoming high speed serial links (10 from each mobile module via the backplane) and 10 outgoing links to the feeder side TDM mux. The high speed serial links are implemented using multi-gigabit transceivers internal to the FPGAs which operate at 1.12 Gbps and use 8b/10b coding. The actual data throughput (accounting for encoding overhead) is 4.48x107 20 bit words per second per link or 35 Gbps across the complete backplane. The front panel of the SDH is shown in figure 2. It is important to note that the use of FPGAs allows for complete reconfiguration of the hardware to use entirely different algorithms and to perform different or additional functions if desired. The top level system architecture is generic and modular but is supplemented by additional inter-FPGA data buses in hardware (which are not used in the current design). These open the possibility of spreading functionality across FPGAs in future designs. IV.

TEST SYSTEM

The primary function of the test system is to verify correct operation of the beamformers and to assess their performance. The strategy adopted consists of simultaneously driving all inputs to each beamformer with signals from a simulated DRA or AFR antenna illuminated by a set of sources. The simulated antennas used are: Analogue mode •

7 element hexagonal DRA (7pt FFT BFN)

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12 element 3N2 hexagonal DRA (12pt FFT BFN)

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16 element square DRA (16pt FFT BFN and matrix BFN)

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16 element AFR (matrix BFN)

Digital mode •

127 element hexagonal DRA (127pt FFT BFN)

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147 element 3N2 hexagonal DRA (147pt FFT BFN)

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144 element square DRA (144pt FFT BFN)

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160 element AFR (matrix BFN)

The individual elements of the DRA antennas are taken to have a gaussian radiation pattern with 3 dB roll-off at 9° from the boresight direction. This approximation is in good agreement with the behaviour of real phased-array elements within the angle of interest. By scanning the sources across the field of view of the simulated antenna and measuring the output power in each beam, it is possible to construct images of the beam shapes and locations for each beamformer. Performing tests of this type requires that all of the analogue inputs to the SDH have a well defined phase and amplitude relationship to each other since each represents an element of the same antenna. Measurement of the analogue outputs in addition to command of the SDH itself is also required. A.

Test Equipment The principal test equipment (shown in figure 3) consists of eight rack-mounted Arbitrary Waveform Generators (AWGs) with three independent outputs each, and a dual-input Vector Signal Analyser (VSA). The AWGs are modified Racal 3153 devices with a maximum sampling rate of 100 MS/s (all channels) giving a usable bandwidth of 40 MHz. Sample precision is 12 bits and each device can store two megasamples of waveform data. The VSA is an Agilent 89600 which also operates at 100 MS/s with 12 bit resolution thus offering similar bandwidth and dynamic range to the AWGs. The AWGs and the VSA are entirely controlled by the instrument control computer which in turn receives commands from the main control computer. The AWGs are supplied with a common 100 MHz sampling clock and make use of a daisychained trigger signal so that the relative phase of each output can be precisely controlled. The AWG sampling clock, the SDH clock and the VSA clock are all locked to the same reference. In addition to commanding the instrument control computer, the main control computer also performs configuration of the SDH via three RS232 links. Variation in phase (due to trigger propagation delay) and output level between AWG instruments must be calibrated out. This is accomplished by using the VSA to compare the first AWG output to each other output while the AWGs play a calibration waveform consisting of many tones of equal nominal amplitude. The resulting measurements of amplitude and phase error versus frequency are used to generate calibration files which are used by the signal generation software. Simpler tests not requiring the full test system are performed using a network analyser (for channelisation tests) or a signal generator and spectrum analyser (for DAC/ADC evaluation tests). B.

Test Software The software on the instrument control computer consists of two programs written in VEE (an Agilent scripting language for instrument control) which present simple network interfaces for performing the required measurement operations.

The majority of the software runs on the main control computer and is responsible for performing automated testing and collation of results. A block diagram of the test software system is given in figure 4. The SDH control server manages reading and writing of data to and from the SDH coefficient RAMs. The RAMs contain the routing and beamforming configuration and, in the digital testing mode, the measured results and signal generation parameters. The two far field emulators calculate the required waveforms for each simulated antenna element given a set of antenna files (GRASP format) and source parameters including location, frequency and amplitude. The Analogue Far Field Emulator (AFFE) sends the calculated waveforms to the instrument control computer for loading into the AWGs and extracts measurements from the returned VSA data. The Digital Far Field Emulator (DFFE) uses the SDH control server to configure and trigger the digital sources and to read back the results from the measurement blocks. The test sequencer reads databases detailing sets of tests to be performed and issues the necessary commands to the SDH control and far field emulator software. Results are collated and written to a single file. The test sequencer enables potentially thousands of tests to be performed without user intervention. C.

Test Scenarios Initial tests not related to beamforming include the input and output processed band tests. These tests evaluate the flatness of the response across the entire usable bandwidth of the ADC/demux and the DAC/mux respectively. For the input processed band test, the input signal contains a tone placed at the centre of each demux bin. The SDH is configured to route every demux bin in turn to a single output bin. By measuring this output signal for each configuration it is possible to plot the response of the ADC and demux with respect to frequency. The output processed band test consists of routing a single input tone to each output bin and measuring the power at each frequency. This characterises the response of the DAC and mux with respect to frequency. Channelisation tests using a network analyser are used to measure the channel shape and contiguity. In this case, the SDH is configured to route a single channel or group of contiguous channels straight through without beamforming or frequency translation. The network analyser sweeps a tone across the band of interest and measures the transmitted power through the SDH. The channel shape measured using this method is the product of the demux and mux channelisation functions. The primary beamforming tests are the beam imaging tests which are conducted as follows: first, a grid of tone sources is set up across the antenna’s field of view. The sources are separated in frequency such that each source falls into a separate demux bin. The SDH is configured to form all beams for each source frequency and to output the signal in each beam on a separate channel. In this way, each source facilitates the measurement of the response of every beam for that location. In order to build a sufficiently high-resolution image of the beams, the source grid must be scanned around the field

of view to generate a larger composite grid as shown in figure 5. The entire process is fully automated by the test sequencer software so the only limiting factor on test complexity is the overall time taken. Once sufficient data have been collected, plotting and further analysis of beam shapes and locations is carried out. The sources are positioned and the beams are plotted using the u,v coordinate system which maps out the solid angle corresponding to the antenna’s field of view. The coordinates u and v are defined in terms of the antenna-centred polar coordinates θ and φ as follows: u = sinθcosφ v = sinθsinφ u,v coordinates can be thought of as the projection of a unit vector in the specified direction onto the x,y–plane of the antenna. Additional beamformer tests carried out in digital mode are the beam degradation test and the beam weight quantisation test. In the first case, errors are deliberately introduced into the antenna emulation parameters to simulate differences between the analogue paths to and from the antenna elements in a real system. The beam weight quantisation test is performed by using progressively fewer bits to describe the coefficients used by the matrix beamformer. In both tests the effect on beam position, width and sidelobe levels is measured. V.

TEST RESULTS

The results presented here are for the basic setup of the system and the analogue tests of the beamformers. These demonstrate that the system is working and show some interesting results for the FFT beamformer. The processed band tests showed both the input and output passband flatness to be better than ±0.3 dB. The network analyser results for a single 200 kHz channel and a group of 10 contiguous channels forming a 2 MHz block are shown in figure 6. The 3 dB points for the single channel fall at ±97 kHz from the channel centre and the flatness within the central 180 kHz is better than ±0.15 dB. Variation within the 10 channel block is less than ±0.17 dB. Figure 7 contains a plot of the cross section (u = 0) through a beam produced by the 16 point FFT beamformer using the 16 element square antenna. The measured data points are plotted against a software simulation of the beamformer function (using the same antenna emulation) and are in excellent agreement. This demonstrates correct functioning of the FFT beamformer and shows that the AWG outputs are coherent and matched in amplitude. Figure 8 is a similar plot using data from the matrix beamformer with the same (DRA) antenna. The matrix beamformer has been configured to produce a beam slightly offset from the nearest FFT beam (also shown). This illustrates the additional flexibility offered by the matrix beamformer in producing beams in arbitrary directions and potentially on a finer grid than the FFT beamformer.

Figure 9 is an interpolated 2-D colour plot of a primary beam produced by the 7 point FFT beamformer; the positions of the six other primary beams and the grating lobes are also plotted. The primary beam pattern is rotated by approximately 19.1° relative to the grating lobe pattern. This is a geometrical effect of using a one-dimensional FFT and a hexagonal element tiling. Note that each beam falls within the nulls of all other beams and it is possible to define a central region covered by 7 beams which is never infringed by grating lobes. This is not the case for the 16 point FFT beamformer. As shown in figure 10, it is not possible to define a region containing 16 unique beams which is centred in the field of view. The same is true of the 12 point FFT (shown in figure 11). Both the 12 and 16 point FFTs produce beams for which the primary and grating lobes are indistinguishable. These beams are unusable for a coverage region which is centred in the antenna’s field of view. This occurs for all even FFTs because it is possible to have a phase difference of π between bins resulting in a beam which is symmetrical about the boresight. VI.

CONCLUSION

The S-UMTS Processor Key Technologies demonstrator implements a number of architectures relevant to the next generation of mobile missions. These include advanced beamforming techniques and a highly flexible routing architecture in addition to the use of high speed serial links within the processor. The demonstrator hardware represents a substantial fraction of the return half of a full scale processor with 16 analogue inputs, all of which are driven by the highly flexible testbed system. Results obtained thus far have been in excellent agreement with simulation and specification. Proposed further work will expand the capabilities of the hardware demonstrator and its testbed enabling even more ambitious algorithms and architectures to be tested. These include digital compensation of phase and amplitude tracking errors (simulated by the testbed) to improve beamformer performance. It is also proposed to implement digital RF sensing and beam pointing correction within the processor to enhance beam-pointing accuracy. REFERENCES [1]

[2]

[3]

[4]

Andrew Bishop, Omar Emam, Lewis Farrugia, Jon Hill, Geoff le Good and Justin Byrne, “Design of the Inmarsat 4 digital signal processor”, ESA SPSC 2003 Conference proceedings. Robert Hughes, Rosalind Warren, Alijah Ahmed, Alan Couchman et al., “High throughput fully processed payload for broadband access networks”, 13th Ka and Broadband Commuunications Conference proceedings. Steven Brown, Robert Hughes, David Howe et al., “Proof of concept of a high-throughput processor for broadband access networks”, proceedings of this conference. G. G. Chadwick, W. Gee, P. T. Lam, J. L. McFarland, “An algebraic synthesis method for RN2 multibeam matrix networks”, Antenna Applications Symposium, 23 Sep. 1981-25 Sep. 1981 Monticello, Il, USA.

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Figure 4. Test software overview Figure 2. S-UMTS Key Technologies Demonstrator Hardware (SDH) Composite Grid IEEE 1394

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Figure 3. Test equipment overview

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Figure 5. Arrangement and scanning of signal sources. Each of the 9 sources shown is placed in a separate demux bin.

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Figure 7. Scanned cross section through the boresight beam produced by the 16 pt FFT beamformer. Measured points (red) are plotted against the simulation (green).

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Figure 8. Scanned cross section through a beam produced by the matrix beamformer (red data points against blue simulation) plotted against the nearest 16pt FFT beam (green).

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Figure 11. 2-D plot of a beam produced by the 12pt FFT beamformer. Positions of the other beams are also shown along with three possible (off-centre) coverage regions.